JPH11163325A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, in which the upper section of an active region is not filled with an insulating film, even if microstinring progresses and which has satisfactory electrical characteristics. SOLUTION: A polysilicon film 7 is formed onto a silicon substrate 1, and a groove section 4 surrounding an active region is formed through the use of the polysilicon film 7 as an etching stopper. An insulating film is deposited on the substrate and planarized, and the groove section is filled with the insulating film and a groove type element isolation 5a is formed. A conductive film 18 is deposited on the substrate, the conductive film 18 and the polysilicon film 7 are patterned, and a lower gate electrode 7a and an upper gate electrode 18a are formed. The element isolation 5a which is not coated with the upper gate electrode 18a is etched selectively, and a stepped section between the element isolation 5a and the silicon substrate 1 is shrunk. An electric field in the lateral direction is not applied to a channel region, because there is a large stepped section under the gate electrodes, and the active region is not also filled with the insulating film because the stepped sections are miniaturized in other regions.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a semiconductor device having a trench isolation type element isolation and an improvement of a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, with the advance of high integration and high performance of semiconductor devices, demands for miniaturization are increasing.
Therefore, there is a technical field in which it is not possible to follow these demands only by improving the conventional technology, and it is necessary to introduce a new technology. For example, as a method of forming element isolation, element isolation has conventionally been formed by the LOCOS isolation method from the viewpoint of simplicity of the manufacturing method and low cost. Recently, however, a trench embedded isolation type has been used to form a finer semiconductor device. (Hereinafter simply referred to as a groove-type element isolation) has been considered to be more advantageous.

That is, since the LOCOS isolation method employs a selective oxidation method, a so-called bird's beak occurs at a boundary with a mask for preventing the oxidation, and the isolation region is located closer to the element region than the actual mask size. Of the insulating film penetrates to cause a dimensional change, and the amount of the change is a value that cannot be tolerated for miniaturization after the 0.5 μm generation. Therefore, in the field of mass production technology, a shift to a trench isolation method with an extremely small dimensional shift has begun.

FIG. 8 shows a conventional trench isolation and MOSFE.
FIG. 9 is a schematic cross-sectional view showing an example of a semiconductor device provided with T, FIG. 9 is a plan view of the semiconductor device, and FIG.
The structure in the cross section of the active region is shown. FIG. 10 is an enlarged cross-sectional view showing the structure in the gate width direction cross section shown in FIG.

As shown in FIG. 8, a trench-type element isolation 105a is formed in a silicon substrate 101. A gate insulating film 103a and a gate electrode 107a are formed on an active region surrounded by the element isolation 105a. Gate electrode 10
The electrode portion sidewalls 108a on both side surfaces of 7a are provided. In the active region, the gate electrode 10
7a, lightly doped source / drain regions 106a and heavily doped source / drain regions 106b
And a channel stop region 115 is provided below the element isolation 105a. Further, an interlayer insulating film 111 made of a silicon oxide film, a metal wiring 112 formed on the interlayer insulating film 111, and a conductive material such as tungsten embedded in a contact hole penetrating the interlayer insulating film 111, Contact portion 11 connecting between metal wiring 112 and source / drain electrode 109c
3 are provided.

Here, in a semiconductor device having such a trench isolation structure, as shown by an arrow in FIG. 10, an electric field is also applied to the channel region from the gate electrode 107a in the lateral direction. There was a possibility that characteristics and the like would be deteriorated.

Therefore, as a technique capable of preventing the above-described problems, as disclosed in Japanese Patent Application Laid-Open No. 9-172603, the upper surface of the trench isolation is made higher than the substrate surface. Techniques for forming structures are known. The manufacturing steps of a semiconductor device having such a trench structure will be described with reference to FIGS.

First, in a step shown in FIG. 11A, a gate oxide film 103 and a polysilicon film 107 to be a gate electrode of a MOS transistor are sequentially deposited on a silicon substrate 101, and an element isolation is formed thereon. The photoresist film 120 that opens the region and covers the active region is patterned. Using the photoresist film 120 as a mask, the polysilicon film 107 and the gate oxide film 103 are selectively removed, and the silicon substrate 101 is etched to form a trench 104 serving as an element isolation region. At this time, the thickness of the polysilicon film 107 is 100 to 200 n.
m, and the thickness of the gate oxide film 103 is about 10 nm. The depth of the groove 104 is about 400 nm.
After that, impurity ions of a conductivity type opposite to the conductivity type of the impurities to be implanted into the source / drain regions to be formed later are implanted, so that the channel stop region 115 is formed. That is, by using different resist masks, the PMOSFE
At T, N-type impurity ions are implanted near the bottom of the trench 104, and at NMOSFET, P-type impurity ions are implanted.

Next, after removing the photoresist film 120, the depth of the groove 104 and the remaining polysilicon film 10 are removed.
7, an insulating film 105 (not shown) having a thickness greater than the height from the bottom of the groove 104 to the surface of the polysilicon film 107 is deposited.
P) to form the insulating film 105 into a polysilicon film 107.
Is removed until the surface of the substrate is exposed, and the entire substrate surface is flattened. By this step, the insulating film 105 is formed in the element isolation region.
Is formed.

Next, in a step shown in FIG. 11B, a conductor film 118 to be a gate electrode wiring layer and a protective film 119 made of an insulating film are deposited on the flattened substrate to form a gate electrode. A photoresist film 121 having an opening in a region other than the region to be formed is formed. Then, this photoresist film 12
Using 1 as a mask, dry etching is performed to pattern the protective film 119a, the upper gate electrode 118a, and the lower gate electrode 107a. At this point, a sufficient step is provided between the surface of the silicon substrate 101 in the active region and the surface of the element isolation 105a, and the step is almost the same as the film thickness of the lower gate electrode 107a.

Next, after an insulating film 108 is deposited on the entire surface of the substrate in a step shown in FIG. 11C, anisotropic etching of the insulating film 108 is performed in a step shown in FIG. Then, an electrode portion side wall 108a is formed on the side surface of the gate electrode 107a and the like. At this time, a step sidewall 108b is also formed on the side surface of the step between the silicon substrate 101 in the active region and the element isolation 105a. Then, impurity ions are implanted in this state to form the high-concentration source / drain regions 106b. Even at this point, the silicon substrate 101 in the active region and the element isolation 105a
And the height difference between the steps is sufficiently ensured.

Although illustration of subsequent steps is omitted, a trench filling type is formed through deposition of an interlayer insulating film 111 and formation of a contact hole, embedding of a metal in the contact hole and formation of a first-layer metal wiring 112. A MOS transistor having an isolation structure is formed.

In the case of such a structure, a high step portion on the element isolation 105a side is formed between the silicon substrate 101 in the active region and the element isolation 105a. Since no electric field is generated and no residue is generated at the time of gate patterning, difficulty in the patterning step can be avoided.

[0014]

However, the semiconductor device having the above-described element isolation of the trench structure has the following problems.

That is, as the miniaturization of the semiconductor device progresses, the design rule becomes 0.25 μm as shown in FIG.
When the distance is equal to or less than m, the source / drain region becomes extremely narrow because the step side wall 108c is formed on the side surface of the element isolation 105a. Alternatively, in a step of performing anisotropic etching for forming a sidewall, that is, when shifting from the state shown in FIG. 11C to the state shown in FIG. There is also a risk of being embedded.

The present invention has been made in view of the above points, and an object of the present invention is to provide a trench type element isolation structure by taking measures for preventing the above-described burying of an active region when forming a sidewall. An object of the present invention is to provide an extremely fine semiconductor device having the same and a method for manufacturing the same.

[0017]

In order to achieve the above object, according to the present invention, there are provided means relating to a semiconductor device according to claims 1 to 7, and a method for manufacturing a semiconductor device according to claims 8 to 11. We have taken steps on how to do it.

According to a first aspect of the present invention, there is provided a semiconductor device, comprising: a semiconductor substrate; an active region provided in a part of the semiconductor substrate; and an insulating material surrounding the active region. , A gate electrode extending over the active region and the groove-type element isolation, and an insulator sidewall formed on a side surface of the gate electrode. In the region below the gate electrode, a step is formed in which the trench-type element isolation is higher than the semiconductor substrate in the active region.
In a region not covered with the gate electrode, a height difference between the trench-type element isolation and the semiconductor substrate in the active region is smaller than the step.

As a result, since the gate electrode on the trench type element isolation always has a structure higher than the semiconductor substrate in the active region, no lateral electric field is applied from the gate electrode to the active region. In a region other than the region below the gate electrode, the height difference between the trench-type element isolation and the semiconductor substrate in the active region is small.
Even in a semiconductor device as fine as about μm or less, a structure in which an active region can be prevented from being buried with the insulator when an insulator sidewall of a gate electrode is formed. Further, even if a sidewall exists at the end of the groove-type element isolation, the height difference between the two is small, so that the lateral dimension of the sidewall can be small, and the area of the active region is widened. Therefore, a semiconductor device having good characteristics suitable for miniaturization can be obtained.

According to a second aspect of the present invention, in the first aspect, the height position of the upper surface of the trench type element isolation in a region not covered with the gate electrode and the height of the upper surface of the semiconductor substrate in the active region. It is preferable that the height position is substantially the same.

According to a third aspect of the present invention, in the first aspect, a height difference between an upper surface of the trench type element isolation in a region not covered with the gate electrode and a semiconductor substrate in the active region. Is preferably not more than の of a step between the trench-type element isolation in a region below the gate electrode and a semiconductor substrate in the active region.

According to a second aspect of the present invention, there is provided a semiconductor device, comprising: a semiconductor substrate; an active region provided in a part of the semiconductor substrate; and an insulating material surrounding the active region. And a gate electrode comprising an upper gate electrode extending over the active region and the trench element isolation, and a lower gate electrode formed only on the active region, and formed on the side surface of the gate electrode. Insulator sidewalls. The height position of the trench-type element isolation upper surface in a region not covered by the upper gate electrode is defined by the height position of the lower gate electrode upper surface and the height position of the semiconductor substrate upper surface in the active region. between.

Thus, since the gate electrode on the trench type element isolation always has a structure higher than the semiconductor substrate in the active region, no lateral electric field is applied from the gate electrode to the active region. In addition, since the upper surface of the groove-type element isolation is located at a position lower than the upper surface of the lower electrode and the height difference between the two is small, even in a semiconductor device whose design rule is as small as about 0.25 μm or less, the insulator side of the gate electrode can be used. When the wall is formed, the active region is prevented from being buried with the insulator. Further, even if a sidewall is present at the end of the trench-type element isolation, the height difference is small, so that the lateral dimension of the sidewall can be small, and the area of the active region can be widened. Therefore, a semiconductor device having good characteristics suitable for miniaturization can be obtained.

According to a third aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate; an active region provided in a part of the semiconductor substrate; and an insulating material surrounding the active region. And a gate electrode formed on the active region and having an upper gate electrode having the same upper surface position as the trench-type element isolation and a lower gate electrode extending from the active region to the trench-type element isolation. And an insulator sidewall formed on a side surface of the gate electrode. In the region below the upper gate electrode, the trench-type element isolation has a step that is higher than the semiconductor substrate in the active region, and is covered with the upper gate electrode. In a region where there is no groove, the height difference between the groove type element isolation and the semiconductor substrate in the active region is smaller than the step.

Thus, since the gate electrode on the trench type element isolation always has a structure higher than the semiconductor substrate in the active region, no lateral electric field is applied from the gate electrode to the active region. In a region other than the region below the gate electrode, the height difference between the groove-type element isolation and the semiconductor substrate in the active region is small.
Even in a semiconductor device as small as the following, a structure in which the active region can be prevented from being buried with the insulator when the insulator sidewall of the gate electrode is formed. Also,
Even if a sidewall is present at the end of the groove-type element isolation, since the height difference between the two is small, the lateral dimension of the sidewall can be small, and the area of the active region is widened. Therefore, a semiconductor device having a gate electrode having a stacked structure and excellent characteristics suitable for miniaturization can be obtained.

According to a sixth aspect of the present invention, in the fifth aspect, the trench-type element isolation in a region not covered with the upper gate electrode and the semiconductor substrate in the active region have substantially the same top surface height. Is preferred.

According to a seventh aspect of the present invention, in the fifth aspect, the height between the upper surface of the trench type element isolation in a region not covered by the upper gate electrode and the semiconductor substrate in the active region is set. It is preferable that the difference be equal to or less than の of the step between the groove-type element isolation in a region below the upper gate electrode and the semiconductor substrate in the active region.

The first method of manufacturing a semiconductor device according to the present invention comprises:
A first step of depositing a protective film on a semiconductor substrate, an opening is formed in the protective film, and a groove is formed by etching the semiconductor substrate in the opening. A second step, a third step of depositing a buried insulating film on the substrate, and etching the buried insulating film until the protective film is exposed, thereby forming a semiconductor device and the trench-type element isolation. A fourth step of forming a trench-type element isolation in which the trench is filled with the filling insulating film so that a step is present between the trench and a conductive film on the substrate after removing the protective film; A fifth step of patterning the conductive film to form a gate electrode extending from the active region surrounded by the groove-type element isolation to the groove-type element separation; Select the part that is not covered by the gate electrode A seventh step of etching, the
An eighth step of forming an insulator sidewall on the side surface of the gate electrode by performing anisotropic etching after depositing a sidewall insulating film on the substrate.

In the semiconductor device formed by this method, a step formed in the fourth step exists between the trench-type element isolation below the gate electrode and the semiconductor substrate in the active region. Therefore, no lateral electric field is applied to the active region. In the seventh step, since the step between the groove-type element isolation in the region other than below the gate electrode and the semiconductor substrate in the active region is reduced, even in a semiconductor device whose design rule is as small as about 0.25 μm or less, the gate can be used. The active region can be prevented from being buried with the insulator when forming the insulator sidewall of the electrode. Therefore, a semiconductor device with good characteristics suitable for miniaturization is formed.

According to the second method of manufacturing a semiconductor device of the present invention,
As described in claim 9, the first on the semiconductor substrate.
A second step of forming an opening in the first conductive film, etching a semiconductor substrate in the opening to form a groove, and embedding the conductive film in the substrate. A third step of depositing an insulating film, and etching the buried insulating film until the first conductive film is exposed;
A fourth step of forming a trench-type element isolation by filling the trench with the filling insulating film so that a step exists between the semiconductor substrate and the trench-type element isolation; A fifth step of selectively etching the isolation, a sixth step of depositing a second conductor film on the substrate, and patterning the first and second conductor films to form the trench-type element isolation. A seventh step of forming a gate electrode extending from the enclosed active region to the trench-type element isolation; and depositing an insulating film for a sidewall on the substrate, and then performing anisotropic etching to insulate the side surface of the gate electrode. Eighth to form body sidewall
Steps.

In the semiconductor device formed by this method, since a step exists between the trench-type element isolation below the gate electrode and the semiconductor substrate in the active region, a lateral electric field is applied from the gate electrode to the active region. It is not applied. Also, in the fifth step, the step between the groove-type element isolation in the region other than below the gate electrode and the semiconductor substrate in the active region is reduced. The active region can be prevented from being buried with the insulator when forming the insulator sidewall of the electrode. Therefore, a semiconductor device having a gate electrode having a stacked structure and excellent characteristics suitable for miniaturization is formed.

According to a third method of manufacturing a semiconductor device of the present invention,
11. A first step of depositing a first conductive film on a semiconductor substrate, forming an opening in the first conductive film, and etching the semiconductor substrate in the opening. A second step of forming a trench by forming a trench, a third step of depositing a buried insulating film on the substrate, and etching the buried insulating film until the first conductive film is exposed. A fourth step of forming a trench-type element isolation by filling the inside of the trench with the burying insulating film so that a step is present between the substrate and the trench-type element isolation; A fifth step of depositing a conductive film, and a sixth step of patterning the second conductive film to form an upper gate electrode extending from the active region surrounded by the trench isolation to the trench isolation. Covered with the upper gate electrode out of the trench type element isolation A seventh step of selectively etching portions that are not present, an eighth step of patterning the first conductive film to form a lower gate electrode, and depositing a sidewall insulating film on the substrate. A ninth step of forming an insulator sidewall on the side surface of the gate electrode by performing anisotropic etching.

In the semiconductor device formed by this method, since the step formed in the fourth step exists between the trench-type element isolation below the upper gate electrode and the semiconductor substrate in the active region, the gate is formed. No lateral electric field is applied from the electrodes to the active region. In the seventh step, since the step between the groove-type element isolation in the region other than below the gate electrode and the semiconductor substrate in the active region is reduced, even in a semiconductor device whose design rule is as small as about 0.25 μm or less, the gate can be used. The active region can be prevented from being buried with the insulator when forming the insulator sidewall of the electrode. Moreover, in the sixth step, the upper gate electrode can be formed in a fully flat state. Therefore, a semiconductor device having a stacked structure and a gate electrode with good shape accuracy and good characteristics suitable for miniaturization is formed.

According to a fourth method of manufacturing a semiconductor device of the present invention,
12. A first step of depositing a first conductive film on a semiconductor substrate, forming an opening in the first conductive film, and etching the semiconductor substrate in the opening. A second step of forming a trench by forming a trench, a third step of depositing a buried insulating film on the substrate, and etching the buried insulating film until the first conductive film is exposed. A fourth step of forming a trench-type element isolation by filling the inside of the trench with the burying insulating film so that a step is present between the substrate and the trench-type element isolation; A fifth step of depositing a conductive film, and a sixth step of patterning the first and second conductive films to form a gate electrode extending from the active region surrounded by the trench isolation to the trench isolation. Process and the trench type element isolation covered with the gate electrode A seventh step of selectively etching portions not present, and an eighth step of forming an insulator sidewall on the side surface of the gate electrode by performing anisotropic etching after depositing a sidewall insulating film on the substrate. Steps.

In the semiconductor device formed by this method, the step formed in the fourth step exists between the trench-type element isolation below the upper gate electrode and the semiconductor substrate in the active region. No lateral electric field is applied from the electrodes to the active region. In the seventh step, since the step between the groove-type element isolation in the region other than below the gate electrode and the semiconductor substrate in the active region is reduced, even in a semiconductor device whose design rule is as small as about 0.25 μm or less, the gate can be used. The active region can be prevented from being buried with the insulator when forming the insulator sidewall of the electrode. Moreover, in the sixth step, the gate electrode can be formed in a fully flat state. Therefore, a semiconductor device having a stacked structure and a gate electrode with good shape accuracy and good characteristics suitable for miniaturization is formed.

[0036]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) First, a first embodiment will be described with reference to FIGS. 1 and 2 (a) to 2 (e). FIG. 1 is a cross-sectional view showing the structure of the semiconductor device according to the present embodiment, and FIGS.
FIG. 2 is a cross-sectional view showing a manufacturing process for realizing the structure of the semiconductor device shown in FIG. 1. However, FIG. 1 and FIG.
In each of (e), the structures in the cross section in the gate width direction, the cross section in the channel direction, and the cross section in the active region shown in FIG. 9 are shown.

In FIG. 1, on a P-type silicon substrate (or well) 1, a groove-type element isolation 5a for dividing a region near the surface of the silicon substrate 1 into a number of active regions is formed. In the cross section in the channel direction and in the cross section of the active region, the upper surface of the element isolation 5a is flattened so as to be substantially the same height as the upper surface of the silicon substrate 1 in the active region. On the other hand, in the cross section in the gate width direction, the element isolation 5a
Is sufficiently higher than the silicon substrate 1 in the active region,
There is a predetermined step (height difference) between the two. The element isolation 5a is formed by embedding an insulating material in a groove formed in the silicon substrate 1 as described later. A channel stop region 15 having a conductivity type opposite to that of the source / drain region is formed at the bottom of the element isolation 5a by ion implantation described later.

The active region surrounded by the element isolation 5a includes a gate electrode 4, a gate oxide film 3, an electrode side wall 8a, a low concentration source / drain region 6
a, a MOS transistor comprising a high concentration source / drain region 6b is formed. Further, the gate electrode 7a
An upper gate electrode 9a and a source / drain electrode 9b made of titanium disilicide (TiSi2) are formed above the high concentration source / drain regions 6b.

The element isolation 5a and the gate electrode 7a
An interlayer insulating film 11 and a first-layer metal wiring 12 are formed on the entire surface of the substrate on which the first-layer metal wiring 12 and the like are formed. And the source / drain electrodes 9b.

Next, a manufacturing process for realizing the structure shown in FIG. 1 will be described with reference to FIGS.

First, in the step shown in FIG. 2A, a silicon oxide film 16 and a silicon nitride film 17 serving as an etching stopper film are deposited on the silicon substrate 1, and a photolithography is performed to open an element isolation region and cover an active region. After patterning the resist film 20, using the photoresist film 20 as a mask,
The silicon nitride film 17 and the silicon oxide film 16 are selectively removed, and the silicon substrate 1 is etched to form the groove 4. At this time, the silicon nitride film 17
Has a thickness of 100 to 200 nm, and the silicon oxide film 1
6 has a thickness of 10 to 20 nm. The depth of the groove 4 is about 400 nm. After that, impurity ions of the conductivity type opposite to the conductivity type of the impurities to be implanted into the source / drain regions to be formed later are implanted to form the channel stop region 15. That is, using different resist masks, the PMOSFET is used to remove N-type impurity ions,
In the NMOSFET, the P-type impurity ions are respectively
Inject near the bottom of the.

Next, in the step shown in FIG. 2B, after removing the photoresist film 20, a value obtained by adding the depth of the groove 4 and the thickness of the remaining silicon nitride film 17, that is, the groove 4
An insulating film (not shown) having a thickness sufficiently larger than the height from the bottom of the silicon nitride film 17 to the upper surface of the silicon nitride film 17 is deposited, and the resulting film is subjected to chemical mechanical polishing (CMP).
Is removed until the upper surface of the substrate is exposed, and the entire substrate surface is flattened. By this step, a trench-type element isolation 5a made of an insulating film is formed in the element isolation region. This flattening method is not limited to this embodiment,
A method of performing etch-back using a reverse pattern of an active region with a photoresist film may be used.

Thereafter, although not shown, the silicon nitride film 17 is removed by using a phosphoric acid boil solution or the like, and the silicon oxide film 16 is further removed by using a hydrofluoric acid-based wet etching solution or the like. The surface of the substrate 1 is exposed. At this time, the distance between the upper surface of the silicon substrate 1 in the active region and the upper surface of the element isolation 5a is 100 to 200 nm.
There is a large step.

Next, in a step shown in FIG. 2C, a polysilicon film 7 is deposited on the silicon substrate 1 and the element isolation 5a, and a region other than a region where a gate electrode is to be formed is opened on the polysilicon film. The formed photoresist film 21 is formed.

Next, in the step shown in FIG. 2D, the polysilicon film 7 is patterned by dry etching using the photoresist film 21 as a mask to form a gate electrode 7a. Further, only the silicon oxide film forming the element isolation 5a is selectively etched in the opening region of the photoresist film 21, and the position of the upper surface of the part of the element isolation 5a that is not covered by the gate electrode 7a is changed to the active region. The height is almost the same as the surface of the silicon substrate 1. The feature of the present embodiment is that it has a step of etching only the element isolation 5a. As a result, a large step exists between the element isolation 5a and the active region in the cross section in the gate width direction. There is no step of about ｎｍ40 nm.

Next, in a step shown in FIG. 2E, an insulating film (silicon oxide film) is deposited on the entire surface of the substrate (not shown), and the insulating film is anisotropically etched to form a gate. An electrode portion side wall 8a is formed on the side surface of the electrode 7a. Then, in this state, impurity ions are implanted,
A high concentration source / drain region 6b is formed.

Although illustration of the subsequent steps is omitted, the upper gate electrode 9a and the source / drain electrodes 9b are formed by the silicide process, the interlayer insulating film 11 is formed, the contact holes are formed, and the metal is buried in the contact holes. Through the formation of the first-layer metal wiring 12, the MOS transistor having the trench-buried isolation structure shown in FIG. 1 is formed.

In the above step, the electrode side wall 8 is formed in order to form a transistor having an LDD structure.
In the transistor having a so-called pocket injection structure in which an impurity of the opposite conductivity type is injected between the source / drain region and the channel region to provide a punch-through stopper, the electrode portion side wall 8a and the like are formed. The present invention is also applied to a transistor having such a pocket injection structure.

When a MOS transistor having a gate length of 0.25 μm or less is formed as in this embodiment, the area occupied by the active region must be reduced as much as possible. However, in the conventional semiconductor device having the stepped trench structure as described above, since the step between the element isolation and the active region is large, the side wall is formed when the active region (source / drain region) is narrowed. Even if the insulating film is anisotropically etched (step shown in FIG. 2E), the insulating film may be buried in the active region. On the other hand, in the present embodiment, in the step shown in FIG. 2D, there is almost no step between the element isolation 5a in the region not covered by the gate electrode and the upper surface of the silicon substrate 1 in the active region. There is no possibility that the active region is buried with the insulating film in the sidewall formation process.
On the other hand, in the state shown in FIG. 1, in the cross section in the gate width direction, the upper surface of the element isolation 5a is higher than the upper surface of the silicon substrate 1 in the active region. No electric field is generated in the horizontal direction. Therefore, miniaturization of the semiconductor device can be promoted without causing a problem in the conventional trench isolation structure with or without a step.

In the manufacturing process of the semiconductor device according to the present embodiment, as compared with the manufacturing process of the conventional stepped trench isolation structure shown in FIGS.
Only the step of reducing the thickness of the element isolation 5a shown in (d) is added. At this time, if the photoresist film 21 is used as it is, the photolithography step does not increase.

In the present embodiment, the silicon nitride film 17 is used as an etching mask for forming the trench 4, but the material of this film may be any material having a smaller etching selectivity than the silicon oxide film. It is also possible to substitute a polysilicon film or the like.

In the present embodiment, an embodiment having a so-called salicide structure in which the upper gate electrode 9a and the source / drain electrode 9b are simultaneously silicided in a self-alignment manner to reduce the resistance has been described. The electrode is formed with a polycide electrode in advance, and the source
Needless to say, a structure in which only the drain electrode is silicided may be employed.

(Second Embodiment) Next, FIGS.
The second embodiment will be described with reference to (a) to (e). 3A to 3E are cross-sectional views illustrating the structure of the semiconductor device according to the present embodiment. FIGS. 4A to 4E are cross-sectional views illustrating a manufacturing process for realizing the structure of the semiconductor device illustrated in FIG. It is. 3 and FIGS. 4 (a) to 4 (e) show the structures in the cross section in the gate width direction, the cross section in the channel direction and the cross section in the active region shown in FIG.

As shown in FIG. 3, on a P-type silicon substrate (or well) 1, a groove-type element isolation 5a for dividing a region near the upper surface of the silicon substrate 1 into a number of active regions is formed. . In the cross section in the channel direction and in the cross section of the active region, the upper surface of the element isolation 5a is flattened so as to be substantially the same height as the upper surface of the silicon substrate 1 in the active region. On the other hand, in the cross section in the gate width direction, the upper surface of the element isolation 5a is sufficiently higher than the silicon substrate 1 in the active region, and there is a step between them. This element isolation 5a
It is formed by embedding an insulating material in a groove formed in the silicon substrate 1 as described later. A channel stop region 15 of a conductivity type opposite to that of the source / drain region is formed at the bottom of the element isolation 5a by ion implantation to be described later.

Then, the element isolation 5a on the silicon substrate 1
, The lower gate electrode 7a, the upper gate electrode 18a and the protective film 19a, the electrode portion side walls 8a formed on the side surfaces of the lower and upper gate electrodes 7a and 18a, A drain region 6a and a high-concentration source / drain region 6b;
A MOSFET comprising a source / drain electrode 9b made of silicide formed on the drain region 6b is provided.

Further, a step portion side wall 8b is formed on the side surface of the step portion between the silicon substrate 1 in the active region and the element isolation 5a. The interlayer insulating film 11 and the first-layer metal wiring 1 are formed on the entire surface of the substrate on which the element isolation 5a and the lower and upper gate electrodes 7a and 18a are formed.
2 are formed, and the first-layer metal wiring 12 is connected to the upper gate electrode 18 a and the source / drain electrodes 9 b via the contact portions 13.

Here, in the present embodiment, in the cross section in the gate width direction, a step of about 100 to 200 nm exists between the upper surface of the element isolation 5a and the upper surface of the silicon substrate 1 in the active region. On the other hand, in the cross section in the channel direction and the cross section of the active region, there is almost no step, and at most the element isolation 5
There is almost no step between the upper surface of a and the upper surface of the silicon substrate 1 in the active region.

Next, a method of manufacturing the semiconductor device shown in FIG. 3 will be described with reference to FIGS.
The point is that the deposition of the gate oxide film and the polysilicon film serving as the gate electrode has been completed before the formation of the trench type element isolation.

First, in the step shown in FIG. 4A, a gate oxide film 3 and a polysilicon film 7 serving as a lower gate electrode of a MOS transistor are sequentially deposited on a silicon substrate 1, and an element isolation is formed thereon. The photoresist film 20 that opens the formation region and covers the active region is patterned. As described above, the point that the deposition of the gate oxide film and the polysilicon film serving as the gate electrode is completed before the formation of the trench type element isolation is different from the method of manufacturing the semiconductor device according to the first embodiment. Using the photoresist film 20 as a mask, the polysilicon film 7 and the gate oxide film 3 are selectively removed, and further, the silicon substrate 1 is etched.
A groove 4 serving as an element isolation region is formed. At this time, the thickness of the polysilicon film 7 is almost the same as that of the silicon nitride film in the first embodiment, that is, 100 to 200 nm.
The thickness of the gate oxide film 3 is about 10 nm. The depth of the groove 4 is about 400 nm. After that, impurity ions of the conductivity type opposite to the conductivity type of the impurities to be implanted into the source / drain regions to be formed later are implanted to form the channel stop region 15. That is,
Using different resist masks, N-type impurity ions are implanted in the PMOSFET and P-type impurity ions are implanted near the bottom of the trench 4 in the NMOSFET.

Next, after the photoresist film 20 is removed, a value obtained by adding the depth of the groove 4 and the thickness of the remaining polysilicon film 7, that is, a value higher than the height from the bottom of the groove 4 to the upper surface of the polysilicon film 7. An insulating film (not shown) having a sufficient thickness is deposited, and the insulating film is removed by chemical mechanical polishing (CMP) until the upper surface of the polysilicon film 7 is exposed, thereby planarizing the entire substrate surface. . By this step, a trench-type element isolation 5a made of an insulating film is formed in the element isolation region. This planarization method is not limited to the present embodiment, and a method of performing etch-back using a reverse pattern of an active region with a photoresist film may be used.

Next, in the step shown in FIG. 4B, a conductor film 18 (a conductive polysilicon film or a silicide film such as WSi or TiSi) serving as a gate electrode wiring layer is formed on the planarized substrate. Further, a high-melting-point metal such as W may be used via a barrier metal such as TiN for lowering resistance, and a protective film 19 made of an insulating film is deposited to form a gate electrode and a gate wiring. A photoresist film 21 having an opening in a region other than the region to be formed is formed.

Then, in the step shown in FIG. 4C, the protective film 19, the conductor film 18 and the polysilicon film 7 are patterned by dry etching using the photoresist film 21 as a mask, and the lower gate electrode 7a and the upper The gate electrode 18a and the protection film 19a are formed. At this point, the distance between the upper surface of the silicon substrate 1 in the active region and the upper surface of the element isolation 5a is also one in the cross section in the channel direction and the cross section in the active region.
There is a step of about 00 to 200 nm.

Next, in the step shown in FIG. 4D, only the silicon oxide film forming the element isolation 5a in the opening region of the photoresist film 21 is selectively etched, and the lower part and the element isolation 5a are separated. Upper gate electrodes 7a, 18a
The position of the upper surface of the portion not covered by the above is lowered to reduce the step between the element isolation 5a and the silicon substrate 1 in the active region. The feature of the present embodiment is that a step for reducing this step is provided. As a result, a large step exists between the element isolation 5a and the active region in the gate width direction cross section,
In the cross section in the channel direction and the cross section of the active region, at the end of the manufacturing process, 20 to 20
There is only a small step of about 40 nm. Thereafter, low-concentration impurity ions are implanted to form low-concentration source / drain regions 6a in the lower and upper gate electrodes 7a and 18a in the active region.

Next, in the step shown in FIG. 4E, after removing the photoresist film 21, similar to the first embodiment,
An insulating film (silicon oxide film) is deposited on the entire surface of the substrate, and anisotropic etching of the insulating film is performed to form electrode portion side walls 8a on the side surfaces of the lower and upper gate electrodes 7a and 18a. At this time, if a step between the element isolation 5a and the surface of the silicon substrate 1 is eliminated, no side wall is formed, and a large source / source area is formed on the active region.
A drain electrode 9b is formed. If there is a step, the step sidewall 8b is also formed on the side surface of the step between the silicon substrate 1 in the active region and the element isolation 5a. The dimensions in the direction are very small. Therefore, a large area of source / drain electrode 9b on the active region can be secured. Then, impurity ions are implanted in this state to form the high-concentration source / drain regions 6b. Further, a source / drain electrode 9b made of silicide is formed only on the high concentration source / drain region 6b.

Although illustration of the subsequent steps is omitted, the deposition of the interlayer insulating film 11 and the formation of the contact hole, the embedding of the metal into the contact hole, and the first-layer metal wiring 1
Through the formation of MOS transistor 2, a MOS transistor having the structure shown in FIG. 3 is formed. However, in this embodiment, an upper gate electrode 18a made of conductive polysilicon or silicide and a protective film 19a made of an insulating film are formed on the lower gate electrode 7a, and a source / drain electrode made of silicide is formed. 9b is an upper gate electrode 18a
It is formed in a process different from that of the above.

In the above process, the electrode side wall 8 is formed in order to form a transistor having an LDD structure.
In the transistor having a so-called pocket injection structure in which an impurity of the opposite conductivity type is injected between the source / drain region and the channel region to provide a punch-through stopper, the electrode portion side wall 8a and the like are formed. The present invention is also applied to a transistor having such a pocket injection structure.

As described above, according to the present embodiment, although a large step exists between the element isolation 5a and the active region in the cross section in the gate width direction (the area covered with the gate electrode), the cross section in the channel direction In addition, in the cross section of the active region (region not covered with the gate electrode), there is almost no step between them, and even if there is, there is no small step. Therefore, the same effects as in the first embodiment can be exhibited.

Also, in the manufacturing process of the semiconductor device according to the present embodiment, the process of reducing the thickness of the element isolation 5a shown in FIG. 4D is different from the manufacturing process of the conventional stepped trench isolation structure shown in FIG. In this case, since the photoresist film 21 is used as it is, no increase in the number of photolithography steps is caused.

In addition, in the present embodiment, the step of patterning the gate electrode 7a and the gate wiring 7b from the state shown in FIG. 4B is fully performed without any influence of the step at the end of the element isolation 5a. Since it can be performed in a flat state, there is an advantage that a fine pattern can be formed stably.

(Third Embodiment) Next, FIGS.
The third embodiment will be described with reference to (a) to (e). 5A to 5E are cross-sectional views illustrating the structure of the semiconductor device according to the present embodiment. FIGS. 6A to 6E are cross-sectional views illustrating a manufacturing process for realizing the structure of the semiconductor device illustrated in FIG. It is. However, FIGS. 5 and 6 (a) to 6 (e) show the structures in the cross section in the gate width direction, the cross section in the channel direction and the cross section in the active region shown in FIG.

As shown in FIG. 5, on a P-type silicon substrate (or well) 1, a groove-type element isolation 5a for dividing a region near the surface of the silicon substrate 1 into a number of active regions is formed. . In the cross section in the channel direction and in the cross section of the active region, the upper surface of the element isolation 5a is flattened so as to be substantially the same height as the upper surface of the silicon substrate 1 in the active region. On the other hand, in the cross section in the gate width direction, the upper surface of the element isolation 5a is sufficiently higher than the silicon substrate 1 in the active region, and a large step exists between them. This element separation 5
“a” is formed by embedding an insulating material in a groove formed in the silicon substrate 1 as described later. A channel stop region 15 having a conductivity type opposite to that of the source / drain region is formed at the bottom of the element isolation 5a by ion implantation described later.

Then, the element isolation 5a on the silicon substrate 1
, The lower gate electrode 7a, the upper gate electrode 18a and the protective film 19a, the electrode portion side walls 8a formed on the side surfaces of the lower and upper gate electrodes 7a and 18a, A drain region 6a and a high-concentration source / drain region 6b;
A MOSFET comprising a source / drain electrode 9b made of silicide formed on the drain region 6b is provided.

Further, a step portion side wall 8b is formed on the side surface of the step portion between the silicon substrate 1 in the active region and the element isolation 5a. The interlayer insulating film 11 and the first-layer metal wiring 1 are formed on the entire surface of the substrate on which the element isolation 5a and the lower and upper gate electrodes 7a and 18a are formed.
2 are formed, and the first-layer metal wiring 12 is connected to the upper gate electrode 18 a and the source / drain electrodes 9 b via the contact portions 13.

Here, in this embodiment, in the cross section in the gate width direction, a step of about 100 to 200 nm exists between the upper surface of the element isolation 5a and the upper surface of the silicon substrate 1 in the active region. On the other hand, in the cross section in the channel direction and the cross section of the active region, there is almost no step between the upper surface of the element isolation 5a and the upper surface of the silicon substrate 1 in the active region.

Next, a method of manufacturing the semiconductor device shown in FIG. 5 will be described with reference to FIGS.
The difference between the present embodiment and the first and second embodiments is that when the trench type element isolation is formed and planarized, only the element isolation is etched to reduce the step between the element isolation and the substrate. It is.

First, in the step shown in FIG. 6A, a gate oxide film 3 and a polysilicon film 7 serving as a lower gate electrode of a MOS transistor are sequentially deposited on a silicon substrate 1, and an element isolation is formed thereon. The photoresist film 20 that opens the formation region and covers the active region is patterned. Using the photoresist film 20 as a mask, the polysilicon film 7 and the gate oxide film 3 are selectively removed, and further, the silicon substrate 1 is etched to form a trench 4 serving as an element isolation region. At this time, the thickness of the polysilicon film 7 is
The thickness of the gate oxide film 3 is set to about the same as the silicon nitride film in the first embodiment, that is, about 100 to 200 nm, and the thickness is about 10 nm. The depth of the groove 4 is about 400 nm. After that, impurity ions of the conductivity type opposite to the conductivity type of the impurities to be implanted into the source / drain regions to be formed later are implanted to form the channel stop region 15. That is, using different resist masks, the PMOSFET is used to remove N-type impurity ions,
In the NMOSFET, the P-type impurity ions are respectively
Inject near the bottom of the.

Next, in the step shown in FIG. 6B, after removing the photoresist film 20, a value obtained by adding the depth of the groove 4 and the thickness of the remaining polysilicon film 7, that is, the polysilicon from the bottom of the groove 4 An insulating film (not shown) having a thickness sufficiently larger than the height up to the upper surface of the silicon film 7 is deposited, and a chemical mechanical polishing (CM
The insulating film is removed until the upper surface of the polysilicon film 7 is exposed by performing P), and the entire substrate surface is flattened. By this step, a trench-type element isolation 5a made of an insulating film is formed in the element isolation region. At this point, a step of about 100 to 200 nm exists between the upper surface of the silicon substrate 1 in the active region and the upper surface of the element isolation 5a in any cross section. This planarization method is not limited to the present embodiment, and a method of performing etch-back using a reverse pattern of an active region with a photoresist film may be used. Alternatively, the groove-type element isolation 5a may be selectively etched, and the etching may be stopped at the same height as the silicon substrate 1 to make the steps uniform.

Next, in the step shown in FIG. 6C, only the element isolation 5a composed of a silicon oxide film is etched, and the upper surface of the element isolation 5a and the silicon substrate 1 in the active region are etched.
Is reduced to about 50 to 100 nm.
This value is determined so that there is almost no step at the end of the manufacturing process.

Next, in the step shown in FIG. 6D, a conductor film 18 (a conductive polysilicon film or a silicide film such as WSi or TiSi may be formed on the substrate as a gate electrode wiring layer. A high-melting-point metal such as W may be used via a barrier metal such as TiN for increasing the resistance.) And a protective film 19 made of an insulating film are deposited, and the region other than the region where the gate electrode and the gate wiring are formed is deposited. A photoresist film 21 having a region opened is formed.

Then, in the step shown in FIG. 6E, the protective film 19, the conductor film 18 and the polysilicon film 7 are patterned by dry etching using the photoresist film 21 as a mask, and the lower gate electrode 7a and the upper The gate electrode 18a and the protection film 19a are formed. At this point, the step between the upper surface of the silicon substrate 1 in the active region and the upper surface of the element isolation 5a in the channel direction cross section and the active region cross section is small as described above. Thereafter, low-concentration impurity ions are implanted to form low-concentration source / drain regions 6a in the lower and upper gate electrodes 7a and 18a in the active region. Further, after the photoresist film 21 is removed, an insulating film (silicon oxide film) is deposited on the entire surface of the substrate as in the first embodiment and the like, and this insulating film is anisotropically etched to form a lower portion. Then, an electrode portion side wall 8a is formed on side surfaces of the upper gate electrodes 7a and 18a. At this time, a step sidewall 8b is also formed on the side surface of the step between the silicon substrate 1 in the active region and the element isolation 5a. Then, impurity ions are implanted in this state to form the high-concentration source / drain regions 6b.

Although illustration of the subsequent steps is omitted, the deposition of the interlayer insulating film 11 and the formation of the contact hole, the embedding of the metal in the contact hole, and the first-layer metal wiring 1
Through the formation of MOS transistor 2, a MOS transistor having the structure shown in FIG. 3 is formed.

However, in this embodiment, the high-density source
Although the source / drain electrodes made of silicide are not formed on the drain region 6b, it goes without saying that they may be formed.

In the above process, the electrode side wall 8 is formed in order to form a transistor having an LDD structure.
In the transistor having a so-called pocket injection structure in which an impurity of the opposite conductivity type is injected between the source / drain region and the channel region to provide a punch-through stopper, the electrode portion side wall 8a and the like are formed. The present invention is also applied to a transistor having such a pocket injection structure.

As described above, according to the present embodiment, although a large step exists between the element isolation 5a and the active region in the cross section in the gate width direction (the area covered with the gate electrode), the cross section in the channel direction In the cross section of the active region (region not covered with the gate electrode), there is almost no step between the element isolation 5a and the active region, or even if there is a step, there is no large step. The same effect as the embodiment can be exerted.

Also, in the manufacturing process of the semiconductor device according to the present embodiment, as compared with the manufacturing process of the conventional stepped trench isolation structure shown in FIGS. 11A to 11E, FIG.
Only the step of reducing the thickness of the element isolation 5a shown in (d) is added. At this time, since the photoresist film 21 is used as it is, no increase in the number of photolithography steps is caused.

(Fourth Embodiment) Next, a fourth embodiment will be described with reference to FIGS. In the present embodiment, the structure of the semiconductor device is substantially the same as the structure shown in FIG. 3 in the second embodiment, and thus the description thereof will be omitted, and only the manufacturing process will be described.

The difference between this embodiment and the second embodiment is that the element isolation and the substrate surface are not completed after the patterning of the upper gate electrode film is completed, rather than after all the gate electrodes made of the laminated film are patterned. Is to perform a step of reducing the level difference from the above.

First, in the step shown in FIG. 7A, a gate oxide film 3 and a polysilicon film 7 serving as a lower gate electrode of a MOS transistor are sequentially deposited on a silicon substrate 1, and an element isolation is formed thereon. The photoresist film 20 that opens the formation region and covers the active region is patterned. Using the photoresist film 20 as a mask, the polysilicon film 7 and the gate oxide film 3 are selectively removed, and further, the silicon substrate 1 is etched to form a trench 4 serving as an element isolation region. At this time, the thickness of the polysilicon film 7 is
The thickness of the gate oxide film 3 is set to about the same as the silicon nitride film in the first embodiment, that is, about 100 to 200 nm, and the thickness is about 10 nm. The depth of the groove 4 is about 400 nm. After that, impurity ions of the conductivity type opposite to the conductivity type of the impurities to be implanted into the source / drain regions to be formed later are implanted to form the channel stop region 15. That is, using different resist masks, the PMOSFET is used to remove N-type impurity ions,
In the NMOSFET, the P-type impurity ions are respectively
Inject near the bottom of the.

Next, after removing the photoresist film 20, a value obtained by adding the depth of the groove 4 and the thickness of the remaining polysilicon film 7, that is, a value higher than the height from the bottom of the groove 4 to the upper surface of the polysilicon film 7 is set. An insulating film (not shown) having a sufficient thickness is deposited, and the insulating film is removed by chemical mechanical polishing (CMP) until the upper surface of the polysilicon film 7 is exposed, thereby planarizing the entire substrate surface. . By this step, a trench-type element isolation 5a made of an insulating film is formed in the element isolation region. This planarization method is not limited to the present embodiment, and a method of performing etch-back using a reverse pattern of an active region with a photoresist film may be used.

Next, in the step shown in FIG. 7B, a conductor film 18 (a conductive polysilicon film or a silicide film such as WSi or TiSi) serving as a gate electrode wiring layer is formed on the planarized substrate. Further, a high-melting-point metal such as W may be used via a barrier metal such as TiN for lowering resistance, and a protective film 19 made of an insulating film is deposited to form a gate electrode and a gate wiring. A photoresist film 21 having an opening in a region other than the region to be formed is formed.

Then, in the step shown in FIG. 7C, the protective film 19 and the conductor film 18 are patterned by dry etching using the photoresist film 21 as a mask to form the upper gate electrode 18a and the protective film 19a. . At this time, in each of the cross sections, 100 to 100 mm is set between the upper surface of the silicon substrate 1 in the active region and the upper surface of the element isolation 5a.
There is a step of about 200 nm.

Next, in the step shown in FIG. 7D, only the element isolation 5a not covered with the polysilicon film 7 serving as the lower gate electrode is selectively etched to be covered with the polysilicon film 7. The position of the upper surface of the non-existing portion is lowered so that the step between the element isolation 5a and the silicon substrate 1 in the active region is almost eliminated. As a result, a large step exists between the element isolation 5a and the active region in the cross section in the gate width direction, and a step is formed in the cross section in the channel direction and the active region so that there is almost no step at the end of the manufacturing process. Only small steps of ４０40 nm are present.

Next, in the step shown in FIG. 7E, the polysilicon film 7 is patterned using the photoresist film 21 as it is to form a lower gate electrode 7a. Thereafter, low-concentration impurity ions are implanted to form low-concentration source / drain regions 6a in the lower and upper gate electrodes 7a and 18a in the active region.
Further, after the photoresist film 21 is removed, an insulating film (silicon oxide film) is deposited on the entire surface of the substrate as in the first embodiment, and anisotropic etching of the insulating film is performed. An electrode portion side wall 8a is formed on side surfaces of the upper gate electrodes 7a, 18a and the like. At this time, a step sidewall 8b is also formed on the side surface of the step between the silicon substrate 1 in the active region and the element isolation 5a. Then, impurity ions are implanted in this state to form the high-concentration source / drain regions 6b. Further, a source / drain electrode 9b made of silicide is formed only on the high concentration source / drain region 6b.

Although illustration of the subsequent steps is omitted, the deposition of the interlayer insulating film 11 and the formation of the contact hole, the embedding of the metal in the contact hole, and the first-layer metal wiring 1
Through the formation of MOS transistor 2, a MOS transistor having the structure shown in FIG. 3 is formed. However, in this embodiment, an upper gate electrode 18a made of conductive polysilicon or silicide and a protective film 19a made of an insulating film are formed on the lower gate electrode 7a, and a source / drain electrode made of silicide is formed. 9b is an upper gate electrode 18a
It is formed in a process different from that of the above.

In the above process, the electrode side wall 8 is formed in order to form a transistor having an LDD structure.
In the transistor having a so-called pocket injection structure in which an impurity of the opposite conductivity type is injected between the source / drain region and the channel region to provide a punch-through stopper, the electrode portion side wall 8a and the like are formed. The present invention is also applied to a transistor having such a pocket injection structure.

As described above, according to the present embodiment, in the cross section in the gate width direction (the area covered with the gate electrode), there is a large step between the element isolation 5a and the active region. In the cross section of the active region (region not covered with the gate electrode), there is almost no step between them, or even if there is a step, there is no small step. Therefore, the same effects as in the first embodiment can be exhibited.

Also, in the manufacturing process of the semiconductor device according to the present embodiment, as compared with the manufacturing process of the conventional stepped trench isolation structure shown in FIGS.
Only the step of reducing the thickness of the element isolation 5a shown in (d) is added. At this time, since the photoresist film 21 is used as it is, no increase in the number of photolithography steps is caused.

(Other Embodiments) In each of the above embodiments, in addition to the gate electrode, a gate wiring extending over the element isolation, and a dummy for forming a line and space pattern for improving patterning accuracy at the time of patterning the gate electrode. The structure provided with a gate can be applied as it is.

In each of the above embodiments, the step between the upper surface of the element isolation and the substrate surface of the active region is kept large under the gate electrode, and the element isolation is not covered by the gate electrode. Whether the step between the upper surface of the active region and the substrate surface of the active region is reduced, the difference between the two is eliminated, or the upper surface of the element isolation is made lower than the substrate surface of the active region.
Different configurations are possible.

In each of the above embodiments, the low concentration source / drain regions 6a need not always be provided.

[0101]

According to the semiconductor device of the first to third aspects, in the semiconductor device having the groove-type element isolation structure, in the region below the gate electrode, the groove-type element isolation is more effective in the active region. By providing a step higher than the semiconductor substrate to prevent a lateral electric field from being applied from the gate electrode to the active region, the trench-type element isolation and the semiconductor substrate in the active region are formed in regions other than below the gate electrode. The design rule is 0.25 by minimizing the height difference from
Even in a semiconductor device as small as about μm or less, a wide active region is secured without being filled with an insulating film for sidewalls, and a rise in contact resistance can be suppressed, and thus characteristics suitable for miniaturization can be achieved. A semiconductor device with good performance can be obtained.

The structure of the semiconductor device according to claims 1 to 3 can be easily realized by the method for manufacturing a semiconductor device according to claim 8.

According to the semiconductor device of the fourth aspect, in a semiconductor device having a trench-type element isolation and a gate electrode including an upper gate electrode and a lower gate electrode, the upper surface of the trench-type element isolation is made active with the upper surface of the lower gate electrode. Since the structure is located between the upper surface of the semiconductor substrate in the region and the lateral electric field from being applied to the active region from the gate electrode, the height of the trench-type element isolation and the height of the semiconductor substrate in the active region are reduced. By minimizing the difference, the design rule becomes 0.2
Even in a semiconductor device as fine as about 5 μm or less, a wide active region is secured without being filled with an insulating film for sidewalls, and an increase in contact resistance can be suppressed. Thus, a semiconductor device having favorable characteristics suitable for miniaturization can be obtained.

The structure of the semiconductor device of claim 4 is the same as that of claim 9
It can be easily realized by the method of manufacturing a semiconductor device.

According to the semiconductor device of the fifth to seventh aspects, in the semiconductor device having the trench-type element isolation and the gate electrode including the upper gate electrode and the lower gate electrode, the region below the upper gate electrode has a trench type. The element isolation is provided with a higher step than the semiconductor substrate in the active region to prevent a lateral electric field from being applied from the gate electrode to the active region. By minimizing the height difference between the trench-type element isolation and the semiconductor substrate in the active region, the design rule is reduced to 0.2.
Even in a semiconductor device as fine as about 5 μm or less, a wide active region is secured without being filled with an insulating film for sidewalls, and an increase in contact resistance can be suppressed. Thus, a semiconductor device having favorable characteristics suitable for miniaturization can be obtained.

The structure of the semiconductor device according to claims 5 to 7 can be easily realized by the method for manufacturing a semiconductor device according to claim 10 or 11.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a structure of a semiconductor device according to a first embodiment.

FIG. 2 is a sectional view illustrating a manufacturing process of the semiconductor device according to the first embodiment.

FIG. 3 is a cross-sectional view illustrating a structure of a semiconductor device according to a second embodiment.

FIG. 4 is a sectional view illustrating a manufacturing process of the semiconductor device according to the second embodiment;

FIG. 5 is a cross-sectional view illustrating a structure of a semiconductor device according to a third embodiment.

FIG. 6 is a sectional view illustrating a manufacturing process of the semiconductor device according to the third embodiment;

FIG. 7 is a sectional view illustrating a manufacturing process of a semiconductor device according to a fourth embodiment.

FIG. 8 is a cross-sectional view showing the structure of a conventional semiconductor device having a general trench-type element isolation structure.

FIG. 9 is a plan view for explaining locations of a cross section in a gate width direction, a cross section in a channel direction, and a cross section of an active region in each cross-sectional view.

FIG. 10 is a cross-sectional view showing a part of FIG. 8 in an enlarged manner to explain a problem in a conventional general semiconductor device having a trench type element isolation.

FIG. 11 is a cross-sectional view showing a manufacturing process of a conventional semiconductor device having a grooved element isolation with a step.

[Description of Signs] 1 Silicon substrate (semiconductor substrate) 3 Gate oxide film 4 Groove 5a Trench type element isolation 6a Low concentration source / drain region 6b High concentration source / drain region 7 Polysilicon film (conductor film) 7a Gate electrode (lower portion) Gate electrode) 8 Silicon oxide film 8a Electrode side wall 8b Step side wall 9a Upper gate electrode 9b Source / drain electrode 11 Interlayer insulating film 12 First layer metal wiring 13 Contact part 15 Channel stop region 16 Silicon oxide film 17 Silicon Nitride film (etching stopper film) 20, 21 Photoresist film

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Akihiro Kanda 1-1, Komachi, Takatsuki-shi, Osaka Matsushita Electronics Corporation

Claims (11)

[Claims] A semiconductor substrate; an active region provided in a part of the semiconductor substrate; a groove-type element isolation made of an insulating material surrounding the active region; and the active region and the groove-type element isolation. A straddling gate electrode; and an insulator sidewall formed on a side surface of the gate electrode. In a region below the gate electrode, the trench-type element isolation is more effective than the semiconductor substrate in the active region. A height difference between the trench-type element isolation and the semiconductor substrate in the active region is smaller than the height difference in a region not covered with the gate electrode. apparatus. 2. The semiconductor device according to claim 1, wherein said trench-type element isolation in a region not covered with said gate electrode and a semiconductor substrate in an active region have substantially the same top surface height. apparatus. 3. The semiconductor device according to claim 1, wherein a height difference between an upper surface of the trench isolation in a region not covered with the gate electrode and a semiconductor substrate in the active region is equal to the gate electrode. A semiconductor device in a region below the semiconductor substrate in the active region. 4. A semiconductor substrate, an active region provided in a part of the semiconductor substrate, a trench isolation formed of an insulating material surrounding the active region, and straddling the active region and the trench isolation. A gate electrode including an upper gate electrode, a lower gate electrode formed only on the active region, and an insulator sidewall formed on a side surface of the gate electrode, covered with the upper gate electrode The height position of the upper surface of the groove type element isolation in the region where there is no gap is between the height position of the upper surface of the lower gate electrode and the height position of the upper surface of the semiconductor substrate in the active region. Semiconductor device. 5. A semiconductor substrate, an active region provided in a part of the semiconductor substrate, a groove-type element isolation made of an insulating material surrounding the active region, and the groove-type element formed on the active region. A lower gate electrode having the same upper surface position as the isolation, an upper gate electrode extending from the active region to the trench-type element isolation, and an insulator sidewall formed on a side surface of the gate electrode. In a region below the upper gate electrode, the trench-type element isolation has a step that is higher than the semiconductor substrate in the active region, but is not covered with the upper gate electrode. In a semiconductor device, a height difference between the trench-type element isolation and a semiconductor substrate in an active region is smaller than the step. 6. The semiconductor device according to claim 5, wherein a height position of an upper surface of the trench-type element isolation in a region not covered with the upper gate electrode and a height position of an upper surface of the semiconductor substrate in an active region. A semiconductor device characterized by being substantially the same. 7. The semiconductor device according to claim 5, wherein a height difference between an upper surface of the trench type element isolation in a region not covered with the upper gate electrode and a semiconductor substrate in the active region is equal to the upper part. A semiconductor device, wherein the height of the groove-type element isolation in a region below a gate electrode is equal to or less than の of a step between the semiconductor substrate in the active region and the semiconductor device in the active region. 8. A first step of depositing a protective film on a semiconductor substrate, a second step of forming an opening in the protective film, and etching a semiconductor substrate in the opening to form a groove. A third step of depositing a buried insulating film on the substrate; and etching the buried insulating film until the protective film is exposed, so that a step is present between the semiconductor substrate and the groove-type element isolation. Thus, a fourth step of forming a trench-type element isolation by filling the inside of the trench with the filling insulating film, and a fifth step of depositing a conductive film on the substrate after removing the protective film. A sixth step of patterning the conductive film to form a gate electrode extending from the active region surrounded by the trench-type element isolation to the trench-type element isolation; and covering the trench-type element isolation with the gate electrode. Selective etching of parts that are not And an eighth step of forming an insulator sidewall on the side surface of the gate electrode by performing anisotropic etching after depositing a sidewall insulating film on the substrate. A method for manufacturing a semiconductor device, comprising: 9. A first step of depositing a first conductor film on a semiconductor substrate, forming an opening in the first conductor film, and etching a semiconductor substrate in the opening to form a groove. A second step, a third step of depositing a buried insulating film on the substrate, and etching the buried insulating film until the first conductor film is exposed, thereby forming the semiconductor substrate and the trench-type element. A fourth step of forming a trench-type element isolation in which the trench is filled with the burying insulating film so that a step is present between the trench and the isolation.
A fifth step of selectively etching the trench-type element isolation; a sixth step of depositing a second conductor film on a substrate; and patterning the first and second conductor films. A seventh step of forming a gate electrode extending from the active region surrounded by the trench-type element isolation to the trench-type element isolation; and depositing a sidewall insulating film on the substrate, and then performing anisotropic etching. An eighth step of forming an insulator sidewall on the side surface of the gate electrode. 10. A first step of depositing a first conductor film on a semiconductor substrate, forming an opening in the first conductor film, and etching a semiconductor substrate in the opening to form a groove. A second step, a third step of depositing a buried insulating film on the substrate, and etching the buried insulating film until the first conductor film is exposed, thereby forming the semiconductor substrate and the trench-type element. A fourth step of forming a trench-type element isolation in which the trench is filled with the burying insulating film so that a step is present between the trench and the isolation.
A fifth step of depositing a second conductor film on the substrate; and patterning the second conductor film to form an upper portion extending from the active region surrounded by the trench element isolation to the trench element isolation. A sixth step of forming a gate electrode, a seventh step of selectively etching a portion of the trench-type element isolation not covered by the upper gate electrode, and patterning the first conductive film. An eighth step of forming a lower gate electrode, and a ninth step of depositing a sidewall insulating film on the substrate and then performing anisotropic etching to form an insulator sidewall on the side surface of the gate electrode. And a method of manufacturing a semiconductor device. 11. A first step of depositing a first conductive film on a semiconductor substrate, an opening is formed in the first conductive film, and a groove is formed by etching the semiconductor substrate in the opening. A second step, a third step of depositing a buried insulating film on the substrate, and etching the buried insulating film until the first conductor film is exposed, thereby forming the semiconductor substrate and the trench-type element. A fourth step of forming a trench-type element isolation in which the trench is filled with the burying insulating film so that a step is present between the trench and the isolation.
And a fifth step of depositing a second conductor film on the substrate. Patterning the first and second conductor films to separate the active region surrounded by the trench element isolation from the trench type element isolation. A sixth step of forming a gate electrode extending over the substrate, a seventh step of selectively etching a portion of the trench-type element isolation not covered by the gate electrode, and forming a sidewall insulating film on the substrate. Forming an insulator sidewall on the side surface of the gate electrode by performing anisotropic etching after the deposition, and an eighth step of manufacturing the semiconductor device.