JPH09172063A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device where the occurrence of junction leakage, deterioration of junction withstand voltage, flowing of a short-circuit current, etc., are prevented and to provide a manufacturing method for such a semiconductor device. SOLUTION: A stepped part higher on an element isolation 5A side is formed between an element forming region Refet and a groove-shaped element isolation 5a. On the sides of a gate electrode 7a and the stepped part, there are sidewalls 8a of the electrode part and sidewalls 8c of the stepped part formed simultaneously. On heavily doped source/drain regions 6b, source/drain electrodes 9c silicidized are formed. By the stepped part between the element forming region Refet and the element isolation 5a, and the sidewalls of the stepped part, intrusion of impurity ions into the lower parts of the end parts of the element isolation 5a and into the interface between a silicon substrate 1 of a silicide layer and the element isolation 5a is blocked.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a structure of a semiconductor device having a groove-buried isolation type element isolation and a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, with the progress of higher integration and higher performance of semiconductor devices, there is an increasing demand for miniaturization.
Therefore, there is a technical field in which introduction of new technology is unavoidable because it is not possible to keep up with the demands only by improving conventional technology. For example, as an element isolation formation method, conventionally, element isolation has been formed by the LOCOS isolation method from the viewpoint of the manufacturing method's simplicity and low cost, but recently, in order to form a finer semiconductor device, a groove-embedded isolation method is used. It has been considered advantageous to provide the element isolation (hereinafter, simply referred to as groove type element isolation).

That is, since the LOCOS isolation method uses a selective oxidation method, so-called bird's beak occurs at the boundary with the mask for preventing the oxidation, and the isolation region is closer to the element region than the actual mask size. The insulating film invades to cause a dimensional change, and the amount of change becomes an unacceptable value for miniaturization after the 0.5 μm generation. Therefore, even in the field of mass production technology, the shift to the trench isolation method with extremely small size shift is beginning. For example, IBM has introduced a groove type element isolation structure for mass production of MPU as a 0.5 μm CMOS process (reference: IBM J
ouralof Research and Dev
element, VOL. 39, NO. 1/2, 19
95, 33-42).

FIG. 6 shows a conventional trench isolation and MOSFE.
It is sectional drawing which shows the example of the semiconductor device in which T and was provided.
As shown in the figure, a groove-type element isolation 105a is formed on the silicon substrate 101. Then, element isolation 10
The gate insulating film 1 is formed on the active region surrounded by 5a.
03a and the gate electrode 107a, and the gate electrode 107a
And the electrode part sidewalls 108a on both side surfaces thereof are provided. In addition, in the active region, the gate electrode 107a
A low-concentration source / drain region 106a and a high-concentration source / drain region 106b are provided in regions located on both sides of each of the above, and a channel stop region 115 is provided below the element isolation 105a. In addition, element isolation 105
Silicon substrate 101 that does not function as an active region of a
A gate wiring 107b made of the same polysilicon film as the gate electrode 107a is provided over the gate insulating film 103b, and wiring sidewalls 108b are provided on both side surfaces thereof. Furthermore, the gate electrode 10
7a, the gate wiring 107b, and the high-concentration source / drain region 106b, an upper gate electrode 109a made of silicide, and an upper gate wiring 109b, respectively.
Source / drain electrodes 109c are provided. Further, the interlayer insulating film 11 made of a silicon oxide film, the metal wiring 112 formed on the interlayer insulating film 111, and the contact hole formed in the interlayer insulating film 111 are filled with the metal wiring 112 and the source / drain. Electrode 109c
And a contact portion 113 for connecting between and.

Next, referring to FIGS. 7A to 7E, the conventional trench type element isolation and MOSFET shown in FIG.
A manufacturing process of a semiconductor device having the above will be described.

First, as shown in FIG. 7A, a silicon oxide film 105 (not shown) is deposited and then the entire surface is planarized until the surface of the silicon nitride film 117 is exposed. By this step, the groove portion 1 is formed in the element isolation region Reiso.
A trench-type element isolation 105a made of a silicon oxide film embedded in the trench 04 is formed. Then, the silicon oxide film 116 is once removed, and then the gate oxide film 103 is formed on the entire surface.

Next, as shown in FIG. 7C, after implanting impurity ions below the element isolation 105a to form a channel stop region 115, a polysilicon film 107 is deposited on the entire surface. A photoresist film 121 having an opening other than the gate formation region is formed on the photoresist film 121.

Next, as shown in FIG. 7D, the polysilicon film 107 is formed using the photoresist film 121 as a mask.
Dry etching is performed to remove M in the element formation region Refet.
Gate electrode 107a of OSFET and element isolation 105a
Gate wiring 107b extending from above to the silicon substrate 101
And are formed. Then, after removing the photoresist film 121, impurity ions are implanted into the silicon substrate 101 using the gate electrode 107a as a mask to form the low concentration source / drain regions 106a. Then, a silicon oxide film 108 is deposited on the entire surface of the substrate.

Next, as shown in FIG. 7E, anisotropic dry etching of the silicon oxide film 108 is performed to form the electrode side wall 108a and the wiring on both side surfaces of the gate electrode 107a and the gate wiring 107b, respectively. The partial sidewall 108b is formed. At that time, the gate oxide film 103 below the silicon oxide film 108 is also removed at the same time, and only the gate oxide film 103a below the gate electrode 107a and the gate oxide film 103b below the gate wiring 107b remain. After that, impurity ions are obliquely implanted using the gate electrode 107a and the electrode portion sidewall 108a as a mask to form the high-concentration source / drain regions 106b. Then, after depositing a Ti film on the entire surface, a high temperature heat treatment is performed to react the Ti film with a member made of silicon which is in direct contact with the Ti film to cause an upper gate electrode 109a made of silicide and an upper gate wiring 109b. And the source / drain electrodes 109c are formed.

The subsequent steps are omitted, and the final structure of the MOSFET is shown in FIG. In FIG. 5, the interlayer insulating film 1
11, the metal wiring 112 is formed, and the metal wiring 112
Between the source and drain electrode 109c and the source / drain electrode 109c.
It is connected by 13.

When the groove-type element isolation structure as described above is adopted, LO that forms a thick silicon oxide film by thermal oxidation is used.
Since the bird's beak, that is, the oxide film does not enter the active region unlike the COS method, the dimensional shift of the source / drain regions is suppressed. Then, in the step shown in FIG. 7C, the element isolation 105a and the silicon substrate 101 in the element formation region Refet are planarized.

[0012]

However, the semiconductor device having the element isolation of the trench structure as described above has the following problems.

That is, when the state shown in FIG. 7D is changed to the state shown in FIG.
8 is anisotropically etched to form each sidewall 108.
Although a and 108b are formed, it is necessary to perform overetching at that time. By this over-etching, the surface of the element isolation 105a is dug down to some extent.

FIGS. 8A and 8B are enlarged sectional views showing the vicinity of the boundary between the high concentration source / drain region 106b and the element isolation 105a at this time.

As shown in FIG. 7A, impurity ions are obliquely implanted between the step shown in FIG. 7D and the step shown in FIG. 7E to form the high concentration source / drain regions. 1
Although the step of forming 06b is performed, since the element isolation 105a is dug down to the lower side, the high concentration source / drain region 106b is formed below the end portion of the element isolation 105a during this ion implantation. Therefore, the high-concentration source / drain region 106b and the channel stop region 115 come close to each other, which causes problems such as deterioration of junction breakdown voltage and increase of junction leak.

Further, as shown in FIG. 8B, in the case where a Ti film or the like is deposited on the high-concentration source / drain regions 106b and silicidation is made to react with the silicon below, the silicide layer is a silicon substrate. 101 and element isolation 10
The interface with 5a is likely to be eroded, which may cause a short-circuit current between the source / drain electrode 109c made of silicide and the channel stop region 115.

The present invention has been made in view of the above points, and an object thereof is to provide means for preventing the trench type element isolation region from being dug down due to overetching at the time of forming the sidewalls. It is an object of the present invention to provide a fine and high-performance semiconductor device having a groove type element isolation structure, without junction leakage, deterioration of junction breakdown voltage, short-circuit current, and the like, and a manufacturing method thereof.

[0018]

In order to achieve the above-mentioned object, the solution means taken by the present invention is such that the groove-type element isolation side is higher between the semiconductor substrate in the element formation region and the groove-type element isolation. Such a step portion is formed and a sidewall is provided on the step portion. Specifically, the means concerning the semiconductor device described in claims 1 to 5 and the method for manufacturing the semiconductor device described in claims 6 to 12 are taken.

As described in claim 1, a semiconductor device of the present invention includes a semiconductor substrate, an element formation region provided in a part of the semiconductor substrate, and the element formation region, and the element formation region. Between the element formation region and the groove-shaped element isolation, and the groove-shaped element isolation made of an insulating material and having a stepped portion higher than the semiconductor substrate in the element formation region between And a step portion sidewall formed on the side surface.

With this structure, since the step of which the surface of the groove type element isolation is higher than the surface of the semiconductor substrate in the element forming region is provided at the end of the groove type element isolation, the impurity diffusion layer of the semiconductor device is formed. Impurity ions are prevented from being implanted below the end portion of the element isolation when the impurity ions are implanted during formation. Further, even when adopting the structure of providing the source / drain electrodes made of silicide, since the stepped side walls prevent the invasion into the depth of the silicide layer, the substrate regions such as the source / drain electrodes and the channel stop regions are blocked. It is possible to prevent a short-circuit current from being generated. Therefore, the deterioration of the isolation function between the semiconductor devices in the trench type element isolation can be prevented.

As described in claim 2, in claim 1, the step portion side wall can be made of an insulating material.

According to a third aspect of the present invention, in the first aspect, the MISF has a gate electrode in the element formation region and electrode sidewalls on both side surfaces of the gate electrode.
By forming ET, at least a part of the step portion side wall can be formed simultaneously with the electrode portion side wall.

According to a fourth aspect of the present invention, in the third aspect, the electrode side wall is formed over the side surface of the gate electrode and the semiconductor substrate with a protective oxide film interposed therebetween, and has a substantially constant thickness. The sidewall of the step portion is formed of an L-shaped silicon nitride film having a thickness, and the side wall of the step portion between the element forming region and the trench type element isolation and the semiconductor substrate are covered with a protective oxide film. It can be composed of the formed L-shaped silicon nitride film having a substantially constant thickness.

With this structure, the L-shaped silicon nitride film provided in the step portion can prevent the deterioration of the isolation function between the semiconductor devices in the trench type element isolation. Moreover, since the structure is such that the film thickness of the trench type element isolation is not reduced even by the over-etching when forming the sidewalls, it is possible to reduce the step value. Therefore, when the gate electrode is patterned, the semiconductor substrate on the active region and the groove-type element isolation are close to a flat state, and the finished dimension accuracy of the gate is improved.

According to a fifth aspect of the present invention, in the third aspect, both the electrode portion sidewall and the step portion sidewall are made of a silicon film, and the electrode portion sidewall, the gate electrode, and the silicon substrate are formed. A source / drain formed of a silicide formed on the insulating film interposed between the electrode side wall, the source / drain region of the element formation region and the stepped side wall. An electrode can be further provided.

With this structure, the function of preventing the implantation of the impurity ions by the side wall of the step portion and the function of preventing the invasion into the depth of the silicide layer in the silicidation process can be obtained. In addition, since the source / drain electrodes made of the silicide layer are provided on the wide area extending over the electrode side wall, the source / drain region and the step side wall, it is easy and reliable to form the contact from the upper wiring. Therefore, the reliability is improved and the area of the element formation region can be reduced.

According to a sixth aspect of the present invention, there is provided a first method of manufacturing a semiconductor device, wherein a first step of forming an oxide film on a semiconductor substrate and the oxidation of the oxide film on the oxide film are performed. The second step of depositing an etching stopper film made of a material different from that of the film, and opening a region of the etching stopper film where element isolation is to be formed, and etching the semiconductor substrate in this opening to form a groove portion. And a fourth step of depositing an insulating film having a thickness equal to or more than the sum of the depth of the groove and the thickness of the etching stopper film, and the insulating film is deposited. A fifth step of planarizing the semiconductor substrate in the state until at least the surface of the etching stopper film is exposed, and forming a groove type element isolation surrounding the element formation region in the groove part;
At least the etching stopper film and the oxide film were removed by etching, and the side of the trench type element isolation between the element forming region and the trench type element isolation became higher in steps than the semiconductor substrate in the element forming region. A sixth step of exposing the step portion, a seventh step of depositing a gate oxide film and a conductive film on the substrate, and then patterning at least a gate electrode from the conductive film, and an insulating film over the entire surface of the substrate. After deposition, an eighth step of forming sidewalls made of the insulating film on each side surface of the gate electrode and the step portion by anisotropic etching, and a semiconductor substrate in an element formation region on both sides of the gate electrode A ninth step of forming a source / drain region by introducing impurities into the inside.

According to this method, since the step portion is formed between the semiconductor substrate in the element forming region and the trench type element isolation at the stage when the sixth step is completed, the impurity ion implantation in the ninth step is performed. At this time, the implantation of the impurity ions below the end of the trench type element isolation is prevented. Further, even when the vicinity of the surface of the source / drain region is silicidized later, the side wall of the step portion formed of the insulating film prevents the invasion of the silicide layer into the depth. Therefore, it is possible to prevent the junction breakdown voltage from deteriorating, the junction leak, and the like, and it is possible to prevent the occurrence of a short-circuit current between the source / drain electrodes and the substrate region such as the channel stop region.

As described in claim 7, in claim 6, in the second step, at least the over-etching amount in the eighth step is taken into consideration in the sixth step.
In the step of, the thickness of the etching stopper film can be determined so that the step portion having a height difference of a predetermined value or more is exposed.

According to this method, when the etching stopper film is removed in the sixth step, the height difference is ensured in consideration of the film reduction of the groove type element isolation due to the overetching amount. Therefore, the action of claim 6 can be effectively obtained.

According to a second method of manufacturing a semiconductor device of the present invention, as described in claim 8, a first step of forming an oxide film on a semiconductor substrate and a gate electrode on the oxide film. A second step of depositing a first conductive film to be formed, and a region of the first conductive film in which the trench type element isolation is to be formed is opened, and the semiconductor substrate in this opening is etched to form the trench. A third step of forming, a fourth step of depositing an insulating film having a thickness not less than the sum of the depth of the groove and the film thickness of the first conductive film, and the insulating film is deposited. The semiconductor substrate in the opened state is planarized until at least the surface of the first conductive film is exposed, and a fifth step of forming a groove type element isolation surrounding the element formation region in the groove section; On at least the upper gate electrode on the entire surface of the formed substrate. A sixth step of depositing a conductive film,
At least a gate electrode is patterned from the first and second conductive films, and the groove-type element isolation side is stepped between the element-forming region and the groove-type element isolation than the semiconductor substrate in the element-forming region. A seventh step of exposing the raised step portion, and an insulating film is deposited on the entire surface of the substrate and then anisotropic etching is performed to form a side formed of the insulating film on each side surface of the gate electrode and the step portion. An eighth step of forming a wall and a ninth step of forming a source / drain region by introducing impurities into the semiconductor substrate in the element forming regions on both sides of the gate electrode are provided.

According to this method, the same effect as that of the sixth aspect can be obtained, and in the gate electrode patterning step, the entire surface of the substrate is in a fully flat state.
The patterning accuracy of the gate electrode is improved.

As described in claim 9, in claim 8, in the second step, at least the over-etching amount in the eighth step is taken into consideration in the seventh step.
The film thickness of the conductive film can be determined so that a step having a height difference of a predetermined value or more is exposed in the step of.

With this method, the same effect as that of the seventh aspect can be obtained.

As described in claim 10, claim 6
Alternatively, a step of silicidating at least a region near the surface of the source / drain region can be further provided after finishing the ninth step in Step 8.

By this step, the low resistance source / drain electrodes are formed, so that a semiconductor device which operates at a low voltage and at a high speed is formed.

As described in claim 11, claim 6
Or 8, further comprising a step of depositing a protective oxide film on the entire surface of the substrate after the seventh step and before the eighth step, and in the eighth step, the protective oxide film is formed on the protective oxide film. A silicon nitride film for forming a sidewall and a mask film are sequentially deposited on the mask film, and the mask film is etched back to leave a mask for patterning the silicon nitride film on the side of the gate electrode and the step portion, The mask may be removed after patterning an L-shaped silicon nitride film to be a sidewall from the silicon nitride film to the side of the gate electrode and the step portion using the mask.

According to this method, the presence of the side wall of the step portion made of the L-shaped nitride film left in the step portion causes the impurity ions below the end portion of the element isolation during the ion implantation in the ninth step. Injection is blocked. Even when the step of providing the source / drain electrodes made of silicide is performed later, the step side wall made of the silicon nitride film prevents the silicide layer from penetrating into the interior. In addition, in the eighth step, even if over-etching is performed when forming the sidewalls, the protective oxide film is deposited on the trench type element isolation, so that film loss due to the trench type element isolation occurs. Absent. Therefore, it is possible to reduce the step difference between the trench-type element isolation and the semiconductor substrate in the active region, and the step difference when patterning the gate electrode in the seventh step is reduced. Accuracy is improved.

As described in claim 12, claim 6
Alternatively, in the seventh step, in the seventh step, a first protective insulating film is further deposited on the conductive film, the first protective insulating film is patterned together with a gate electrode, and the seventh protective film is formed.
And the step of depositing a second protective insulating film on the entire surface of the substrate after the step of, and in the eighth step, the second protective insulating film is deposited on the second protective insulating film. A silicon film for forming a sidewall is deposited, an electrode part sidewall and a step part sidewall made of the silicon film are formed on the side surfaces of the gate electrode and the step part, and after the ninth step, the electrode part side is formed. A step of siliciding the wall, the source / drain region, and the region extending over the stepped sidewall can be further provided.

By this method, the same operation as that of claim 6 or 8 can be obtained. Further, in the step of silicidizing the vicinity of the surface of the source / drain region, the surface of the sidewall of the step portion made of the silicon film is silicidized, but the penetration of the silicide layer into the depth is prevented. Therefore, it becomes possible to prevent the occurrence of a short circuit current between the source / drain electrodes and the substrate region such as the channel stop region. Moreover, since the silicided source / drain electrodes are formed over a wide range of the electrode portion sidewall-source / drain region-step portion sidewall, the contact portion can be easily formed from the upper layer wiring, and the semiconductor device It is also possible to reduce the area occupied by.

[0041]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) First, a first embodiment will be described with reference to FIGS. 1 and 2A to 2E. FIG. 1 is a cross-sectional view showing the structure of the semiconductor device according to the present embodiment, and FIGS. 2A to 2E are cross-sectional views showing a manufacturing process for realizing the structure of the semiconductor device shown in FIG. Is.

In FIG. 1, on a silicon substrate (or well) 1 of one conductivity type, a groove type element is provided in an element isolation region Reiso which divides a region near the surface of the silicon substrate 1 into a large number of element formation regions Refet. A separation 5a is formed. The surface of the element isolation 5a is sufficiently higher than the surface of the silicon substrate 1 in the element formation region Refet, and a step portion having a predetermined height difference is formed between them. This element isolation 5a
Is formed by embedding an insulating material in the groove formed in the silicon substrate 1 as described later. And
A channel stop region 15 of the same conductivity type as the silicon substrate 1 is formed at least at the bottom of the element isolation 5a.

On the other hand, in the element formation region Refet defined by the element isolation 5a, the gate electrode 4, the gate oxide film 3, the electrode side wall 8a, the low concentration source / drain region 6a, and the high concentration source / drain region are formed. A MOS transistor composed of 6b is formed. Further, a MOS transistor or the like having the source / drain electrodes 5 and the like made of a high-concentration impurity diffusion layer is formed. In addition, on the semiconductor substrate other than the element formation region Refet and the element isolation 5a
A gate wiring 7b and a wiring portion sidewall 7b, which are formed at the same time as the gate electrode 7a, are also formed thereon. Further, the upper portions of the gate electrode 7a, the gate wiring 7b, and the high-concentration source / drain region 6b are respectively composed of titanium silicide (TiSi2), and the upper gate electrode 9a, the upper gate wiring 9b, and the source / drain electrode 9 are formed.
c is formed.

Here, as a feature of this embodiment, a step portion side wall 8c formed at the same time as the electrode portion side wall 8a and the wiring portion side wall 8b is formed on the side surface of the step portion of the element isolation 5a. There is. A part of the step side wall 8c is connected to the electrode side wall 8a and the wiring side wall 8b.

The element isolation 5a and the gate electrode 7a are also provided.
An interlayer insulating film 11 and a first-layer metal wiring 12 are formed on the entire surface of the substrate on which the above-described elements are formed. The first-layer metal wiring 12 is connected through a contact portion 13 to the upper gate electrode in the element formation region. 9a and the source / drain electrode 9c.

Next, a manufacturing process for realizing the structure of FIG. 1 will be described with reference to FIGS.

First, as shown in FIG. 2A, a silicon oxide film 16 and a silicon nitride film 1 are formed on a silicon substrate 1.
7 is deposited, the photoresist film 20 which opens the element isolation region Reiso and covers the element formation region Refet is patterned, and then the silicon nitride film 17 and the silicon oxide film 16 are selectively removed using the photoresist film 20 as a mask. Then, the silicon substrate 1 is etched to form the groove 4
To form At this time, unlike the conventional groove method, the thickness of the silicon nitride film 17 is increased to about 150 to 200 nm, but the thickness of the silicon oxide film 16 is 10 to 20 nm as in the conventional method. . And the groove 4
The depth may be about the same as in the conventional method and is about 500 nm. After that, impurity ions of a conductivity type opposite to the conductivity type of impurities implanted into the source / drain regions to be formed later are implanted to form the channel stop region 15.

Next, as shown in FIG. 2B, after removing the photoresist film 20, a value obtained by adding the depth of the groove portion 4 and the thickness of the remaining silicon nitride film 17, that is, the groove portion 4.
An insulating film 5 (not shown) having a thickness which is more than the height from the bottom of the silicon nitride film 17 to the surface of the silicon nitride film 17 is deposited, and chemical mechanical polishing (CMP) is performed to remove the insulating film 5 from the silicon nitride film 17 The surface of the substrate is removed until it is exposed, and the entire surface of the substrate is flattened. By this step, a groove-type element isolation 5a made of the insulating film 5 is formed in the element isolation region Reiso. This flattening method is not limited to this embodiment, and a method of etching back using a reverse pattern of the element formation region Refet with a photoresist film may be used.

Thereafter, although not shown, the silicon nitride film 17 is removed using a boil phosphate solution or the like, and the silicon oxide film 16 is removed using a hydrofluoric acid-based wet etching solution or the like to form an element formation region Refet. The surface of the silicon substrate 1 is exposed. At this point, the element formation region Refet
The feature of this embodiment is that a step portion having a sufficient height difference is exposed between the surface of the silicon substrate 1 and the surface of the element isolation 5a. Considering the etching amount and the like, it is about 50 to 100 nm. However, in order to effectively obtain the effect of the present embodiment, it is necessary to properly determine the thickness and the over-etching amount of the sidewall insulating film when the sidewall is formed next.

Next, as shown in FIG. 2C, a polysilicon film 7 is deposited on the silicon substrate 1 and the element isolation 5a, and a polysilicon film 7 is formed on the polysilicon film 7 except the region where the gate electrode and the gate wiring are formed. A photoresist film 21 having an open area is formed. Although not shown, this photoresist film 2
Using 1 as a mask, dry etching is performed to pattern the gate electrode 7a and the gate wiring 7b.

Next, as shown in FIG. 2 (d), an insulating film (silicon oxide film) is deposited on the entire surface of the substrate, and this insulating film is anisotropically etched to obtain the structure shown in FIG. 2 (e). As shown, the electrode portion sidewall 8a is formed on the side surface of the gate electrode 7a, and the wiring portion sidewall 8b is formed on the side surface of the gate wiring 7b. At that time, the step portion sidewall 8c is also formed on the side surface of the step portion between the silicon substrate 1 and the element isolation 5a in the element formation region Refet. Then, in this state, the impurity ions are implanted to
The drain region 6b is formed. Even at this time, the height difference of the step portion between the silicon substrate 1 in the element formation region Refet and the element isolation 5a is sufficiently secured.

Although illustration of the subsequent steps is omitted, the upper gate electrode 9a and the upper gate wiring 9 by the silicide step are formed.
1b and the source / drain electrode 9c, the interlayer insulating film 11 is deposited and the contact hole is formed, the contact hole is filled with metal and the first-layer metal wiring 12 is formed, and then the groove shown in FIG. A MOS transistor having a buried isolation structure is formed.

In the above process, the electrode side wall 8 is formed to form the transistor having the LDD structure.
Although a and the like are formed, the electrode side wall 8a and the like are formed also in a transistor having a so-called pocket injection structure in which an impurity of opposite conductivity type is injected between the source / drain region and the channel region to provide a punch-through stopper. However, the present invention is also applied to a transistor having such a pocket injection structure.

When a MOS transistor having a gate length of 1 μm or less is formed as in this embodiment, a transistor having an LDD structure or a pocket injection structure for suppressing the short channel effect and ensuring the reliability of the transistor is used. In order to form it, it is necessary to form the electrode part sidewall 8a on the sidewall of the gate electrode 7a. The thickness of the electrode side wall 8a at this time is determined from the required characteristics of the device, but since it is formed by the dry etching technique having a strong anisotropy, the film thickness is controlled substantially by the deposited film thickness. Can be decided. However, in consideration of variations in etching rate within the wafer surface, variations in deposited film thickness, and the like, overetching is usually performed at about 10 to 30%. For example, when the electrode side wall 8a is formed from an insulating film having a thickness of 100 nm, 1
Etching is performed for a time corresponding to removing the insulating film having a thickness of 10 to 130 nm.

At this time, element isolation 5 made of an oxide film
Since a is etched with a higher selection ratio than the silicon substrate 1 in the element formation region Refet, a film loss of, for example, about 10 to 30 nm occurs. Therefore, in the conventional structure, as shown in FIGS. 8A and 8B, the surface of the element isolation 105a is lower than the surface of the silicon substrate 101, and the above-mentioned problems occur. On the other hand, in the present embodiment,
In the state shown in FIG. 2D, since the step portion is formed so that the surface of the element isolation 5a is higher than the silicon substrate surface of the element formation region Refet, it is possible to effectively prevent the above problems. You can That is, even when impurity ions are implanted from an oblique direction when forming the high-concentration source / drain regions 8b, the element isolation 5a at the step portion has a sufficient film thickness. Is stopped. Therefore, the distance between the high-concentration source / drain region 6b and the channel stop region 15 is kept substantially constant, and the deterioration of junction breakdown voltage and the increase of junction leak can be prevented. Also, when the source / drain electrodes 9c made of silicide are formed on the high-concentration source / drain regions 6b, the silicide layer erodes the boundary surface between the silicon substrate 1 and the element isolation 5a by the stepped side wall 8c. It can prevent you from trying. Therefore, it is possible to effectively prevent a short circuit current from occurring between the source / drain electrode 9c and the channel stop region 15.

However, in this embodiment, in order to effectively exhibit the above effects, at least the amount of overetching in the sidewall forming step, that is, 1
It is preferable that there is a film thickness reduction of about 0 to 30 nm or more. In addition, in practice, even after the element isolation 5a is formed, there is a step accompanied by the film reduction of the silicon oxide film forming the element isolation 5a, including the step of removing the silicon oxide film 16, so that the high and low values are taken into consideration in consideration of the film reduction amount. It is preferable to form a step having a difference in advance. Therefore, FIG.
Silicon nitride film 1 deposited in the step shown in FIG.
The lower limit of the film thickness of No. 7 is determined from the over-etching amount and the etching amount in the step of removing the silicon oxide film 16.

However, although the silicon nitride film 17 is used as the etching mask for forming the groove portion 4 in this embodiment, the material of this film may be any material having an etching selection ratio smaller than that of the silicon oxide film. It is also possible to substitute a polysilicon film or the like.

In the present embodiment, an embodiment having a so-called salicide structure in which the upper gate electrode 9a and the source / drain electrode 9c are simultaneously silicided in a self-aligned manner in order to reduce the resistance has been described. The electrode is formed with a polycide electrode in advance, and the source
It goes without saying that only the drain electrode may be silicided.

(Second Embodiment) Next, FIG.
The second embodiment will be described with reference to (e). The difference between this embodiment and the first embodiment is that
The point is that the deposition of the gate oxide film and the polysilicon film to be the gate electrode is completed before forming the trench type element isolation.

First, as shown in FIG. 3A, a gate oxide film 3 and a polysilicon film 7 to be a gate electrode of a MOS transistor are sequentially deposited on a silicon substrate 1, and element isolation formation is performed thereon. The photoresist film 20 that opens the region Reiso and covers the element formation region Refet is patterned. Using the photoresist film 20 as a mask, the polysilicon film 7 and the gate oxide film 3 are selectively removed,
Further, the silicon substrate 1 is etched to form a groove portion 4 which will be an element isolation region. At this time, unlike the conventional groove method, the thickness of the polysilicon film 7 is about the same as that of the silicon nitride film in the first embodiment, that is, 1
The thickness of the gate oxide film 3 is set to about 50 to 200 nm and is 10 to 20 nm. The depth of the groove 4 is 500n
m. After that, impurity ions of a conductivity type opposite to the conductivity type of impurities implanted into the source / drain regions to be formed later are implanted to form the channel stop region 15.

Next, after removing the photoresist film 20, a value obtained by adding the depth of the groove portion 4 and the thickness of the remaining polysilicon film 7, that is, the height from the bottom of the groove portion 4 to the surface of the polysilicon film 7. Insulation film 5 with sufficient thickness (not shown)
Is deposited and chemical mechanical polishing (CMP) is performed to remove the insulating film 5 until the surface of the polysilicon film 7 is exposed.
The entire substrate surface is flattened. By this step, the groove-type element isolation 5 formed of the insulating film 5 is formed in the element isolation region Reiso.
a is formed. This flattening method is not limited to this embodiment, and a method of etching back using a reverse pattern of the element formation region Refet with a photoresist film may be used.

Next, as shown in FIG. 3B, a conductive film 18 (conductive polysilicon film or a silicide film such as WSi or TiSi) which will be a gate electrode wiring layer is formed on the flattened substrate. Further, a refractory metal such as W may be used via a barrier metal such as TiN for lowering the resistance.) And a protective film 19 made of an insulating film are deposited to form a gate electrode and a gate wiring. A photoresist film 21 having an opening in a region other than the region is formed. Then, although not shown, dry etching is performed using the photoresist film 21 as a mask to pattern the gate electrode 7a, the upper gate electrode 18a and the protective film 19a, and the gate wiring 7b, the upper gate wiring 18b and the protective film 19b. To do. At this point, the silicon substrate 1 in the element formation region Refet
A feature of the present embodiment is that a step portion having a sufficient height difference is exposed between the surface and the surface of the element isolation 5a. The height difference is caused by the over-etching amount in the sidewall formation process described later. Considering 50-100n
m. However, in order to effectively obtain the effect of the present embodiment, it is necessary to properly determine the thickness and the over-etching amount of the sidewall insulating film when the sidewall is formed next.

Next, as shown in FIG. 3C, similarly to the first embodiment, an insulating film (silicon oxide film) is deposited on the entire surface of the substrate, and the insulating film is anisotropically etched. Then, as shown in FIG. 3D, the electrode portion sidewall 8a is formed on the side surface of the gate electrode 7a and the like, and the wiring portion sidewall 8b is formed on the side surface of the gate wiring 7b and the like. At that time, the step portion sidewall 8c is also formed on the side surface of the step portion between the silicon substrate 1 and the element isolation 5a in the element formation region Refet. Then, impurity ions are implanted in this state to form the high concentration source / drain regions 6b. Even at this time, the height difference of the step portion between the silicon substrate 1 in the element formation region Refet and the element isolation 5a is sufficiently secured.

Next, as shown in FIG. 3E, source / drain electrodes 9c made of silicide are formed only on the high-concentration source / drain regions 6b.

Although illustration of the subsequent steps is omitted, deposition of an interlayer insulating film 11 and formation of a contact hole, burying metal in the contact hole, and first-layer metal wiring 1
2 is formed, a MOS type transistor having a groove-separated isolation structure similar to the structure shown in FIG. 1 is formed. However, in the present embodiment, on the gate electrode 7a and the gate wiring 7b, the upper gate electrode 18a and the upper gate wiring 18b made of conductive polysilicon or silicide, respectively, and the protective films 19a and 1 made of an insulating film are formed.
9b is formed, and the source / drain electrode 9c made of silicide is used as the upper gate electrode 18a and the upper gate wiring 1
It is formed in a process different from 8b.

As described above, according to the present embodiment, a step portion having a high element isolation 5a side is formed between the silicon substrate 1 and the element isolation 5a in the element formation region Refet, and the step portion is formed on the side surface of the step portion. Since the sidewalls 8c are formed, it is possible to achieve the same effect as that of the first embodiment while reducing the number of steps.

In addition, in this embodiment, the step of patterning the gate electrode 7a and the gate wiring 7b from the state shown in FIG. 3B is completely performed without being affected by the stepped portion at the end of the element isolation 5a. Since it can be performed in a flat state, there is an advantage that a fine pattern can be stably formed.

(Third Embodiment) Next, a third embodiment will be described. 4A to 4F are cross-sectional views showing the manufacturing process of the semiconductor device according to the third embodiment.

By the time the state shown in FIG. 4A is reached, the trench type element isolation 5a, the channel stop region 15, the low concentration source / drain region 6a, the gate insulating film 3, the gate electrode 7a, the gate wiring 7b, etc. are formed. After forming by the same process as the first embodiment, a protective oxide film 31 is formed on the substrate,
Both the silicon nitride film 32 for the sidewall and the polysilicon film 33 for the mask are deposited by the CVD method. At this time, the thickness of the polysilicon film forming the gate electrode 7a and the gate wiring 7b is 330 nm, the minimum line width is 0.35 μm, and the thickness of the protective oxide film 31 is about 2 mm.
The thickness of the silicon nitride film 32 is about 30 nm.
The thickness of the polysilicon film 33 is about 100 nm.

Next, as shown in FIG. 4B, the polysilicon film 33 is etched back by RIE, and the electrode portion polysilicon mask 33a is formed on each side surface of the gate electrode 7a, the gate wiring 7b and the step portion. A wiring part polysilicon mask 33b and a step part polysilicon mask 33c are formed. At this time, the etching selection ratio between the polysilicon film 33 and the silicon nitride film 32 is large.

Next, as shown in FIG. 4C, wet etching with H3 PO4 (hot phosphoric acid at 150 ° C.) is performed using the remaining polysilicon masks 33a, 33b, 33c as masks to remove the silicon nitride film 32. Only the portion covered by each polysilicon mask 33a, 33b, 33c is left and the other portions are removed. At this time, the etching selection ratio between the silicon nitride film 32 and the polysilicon masks 33a, 33b, 33c can be set to about 30: 1. By this step, the gate electrode 7a and the gate wiring 7b
The L-shaped electrode part sidewall 32a, the wiring part sidewall 32b, and the step part sidewall 32c are left on each side of the step part.

Next, as shown in FIG. 4D, the gate electrode 7a, the protective oxide film 31, the electrode portion polysilicon mask 3 are formed.
3a, the electrode portion sidewall 32a, the stepped portion polysilicon mask 33c, and the stepped portion sidewall 32c are used as masks to implant high concentration impurity ions into the silicon substrate 1 in the active region to form high concentration source / drain regions 6b. To do.

Thereafter, as shown in FIG. 4E, the polysilicon masks 33a, 33b, 33c are removed by dry etching or wet etching.

Next, as shown in FIG. 4F, the protective oxide film 31 on the exposed portion on the substrate is removed by using an HF-based etching solution. Then, a titanium film is deposited and the first RTA process is performed to form a silicide layer made of a TiSi2 film by the reaction between titanium and silicon.
After removing the titanium film, a second RTA process is performed to form an upper electrode 9a made of a silicide layer having a low resistivity on the gate electrode 7a, the gate wiring 7b, and the source / drain region 6b, an upper wiring 9b, and The source / drain electrodes 9c are formed respectively. Then, an LSI is formed by depositing an interlayer insulating film, flattening, opening a contact hole, depositing a metal wiring film, forming a metal wiring, and the like.

In the method of this embodiment, since the protective oxide film 31c and the L-shaped step portion sidewall 32c are formed on the side surface of the step portion in the step shown in FIG. 4 (f),
It is possible to effectively prevent the silicide layer from entering the boundary between the silicon substrate 1 and the element isolation 5a in the active region.

Further, in the steps shown in FIGS. 4 (c) and 4 (d),
Since the protective oxide film 31 is formed on the element isolation 5a and the silicon substrate 1 in the active region, the element isolation 5 is formed when the L-shaped sidewalls 32a, 32b, 32c are formed.
The film thickness of a does not decrease. Therefore, the step difference between the element isolation 5a and the silicon substrate 1 can be reduced accordingly, and the patterning accuracy of the gate can be improved.

The step of forming the gate electrode may be performed by using the first and second conductive films as in the case of the second embodiment, and in that case, the same effect as that of the present embodiment is obtained. Can be demonstrated.

(Fourth Embodiment) In each of the above embodiments,
Although each of the sidewalls is made of a silicon oxide film or a silicon nitride film which is an insulating material, each of the sidewalls may be made of a conductive material such as a polysilicon film. 5A to 5E are cross-sectional views showing a manufacturing process of a semiconductor device when a conductive sidewall is formed.

By the time the state shown in FIG. 5A is reached, the trench type element isolation 5a, the channel stop region 15, the low concentration source / drain region 6a, the gate insulating film 3, the gate electrode 7a, the gate wiring 7b, etc. are formed. After forming by the same process as the first embodiment, a protective oxide film 31 is formed on the substrate,
The sidewall polysilicon film 34 and the polysilicon film 34 are both deposited by the CVD method. However, in the present embodiment, the protective oxide films 10a and 10b are formed on the gate electrode 7a and the gate wiring 7b, respectively. At this time,
The thickness of the polysilicon film forming the gate electrode 7a and the gate wiring 7b is 330 nm, the minimum line width is 0.35 μm, and the thickness of the protective oxide film 31 is about 20 nm.
The thickness of the polysilicon film 34 is about 100 nm.

Next, as shown in FIG. 5B, the polysilicon film 34 is etched back by RIE, and the polysilicon film is formed on each side of the gate electrode 7a, the gate wiring 7b, and the step portion. Electrode part side wall 32a, wiring part side wall 32b, and step part side wall 32
Form c.

Next, as shown in FIG. 5C, the gate electrode 7a, the protective oxide film 31, the electrode portion sidewall 34a.
Using the stepped sidewall 34c as a mask, impurity ions are implanted at high concentration into the silicon substrate 1 in the active region to form the high concentration source / drain regions 6b.

After that, as shown in FIG. 5D, the protective oxide film 31 on the exposed portion on the substrate is removed by using an HF-based etching solution. Then deposit a titanium film and
A second RTA process is performed to form a silicide layer made of a TiSi2 film by the reaction between titanium and silicon. Then, after removing the titanium film, a second RTA process is performed to perform the electrode part sidewall 34a, the high-concentration source / drain region 6b, and the step part sidewall 34.
A source / drain electrode 9d made of a silicide layer extending over c is formed. The wiring side wall 34b
Since the silicide layer is also formed on the above, the silicide layer can be directly connected to the source / drain electrodes. In the present embodiment, etching is performed on the element isolation 5a using a photoresist film or the like to form the gate wiring 7
The wiring part sidewalls 34b on both sides of b and the silicide layer thereon are selectively removed so that the source / drain electrodes 9d in each active region are not connected to each other. However, the sidewall 3 made of a polysilicon film
Immediately after forming 4a, 34b and 34c, only the wiring part sidewalls 34b on both sides of the gate wiring 7b may be selectively removed.

After that, an LSI is formed by depositing an interlayer insulating film, flattening, opening a contact hole, depositing a metal wiring film, forming a metal wiring, and the like.

In the present embodiment, finally, the source / drain electrodes 9c made of a silicide layer are formed in a wide range over the electrode side wall 34a-high-concentration source / drain region 6b-step side wall 8c. Therefore, due to the presence of the step between the element formation region Refet and the element isolation 5a, the high-concentration source / drain region 6b and the channel stop region 15 at the time of impurity ion implantation are formed.
It is possible to effectively prevent the proximity to. Further, when the source / drain electrodes 9c made of silicide are formed on the high-concentration source / drain regions 6b, the stepped sidewalls 34c are also silicided by a certain amount of thickness, but penetrate into the depth of the silicide layer. Therefore, it is possible to effectively prevent generation of a short-circuit current between the source / drain electrode 9c and the channel stop region 15 due to the penetration of the silicide layer into the interface between the element isolation and the silicon substrate. Moreover, in such an embodiment, since a wide region from the electrode side wall 34a to the stepped side wall 34c via the high-concentration source / drain regions 6b is silicided, contact with the upper first layer wiring is made. It becomes extremely easy to form the portion, and the area of the element formation region Refet can be reduced accordingly. That is,
There is an advantage that the degree of integration of the semiconductor device can be improved. Although the electrode side wall 34a and the wiring side wall 34b are made of polysilicon which is a conductive film, the protective oxide film 31 is formed between each side wall 34a, 34b and the gate electrode 7a and the gate wiring 7b.
Since it is insulated by, there is no possibility that a short circuit or the like will occur between the sidewall and the gate.

The step of forming the gate electrode may be performed by using the first and second conductive films as in the case of the second embodiment, and in that case, the same effect as that of the present embodiment is obtained. Can be demonstrated.

In the present embodiment, each sidewall is made of a polysilicon film, but it may be made of an amorphous silicon film. Furthermore, not only the silicon film,
A side wall made of a conductive material such as another metal may be formed, and it is not always necessary to silicidize the side wall.

[0087]

As described above, according to the semiconductor device of the first to third aspects, in the semiconductor device having the trench type element isolation structure, the trench is provided between the semiconductor substrate in the element forming region and the trench type element isolation. Since the stepped portion where the die element isolation becomes higher stepwise is formed and the sidewall is formed on the side surface of this stepped portion, the deterioration of the junction breakdown voltage and the increase of the junction leakage are prevented, and the source / drain electrode It is possible to prevent the occurrence of a short circuit current between the source / drain electrodes and the substrate region due to silicidation.

According to the fourth aspect, since each of the sidewalls is formed of the L-shaped silicon nitride film formed through the protective oxide film, in addition to the effect of the first aspect, the gate is reduced by the step difference. The finished size of the electrode can be improved.

According to the fifth aspect, each of the sidewalls is formed of a silicon film,
Since the source / drain electrodes made of the silicide layer are provided over a wide area extending over the source / drain regions and the side wall of the step portion, in addition to the effect of claim 1, the formation of the contact from the upper layer wiring is facilitated, and the semiconductor device is provided. The degree of integration can be improved.

According to the sixth or seventh aspect of the present invention, there is provided a method of manufacturing a semiconductor device having a trench type element isolation structure, wherein when the etching stopper film is removed after the trench type element isolation is formed,
The step of which the trench type element isolation side is higher than the semiconductor substrate in the element formation region is exposed so that the sidewall is formed on the side surface of the step at the same time when the sidewall of the gate electrode is formed. It is possible to facilitate the manufacturing of a semiconductor device that exhibits the above-mentioned characteristics.

According to claim 8 or 9, the etching stopper film in the method according to claim 6 or 7 is formed of a first conductive film capable of functioning as a gate electrode, and the gate electrode is formed of this first conductive film. Since it is formed with the second conductive film deposited thereon, the step of patterning the gate electrode can be performed in a fully flat state, and in addition to the effect of the method of claim 6 or 7, It is possible to improve the patterning accuracy of the gate electrode.

According to the tenth aspect of the present invention, since the step of siliciding the source / drain regions is further provided in the sixth or eighth aspect, the source / drain electrode having a low resistance is provided, and the low voltage and high speed operation is performed. A semiconductor device can be manufactured.

According to the eleventh aspect, in the sixth or the eighth aspect, after the gate electrode is patterned, a protective oxide film, a sidewall silicon nitride film and a masking film are deposited on the substrate and formed by etching back. Since the L-shaped sidewall is patterned from the silicon nitride film using the mask, the patterning accuracy of the gate electrode can be improved in addition to the effect of the sixth or eighth aspect.

According to a twelfth aspect, in the sixth or eighth aspect, the side wall of the gate electrode and the step portion is made of a silicon film, and the side surface of the gate electrode extends from the side surface of the source / drain region to the side surface of the step portion. Since the source / drain electrodes made of silicide are formed on the entire region, it is possible to manufacture a highly reliable and highly integrated semiconductor device.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a structure of a semiconductor device according to a first embodiment.

FIG. 2 is a sectional view illustrating a manufacturing process of the semiconductor device according to the first embodiment.

FIG. 3 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment.

FIG. 4 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the third embodiment.

FIG. 5 is a sectional view illustrating a manufacturing process of a semiconductor device according to a fourth embodiment.

FIG. 6 is a cross-sectional view showing the structure of a conventional semiconductor device having a groove-type element isolation structure.

FIG. 7 is a cross-sectional view showing a manufacturing process of a conventional semiconductor device having groove type element isolation.

FIG. 8 is a partial cross-sectional view showing a defect in the impurity ion implantation step and the silicidation step of the conventional semiconductor device having the groove type element isolation.

[Explanation of symbols]

 1 Silicon Substrate (Semiconductor Substrate) 3 Gate Oxide Film 4 Groove 5 Silicon Oxide Film (Insulating Film) 5a Groove Element Isolation 6a Low Concentration Source / Drain Region 6b High Concentration Source / Drain Region 7 Polysilicon Film (Conductive Film) 7a Gate Electrode 7b Gate wiring 8 Silicon oxide film 8a Electrode side wall 8b Wiring side wall 8c Stepped side wall 9a Upper gate electrode 9b Upper gate wiring 9c Source / drain electrode 11 Interlayer insulating film 12 First layer metal wiring 13 Contact section 15 channel stop region 16 silicon oxide film 17 silicon nitride film (etching stopper film) 20, 21 photoresist film

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[Procedure amendment]

[Submission date] July 16, 1996

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Full text

[Correction method] Change

[Correction contents]

[Document Name] Statement

Patent application title: Semiconductor device and manufacturing method thereof

[Claims]

4. The semiconductor device according to claim 1 , wherein at least a portion near the surface of the active region is silicided.
A semiconductor device , further comprising a source / drain electrode formed by forming a semiconductor.

A first step of forming a 5. underlay insulating film on a semiconductor substrate, a second step of depositing or falling edge of quenching stopper film on the underlay insulating film, the etching stopper film and the underlay insulating film A third step of forming an opening in a region where element isolation is to be formed and etching the semiconductor substrate in the opening to form a groove, and after depositing an isolation insulating film on the entire surface of the substrate , with planarized to the surface of the etching stopper film is exposed, and a fourth step of forming a trench isolation surrounding the element formation region in the groove by etching, at least the etching stopper layer and the underlay insulating film removal of the gate oxide film and the conductive film and the fifth step of exposing the step difference portion, on the substrate between the device formation region and the trench isolation After deposition, the patterning at least the gate electrode from the conductive layer
Step 6 , and after depositing the sidewall insulating film on the entire surface of the substrate,
Performing anisotropic etching, the electrode portions Saidowo made of the insulating film on the gate electrode and on each side of the step portion
No. 7 for forming a side wall and a step side wall respectively
And steps, eighth forming the source and drain regions by introducing impurities into the semiconductor substrate on both sides of the element forming region of the gate electrode
And a method for manufacturing a semiconductor device.

6. The method of manufacturing a semiconductor device according to claim 5, wherein in the second step, at least a predetermined value or more in the fifth step is taken into consideration in consideration of the over-etching amount in the seventh step. A method of manufacturing a semiconductor device, wherein a film thickness of an etching stopper film is determined so that a step having a difference is exposed.

7. A first step of forming a gate insulating film on a semiconductor substrate, a second step of depositing a first conductive film to be a gate electrode on the gate insulating film , and the first step. A third step of forming an opening in a region of the conductive film where a groove type element isolation is to be formed and etching the semiconductor substrate in the opening to form a groove, and an isolation insulating film is deposited on the entire surface of the substrate. after the substrate with at least the surface of the first conductive film substrate is planarized to expose a fourth step of forming a trench isolation surrounding the element formation region in the groove, which is the flattened A fifth step of depositing at least a second conductive film to be an upper gate electrode on the entire surface of the substrate, patterning at least the gate electrode from the first and second conductive films, and forming the element formation region and the trench type element. stage difference between the separation A sixth step of exposing the, after depositing an insulating film sidewall onto the entire surface of the substrate,
Performing anisotropic etching, the electrode portions Saidowo made of the insulating film on the gate electrode and on each side of the step portion
8 to form a seventh step of forming a Lumpur and the stepped portion side walls, the source and drain regions by introducing impurities into the semiconductor substrate on both sides of the element forming region of the gate electrode
And a method for manufacturing a semiconductor device.

8. The method of manufacturing a semiconductor device according to claim 7, wherein in the second step, at least a predetermined value or more in the fifth step is taken into consideration in consideration of the over-etching amount in the seventh step. A method of manufacturing a semiconductor device, characterized in that the film thickness of the first conductive film is determined so that a step having a difference is exposed.

9. The method according to claim 5 or 7, wherein, after completion of the eighth step, further comprising the step of siliciding the region in the vicinity of the surface of at least the source and drain regions A method of manufacturing a semiconductor device, comprising:

10. The method of manufacturing a semiconductor device according to claim 5 , wherein in the sixth step, a first protective insulating film is further deposited on the conductive film, and the first protective insulating film is deposited. film is patterned along with the gate electrode, the further comprises a step of depositing a second protective insulating film on the entire surface of the substrate prior to the sixth to the seventh step after step, in the seventh step, As a silicon film for sidewalls
Further comprising a step of depositing a silicon oxide film by means of a silicon oxide film, and silicidizing a region extending over the electrode side wall, the source / drain region and the step part side wall after the eighth step. Of manufacturing a semiconductor device.

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a structure of a semiconductor device having a groove-buried isolation type element isolation and a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, with the progress of higher integration and higher performance of semiconductor devices, there is an increasing demand for miniaturization.
Therefore, there is a technical field in which introduction of new technology is unavoidable because it is not possible to keep up with the demands only by improving conventional technology. For example, as an element isolation formation method, conventionally, element isolation has been formed by the LOCOS isolation method from the viewpoint of the manufacturing method's simplicity and low cost, but recently, in order to form a finer semiconductor device, a groove-embedded isolation method is used. It has been considered advantageous to provide the element isolation (hereinafter, simply referred to as groove type element isolation).

That is, since the LOCOS isolation method uses a selective oxidation method, so-called bird's beak occurs at the boundary with the mask for preventing the oxidation, and the isolation region is closer to the element region than the actual mask size. The insulating film invades to cause a dimensional change, and the amount of change becomes an unacceptable value for miniaturization after the 0.5 μm generation. Therefore, even in the field of mass production technology, the shift to the trench isolation method with extremely small size shift is beginning. For example, IBM has introduced a groove type element isolation structure for mass production of MPU as a 0.5 μm CMOS process (reference: IBM J
ouralof Research and Dev
element, VOL. 39, NO. 1/2, 19
95, 33-42).

FIG. 6 shows conventional trench isolation and salicide.
It is sectional drawing which shows the example of the semiconductor device in which the MOSFET which has a structure was provided. As shown in the figure, a groove-type element isolation 105a is formed on the silicon substrate 101. The gate insulating film 103a and the gate electrode 107 are formed on the active region surrounded by the element isolation 105a.
a and an electrode portion sidewall 108a on both side surfaces of the gate electrode 107a are provided. Further, in the active region, on both sides of the gate electrode 107a, the low concentration source / drain regions 106a and the high concentration source / drain regions 106a are formed.
A drain region 106b is provided and element isolation 105a is provided.
A channel stop region 115 is provided below. The gate electrode 107 over the top of the silicon substrate 101 which does not function as an element isolation 105 a及 beauty active region
A gate wiring 107b made of the same polysilicon film as a is provided via a gate insulating film 103b, and wiring side wall walls 108b are provided on both side surfaces thereof.
Further, on the gate electrode 107a, the gate wiring 107b, and the high-concentration source / drain region 106b, an upper gate electrode 109a made of silicide, an upper gate wiring 109b, and a source / drain electrode 109c, respectively.
Are provided. Further, the interlayer insulating film 111 made of a silicon oxide film, the metal wiring 112 formed on the interlayer insulating film 111, and the contact hole formed in the interlayer insulating film 111 are embedded to form the metal wiring 112 and the source / drain. A contact portion 113 that connects the electrode 109c is provided.

Next, referring to FIGS. 7A to 7E, the conventional trench type element isolation and MOSFET shown in FIG.
A manufacturing process of a semiconductor device having the above will be described.

First, as shown in FIG. 7A, silicon is used.
Silicon oxide film 116 and silicon are formed on the substrate 101.
A nitride film 117 is sequentially deposited, and an element isolation region is opened to form an element.
A resist film 120 covering the formation region is formed on the silicon nitride film 11
7 is formed, and then the resist film 120 is used as a mask
By etching, the silicon nitride film 116 and
The silicon oxide film 117 is selectively removed, and
The con substrate 101 is etched to form the groove 104.
You. Further, by implanting impurity ions into the bottom of the groove 104,
To form the channel stop region 115.

[0007] Next, as shown in FIG. 7 (b), a silicon
After depositing an oxide film (not shown), the silicon nitride film 1
The entire surface is flattened until the surface of 17 is exposed. This process
In the element isolation region Reiso,
Groove-type element isolation consisting of embedded silicon oxide film 1
05a is formed.

Next, as shown in FIG. 7 (c),
Silicon nitride film 117 and silicon oxide film 116 are removed
Then, the gate oxide film 10 is formed on the silicon substrate 101.
3 is formed, and the polysilicon film 107 is further formed on the entire surface of the substrate.
After depositing, a gate is formed on the polysilicon film 107.
The photoresist film 121 in which the area other than the area is opened
Form.

Next, as shown in FIG. 7D, the polysilicon film 107 is formed using the photoresist film 121 as a mask.
Of the polysilicon film 107 and
The gate oxide film 103 is selectively removed to form a gate electrode 107a of the MOSFET in the element formation region Refet and a gate wiring 107b extending over the element isolation 105a and the silicon substrate 101. Then, after removing the photoresist film 121, impurity ions are implanted into the silicon substrate 101 using the gate electrode 107a as a mask to form the low concentration source / drain regions 106a.
Then, a silicon oxide film 108 is deposited on the entire surface of the substrate.

Next, as shown in FIG. 7E, anisotropic dry etching of the silicon oxide film 108 is performed to form the electrode side wall 108a and the wiring on both side surfaces of the gate electrode 107a and the gate wiring 107b, respectively. The partial sidewall 108b is formed. At that time, the gate oxide film 103 below the silicon oxide film 108 is also removed at the same time, and only the gate oxide film 103a below the gate electrode 107a and the gate oxide film 103b below the gate wiring 107b remain. After that, impurity ions are obliquely implanted using the gate electrode 107a and the electrode portion sidewall 108a as a mask to form the high-concentration source / drain regions 106b. Then, after depositing a Ti film on the entire surface, a high temperature heat treatment is performed to react the Ti film with a member made of silicon which is in direct contact with the Ti film to cause an upper gate electrode 109a made of silicide and an upper gate wiring 109b. And the source / drain electrodes 109c are formed.

[0011] Subsequent steps are omitted Suruga finally 6
A semiconductor device including a MOSFET having the structure shown in FIG.
Is obtained. In FIG. 6 , a metal wiring 112 is formed on the interlayer insulating film 111, and the metal wiring 112 and the source
The drain electrode 109c is connected to a contact portion 113 made of a W plug or the like with a contact hole buried therein.

When the groove-type element isolation structure as described above is adopted, LO that forms a thick silicon oxide film by thermal oxidation is used.
Since the bird's beak, that is, the oxide film does not enter the active region unlike the COS method, the dimensional shift of the source / drain regions is suppressed. Then, in the step shown in FIG. 7C, the element isolation 105a and the silicon substrate 101 in the element formation region Refet are planarized.

[0013]

However, the semiconductor device having the element isolation of the trench structure as described above has the following problems.

That is, when the state shown in FIG. 7D is changed to the state shown in FIG.
8 is anisotropically etched to form each sidewall 108.
Although a and 108b are formed, it is necessary to perform overetching at that time. By this over-etching, the surface of the element isolation 105a is dug down to some extent.

8 (a) and 8 (b) are enlarged sectional views showing the vicinity of the boundary between the high concentration source / drain region 106b and the element isolation 105a at this time.

As shown in FIG. 7A, impurity ions are obliquely implanted between the step shown in FIG. 7D and the step shown in FIG. 7E to form the high concentration source / drain regions. 1
Although the step of forming 06b is performed, since the element isolation 105a is dug down to the lower side, the high concentration source / drain region 106b is formed below the end portion of the element isolation 105a during this ion implantation. Therefore, the high-concentration source / drain region 106b and the channel stop region 115 come close to each other, which causes problems such as deterioration of junction breakdown voltage and increase of junction leak.

Further, as shown in FIG. 8B, in the case where a Ti film or the like is deposited on the high-concentration source / drain region 106b and silicidation is made to react with silicon below, the silicide layer is a silicon substrate. 101 and element isolation 10
The interface with 5a is likely to be eroded, which may cause a short-circuit current between the source / drain electrode 109c made of silicide and the channel stop region 115.

The present invention has been made in view of the above circumstances, and an object thereof is to provide means for preventing the trench type element isolation region from being dug down due to overetching at the time of forming the sidewalls. It is an object of the present invention to provide a fine and high-performance semiconductor device having a groove type element isolation structure, without junction leakage, deterioration of junction breakdown voltage, short-circuit current, and the like, and a manufacturing method thereof.

[0019]

In order to achieve the above-mentioned object, the solution means taken by the present invention is such that the groove-type element isolation side is higher between the semiconductor substrate in the element formation region and the groove-type element isolation. Such a step portion is formed and a sidewall is provided on the step portion. Specifically, the means concerning the semiconductor device described in claims 1 to 4 and the method for manufacturing a semiconductor device described in claims 5 to 10 is taken.

A semiconductor device according to the present invention has a plurality of active regions on a semiconductor substrate, each of which has a semi-conductive region.
In a semiconductor device having a conductor element, the active
Has an upper surface that is higher than the surface of the region, and
Separate each active area while forming a step on the boundary of
Of the groove-type element isolation surrounding the
The step portion sidewall is formed on the side surface of the step portion .

With this structure, since the stepped portion in which the surface of the groove type element isolation is higher than the surface of the semiconductor substrate in the element forming region is provided at the end of the groove type element isolation, the impurity diffusion layer of the semiconductor device is formed. Impurity ions are prevented from being implanted below the end portion of the element isolation when the impurity ions are implanted during formation. Further, even when adopting the structure of providing the source / drain electrodes made of silicide, since the stepped side walls prevent the invasion into the depth of the silicide layer, the substrate regions such as the source / drain electrodes and the channel stop regions are blocked. It is possible to prevent a short-circuit current from being generated. Therefore, the deterioration of the isolation function between the semiconductor devices in the trench type element isolation can be prevented.

According to a second aspect of the present invention, in the first aspect, the step portion sidewall can be made of an insulating material.

As described in claim 3, in claim 1, the semiconductor element is formed on the active region.
The gate insulating film and the gate electrode formed on the active region.
Saw formed in the regions located on both sides of the gate electrode
A drain and a drain region,
Electrode side walls formed on both sides of the gate electrode
Further comprising a Le, as the step portion sidewall, and is formed simultaneously with the electrode portion side wall
Can be configured to .

As described in claim 4 , in claim 1, at least a portion near the surface of the active region is shielded.
It may further include source / drain electrodes which are formed into a silicide .

With this structure, the function of preventing the implantation of impurity ions by the side wall of the step portion and the function of preventing the penetration of the silicide layer into the depth of the silicide layer in the silicidation process can be obtained. In addition, since the source / drain electrodes made of the silicide layer are provided on the wide area extending over the electrode side wall, the source / drain region and the step side wall, it is easy and reliable to form the contact from the upper wiring. Therefore, the reliability is improved and the area of the element formation region can be reduced.

The first method for manufacturing a semiconductor device according to the present invention, as described in claim 5, underlay on a semiconductor substrate
A first step of forming a can insulating film, the region to form a second step of depositing or falling edge of quenching stopper film on the underlay insulating film, the isolation of the etching stopper layer and the underlay insulating film And a third step of forming a groove by etching the semiconductor substrate in the opening, and after depositing an isolation insulating film on the entire surface of the substrate , at least the surface of the etching stopper film is exposed on the substrate. A fourth step of forming a groove-type element isolation surrounding the element forming region in the groove while flattening the surface, and removing at least the etching stopper film and the underlying insulating film by etching to form the element forming region. a fifth step of exposing the stepped difference portion between the trench element isolation, after depositing a gate oxide film and a conductive film on the substrate, less the conductive film A sixth step of patterning the gate electrode with, after depositing the insulation <br/> Enmaku sidewall over the entire surface of the substrate, performing anisotropic etching, the gate electrode and each side of the step portion Overlying the electrode part sidewall and the step part sidewall made of the above-mentioned insulating film
The seventh step of respectively forming, and a eighth step of forming a source and drain region by introducing impurities into the semiconductor substrate on both sides of the element forming region of the gate electrode.

According to this method, since the step portion is formed between the semiconductor substrate in the element forming region and the trench type element isolation at the stage when the sixth step is completed, the impurity ion implantation in the eighth step is performed. At this time, the implantation of the impurity ions below the end of the trench type element isolation is prevented. Further, even when the vicinity of the surface of the source / drain region is silicidized later, the side wall of the step portion formed of the insulating film prevents the invasion of the silicide layer into the depth. Therefore, it is possible to prevent the junction breakdown voltage from deteriorating, the junction leak, and the like, and it is possible to prevent the occurrence of a short-circuit current between the source / drain electrodes and the substrate region such as the channel stop region.

As described in claim 6 , in claim 5 , in the second step, at least the over-etching amount in the eighth step is taken into consideration in the fifth step.
In the step of, the thickness of the etching stopper film can be determined so that the step portion having a height difference of a predetermined value or more is exposed.

According to this method, when the etching stopper film is removed in the fifth step, the height difference is ensured in consideration of the film reduction of the groove type element isolation due to the overetching amount. Therefore, the action of claim 5 can be effectively obtained.

The second method for fabricating a semiconductor device according to the present invention, as described in claim 7, gate on a semiconductor substrate
A first step of forming a gate insulating film , a second step of depositing a first conductive film to serve as a gate electrode on the gate insulating film , and a trench type element isolation of the first conductive film. A third step of opening a region to be formed and etching the semiconductor substrate in the opening to form a groove, and the whole surface of the substrate
After depositing the isolation insulating film on the substrate, the substrate is planarized until at least the surface of the first conductive film is exposed, and
A fourth step of forming a groove type element isolation surrounding the element forming region in the groove section, and a fifth step of depositing at least a second conductive film to be an upper gate electrode on the entire surface of the flattened substrate. When, with patterning at least the gate electrode from the first and second conductive films, a sixth step of exposing the stepped difference portion between the element forming region and the groove type element separation, over the entire surface of the substrate after depositing the sidewall insulating film by performing anisotropic etching, electrodeposition made of the insulating film on the gate electrode and on each side of the step portion
A seventh step of forming a pole sidewall and the step portion sidewall, and an eighth step of introducing an impurity to form source and drain regions in the semiconductor substrate on both sides of the element forming region of the gate electrode I have it.

According to this method, the same effect as that of the fifth aspect can be obtained, and in the step of patterning the gate electrode, the entire surface of the substrate is in a fully flat state.
The patterning accuracy of the gate electrode is improved.

[0032] As described in claim 8, in claim 8, in the second step, taking into account the amount of over-etching of at least the seventh step, the fifth
The film thickness of the conductive film can be determined so that a step having a height difference of a predetermined value or more is exposed in the step of.

With this method, the same effect as that of the sixth aspect can be obtained.

As described in claim 9 , claim 5 or
7 , the method may further include a step of silicidizing at least a region near the surface of the source / drain region after the eighth step is completed.

By this step, low-resistance source / drain electrodes are formed, so that a semiconductor device which operates at low voltage and high speed is formed.

As described in claim 10 , claim 5
Alternatively , in the sixth step, in the sixth step, a first protective insulating film is further deposited on the conductive film, and the first protective insulating film is patterned together with a gate electrode to form the sixth protective film.
Further comprising the step of depositing the second protective insulating film on the entire surface of the substrate prior to the seventh step after step, in the seventh step, silicon as the silicon film for the sidewall
After the eighth step, a step of silicidizing the electrode sidewall, the source / drain region, and the step portion sidewall may be further provided after depositing a conoxide film .

With this method, the same operation as in claim 5 or 7 can be obtained. Further, in the step of silicidizing the vicinity of the surface of the source / drain region, the surface of the sidewall of the step portion made of the silicon film is silicidized, but the penetration of the silicide layer into the depth is prevented. Therefore, it becomes possible to prevent the occurrence of a short circuit current between the source / drain electrodes and the substrate region such as the channel stop region. Moreover, since the silicided source / drain electrodes are formed over a wide range of the electrode portion sidewall-source / drain region-step portion sidewall, the contact portion can be easily formed from the upper layer wiring, and the semiconductor device It is also possible to reduce the area occupied by.

[0038]

BEST MODE FOR CARRYING OUT THE INVENTION (First Embodiment) First, a first embodiment will be described with reference to FIGS. 1 and 2A to 2E. FIG. 1 is a cross-sectional view showing the structure of the semiconductor device according to the present embodiment, and FIGS. 2A to 2E are cross-sectional views showing a manufacturing process for realizing the structure of the semiconductor device shown in FIG. Is.

In FIG. 1, on a silicon substrate (or well) 1 of one conductivity type, a groove type element is provided in an element isolation region Reiso that divides a region near the surface of the silicon substrate 1 into a large number of element formation regions Refet. A separation 5a is formed. The surface of the element isolation 5a is sufficiently higher than the surface of the silicon substrate 1 in the element formation region Refet, and a step portion having a predetermined height difference is formed between them. This element isolation 5a
Is formed by embedding an insulating material in the groove formed in the silicon substrate 1 as described later. And
A channel stop region 15 of the same conductivity type as the silicon substrate 1 is formed at least at the bottom of the element isolation 5a.

On the other hand, in the element forming region Refet defined by the element isolation 5a, the gate electrode 4, the gate oxide film 3, the electrode side wall 8a, the low concentration source / drain region 6a, and the high concentration source / drain region are formed. MOS transistor consisting 6b is that has been formed. Also, even the element formation region on a semiconductor substrate other than Refet and isolation 5a on, the gate electrode 7a at the same time formed the gate line 7b and the wiring portion side walls 7b are formed.
Further, the upper portions of the gate electrode 7a, the gate wiring 7b, and the high-concentration source / drain regions 6b are formed of titanium silicide (TiSi2), respectively.
a, upper gate wiring 9b and source / drain electrodes 9c
Are formed.

Here, as a feature of this embodiment, a step portion sidewall 8c formed at the same time as the electrode portion sidewall 8a and the wiring portion sidewall 8b is formed on the side surface of the step portion of the element isolation 5a. There is. A part of the step side wall 8c is connected to the electrode side wall 8a and the wiring side wall 8b.

The element isolation 5a and the gate electrode 7a are also provided.
An interlayer insulating film 11 and a first-layer metal wiring 12 are formed on the entire surface of the substrate on which the above-described elements are formed. The first-layer metal wiring 12 is connected through a contact portion 13 to the upper gate electrode in the element formation region. 9a and the source / drain electrode 9c.

Next, a manufacturing process for realizing the structure shown in FIG. 1 will be described with reference to FIGS.

First, as shown in FIG. 2A, a silicon oxide film 16 and an etching stopper are formed on the silicon substrate 1.
After depositing a silicon nitride film 17 serving as a barrier film, patterning the photoresist film 20 which opens the element isolation region Reiso and covers the element formation region Refet,
The silicon nitride film 17 and the silicon oxide film 16 are selectively removed using the mask as a mask, and the silicon substrate 1
Is etched to form the groove portion 4. At this time, unlike the conventional groove method, the thickness of the silicon nitride film 17 is set to 1
The thickness of the silicon oxide film 16 is set to about 50 to 200 nm, but the thickness of the silicon oxide film 16 is set to 10 to 20 n as in the conventional method.
m. The depth of the groove 4 may be about the same as in the conventional method and is about 500 nm. After that, impurity ions of a conductivity type opposite to the conductivity type of impurities implanted into the source / drain regions to be formed later are implanted to form the channel stop region 15.

Next, as shown in FIG. 2B, after removing the photoresist film 20, a value obtained by adding the depth of the groove portion 4 and the thickness of the remaining silicon nitride film 17, that is, the groove portion 4.
An insulating film 5 (not shown) having a thickness which is more than the height from the bottom of the silicon nitride film 17 to the surface of the silicon nitride film 17 is deposited, and chemical mechanical polishing (CMP) is performed to remove the insulating film 5 from the silicon nitride film 17 The surface of the substrate is removed until it is exposed, and the entire surface of the substrate is flattened. By this step, a groove-type element isolation 5a made of the insulating film 5 is formed in the element isolation region Reiso. This flattening method is not limited to this embodiment, and a method of etching back using a reverse pattern of the element formation region Refet with a photoresist film may be used.

Thereafter, although not shown, the silicon nitride film 17 is removed by using a phosphoric acid boil solution or the like, and further, the silicon oxide film 16 is removed by using a hydrofluoric acid-based wet etching solution or the like to form an element formation region Refet. The surface of the silicon substrate 1 is exposed. At this point, the element formation region Refet
The feature of this embodiment is that a step portion having a sufficient height difference is exposed between the surface of the silicon substrate 1 and the surface of the element isolation 5a. Considering the etching amount and the like, it is about 50 to 100 nm. However, in order to effectively obtain the effect of the present embodiment, it is necessary to properly determine the thickness and the over-etching amount of the sidewall insulating film when the sidewall is formed next.

Next, as shown in FIG. 2C, a polysilicon film 7 is deposited on the silicon substrate 1 and the element isolation 5a, and a polysilicon film 7 is formed on the polysilicon film 7 except the region where the gate electrode and the gate wiring are formed. A photoresist film 21 having an open area is formed. Although not shown, this photoresist film 2
1 as a mask, dry etching is performed to form the gate electrode 7a and the gate wiring 7b.

Next, as shown in FIG.
Impurity ions of low concentration are implanted using the pole 7a as a mask.
After forming the low concentration source / drain regions 6a,
An insulating film (silicon oxide film) is deposited on the entire surface of the plate.

Next, as shown in FIG.
Anisotropic etching is performed on the film to form the electrode side wall 8a on the side surface of the gate electrode 7a and the wiring side wall 8b on the side surface of the gate wiring 7b. At that time, the element isolation region Refet and the silicon substrate 1 and the element isolation 5
The side wall 8 of the step portion is also formed on the side surface of the step portion between a and
c is formed. Then, impurity ions are implanted in this state to form the high concentration source / drain regions 6b. Even at this time, the height difference of the step portion between the silicon substrate 1 in the element formation region Refet and the element isolation 5a is sufficiently secured.

Although illustration of subsequent steps is omitted, the upper gate electrode 9a and the upper gate wiring 9 by the silicide step are formed.
1b and the source / drain electrode 9c, the interlayer insulating film 11 is deposited and the contact hole is formed, the contact hole is filled with metal and the first-layer metal wiring 12 is formed, and then the groove shown in FIG. A MOS transistor having a buried isolation structure is formed.

In the above process, the electrode side wall 8 is formed in order to form the transistor having the LDD structure.
Although a and the like are formed, the electrode side wall 8a and the like are formed also in a transistor having a so-called pocket injection structure in which an impurity of opposite conductivity type is injected between the source / drain region and the channel region to provide a punch-through stopper. However, the present invention is also applied to a transistor having such a pocket injection structure.

When a MOS transistor having a gate length of 1 μm or less is formed as in this embodiment, a transistor having an LDD structure or a pocket injection structure for suppressing the short channel effect and ensuring the reliability of the transistor is formed. In order to form it, it is necessary to form the electrode part sidewall 8a on the sidewall of the gate electrode 7a. The thickness of the electrode side wall 8a at this time is determined from the required characteristics of the device, but since it is formed by the dry etching technique having a strong anisotropy, the film thickness is controlled substantially by the deposited film thickness. Can be decided. However, in consideration of variations in etching rate within the wafer surface, variations in deposited film thickness, and the like, overetching is usually performed at about 10 to 30%. For example, when the electrode side wall 8a is formed from an insulating film having a thickness of 100 nm, 1
Etching is performed for a time corresponding to removing the insulating film having a thickness of 10 to 130 nm.

At this time, the element isolation 5 composed of an oxide film
Since a is etched with a higher selection ratio than the silicon substrate 1 in the element formation region Refet, a film loss of, for example, about 10 to 30 nm occurs. Therefore, in the conventional structure, as shown in FIGS. 8A and 8B, the surface of the element isolation 105a is lower than the surface of the silicon substrate 101, and the above-mentioned problems occur. On the other hand, in the present embodiment,
In the state shown in FIG. 2D, since the step portion is formed so that the surface of the element isolation 5a is higher than the silicon substrate surface of the element formation region Refet, it is possible to effectively prevent the above problems. You can That is, even when impurity ions are implanted from an oblique direction when forming the high-concentration source / drain regions 8b, the element isolation 5a at the step portion has a sufficient film thickness. Is stopped. Therefore, the distance between the high-concentration source / drain region 6b and the channel stop region 15 is kept substantially constant, and the deterioration of junction breakdown voltage and the increase of junction leak can be prevented. Also, when the source / drain electrodes 9c made of silicide are formed on the high-concentration source / drain regions 6b, the silicide layer erodes the boundary surface between the silicon substrate 1 and the element isolation 5a by the stepped side wall 8c. It can prevent you from trying. Therefore, it is possible to effectively prevent a short circuit current from occurring between the source / drain electrode 9c and the channel stop region 15.

However, in this embodiment, in order to effectively exert the above-mentioned effects, at least the over-etching amount in the sidewall forming step, that is, 1
It is preferable that there is a film thickness reduction of about 0 to 30 nm or more. In addition, in practice, even after the element isolation 5a is formed, there is a step accompanied by the film reduction of the silicon oxide film forming the element isolation 5a, including the step of removing the silicon oxide film 16, so that the high and low values are taken into consideration in consideration of the film reduction amount. It is preferable to form a step having a difference in advance. Therefore, FIG.
Silicon nitride film 1 deposited in the step shown in FIG.
The lower limit of the film thickness of No. 7 is determined from the over-etching amount and the etching amount in the step of removing the silicon oxide film 16.

However, in the present embodiment, the silicon nitride film 17 is used as the etching mask for forming the groove portion 4, but the material of this film may be any material having an etching selection ratio smaller than that of the silicon oxide film, for example, It is also possible to substitute a polysilicon film or the like.

In the present embodiment, an embodiment having a so-called salicide structure in which the upper gate electrode 9a and the source / drain electrode 9c are simultaneously silicided in a self-aligned manner in order to reduce the resistance has been described. The electrode is formed with a polycide electrode in advance, and the source
It goes without saying that only the drain electrode may be silicided.

(Second Embodiment) Next, FIG.
The second embodiment will be described with reference to (e). The difference between this embodiment and the first embodiment is that
The point is that the deposition of the gate oxide film and the polysilicon film to be the gate electrode is completed before forming the trench type element isolation.

First, as shown in FIG. 3A, a gate oxide film 3 and a polysilicon film 7 to be a gate electrode of a MOS transistor are sequentially deposited on a silicon substrate 1, and element isolation formation is performed thereon. The photoresist film 20 that opens the region Reiso and covers the element formation region Refet is patterned. Using the photoresist film 20 as a mask, the polysilicon film 7 and the gate oxide film 3 are selectively removed,
Further, the silicon substrate 1 is etched to form a groove portion 4 which will be an element isolation region. At this time, the shape of the conventional groove
Unlike the forming method, the film thickness of the polysilicon film 7 is set to about the same as the silicon nitride film in the first embodiment, that is, about 150 to 200 nm, and the film thickness of the gate oxide film 3 is 10 to 20 nm. is there. The depth of the groove 4 is 5
It is about 00 nm. Then the source formed later
Impurity ions having a conductivity type opposite to that of the impurities implanted into the drain region are implanted to form the channel stop region 15.

Next, after removing the photoresist film 20, a value obtained by adding the depth of the groove 4 and the thickness of the remaining polysilicon film 7, that is, the height from the bottom of the groove 4 to the surface of the polysilicon film 7. Insulation film 5 with sufficient thickness (not shown)
Is deposited and chemical mechanical polishing (CMP) is performed to remove the insulating film 5 until the surface of the polysilicon film 7 is exposed.
The entire substrate surface is flattened. By this step, the groove-type element isolation 5 formed of the insulating film 5 is formed in the element isolation region Reiso.
a is formed. This flattening method is not limited to this embodiment, and a method of etching back using a reverse pattern of the element formation region Refet with a photoresist film may be used.

Next, as shown in FIG. 3 (b), may be a conductive film 18 (conductive polysilicon film serving as a gate wiring layer on a planarized substrate, a silicide film such as WSi or TiSi Further, a refractory metal such as W may be used via a barrier metal such as TiN to reduce the resistance.) And a protective film 19 made of an insulating film are deposited to form a gate electrode and a gate wiring. A photoresist film 21 having an opening other than the exposed area is formed. Then, although not shown, dry etching is performed using the photoresist film 21 as a mask to pattern the gate electrode 7a, the upper gate electrode 18a and the protective film 19a, and the gate wiring 7b, the upper gate wiring 18b and the protective film 19b. To do. At this point, the silicon substrate 1 in the element formation region Refet
A feature of the present embodiment is that a step portion having a sufficient height difference is exposed between the surface and the surface of the element isolation 5a. The height difference is caused by the over-etching amount in the sidewall formation process described later. Considering 50-100n
m. However, in order to effectively obtain the effect of the present embodiment, it is necessary to properly determine the thickness and the over-etching amount of the sidewall insulating film when the sidewall is formed next.

Next, as shown in FIG. 3C , both sides of the gate electrode 7a in the active region are formed as in the first embodiment.
The low concentration source / drain region 6a is formed in the region
After the formation, an insulating film (silicon oxide film) is deposited on the entire surface of the substrate, and the insulating film is anisotropically etched to form the insulating film shown in FIG.
As shown in (d), an electrode portion sidewall 8a is formed on the side surface of the gate electrode 7a and the like, and a wiring portion sidewall 8b is formed on the side surface of the gate wiring 7b and the like. At that time, the step portion sidewall 8c is also formed on the side surface of the step portion between the silicon substrate 1 and the element isolation 5a in the element formation region Refet. Then, impurity ions are implanted in this state to form the high concentration source / drain regions 6b. Even at this time, the height difference of the step portion between the silicon substrate 1 in the element formation region Refet and the element isolation 5a is sufficiently secured.

Next, as shown in FIG. 3E, source / drain electrodes 9c made of silicide are formed only on the high-concentration source / drain regions 6b.

Although illustration of subsequent steps is omitted, deposition of an interlayer insulating film 11 and formation of a contact hole, burying metal in the contact hole, and first-layer metal wiring 1
2 is formed, a MOS type transistor having a groove-separated isolation structure similar to the structure shown in FIG. 1 is formed. However, in the present embodiment, on the gate electrode 7a and the gate wiring 7b, the upper gate electrode 18a and the upper gate wiring 18b made of conductive polysilicon or silicide, respectively, and the protective films 19a and 1 made of an insulating film are formed.
9b is formed, and the source / drain electrode 9c made of silicide is used as the upper gate electrode 18a and the upper gate wiring 1
It is formed in a process different from 8b.

As described above, according to the present embodiment, a step portion having a high element isolation 5a side is formed between the silicon substrate 1 and the element isolation 5a in the element formation region Refet, and the step portion is formed on the side surface of the step portion. Since the sidewalls 8c are formed, it is possible to achieve the same effect as that of the first embodiment while reducing the number of steps.

In addition, in the present embodiment, the step of patterning the gate electrode 7a and the gate wiring 7b from the state shown in FIG. 3B is completely performed without being affected by the stepped portion at the end of the element isolation 5a. Since it can be performed in a flat state, there is an advantage that a fine pattern can be stably formed.

(Third Embodiment) Next, a third embodiment will be described. 4A to 4F are cross-sectional views showing the manufacturing process of the semiconductor device according to the third embodiment.

By the time the state shown in FIG. 4A is reached, the trench type element isolation 5a, the channel stop region 15, the low concentration source / drain region 6a, the gate insulating film 3, the gate electrode 7a, the gate wiring 7b, etc. are formed. After forming by the same process as the first embodiment, a protective oxide film 31 is formed on the substrate,
Both the silicon nitride film 32 for the sidewall and the polysilicon film 33 for the mask are deposited by the CVD method. At this time, the thickness of the polysilicon film forming the gate electrode 7a and the gate wiring 7b is 330 nm, the minimum line width is 0.35 μm, and the thickness of the protective oxide film 31 is about 2 mm.
The thickness of the silicon nitride film 32 is about 30 nm.
The thickness of the polysilicon film 33 is about 100 nm.

Next, as shown in FIG. 4B, the polysilicon film 33 is etched back by RIE, and the electrode portion polysilicon mask 33a is formed on each side surface of the gate electrode 7a, the gate wiring 7b and the step portion. A wiring part polysilicon mask 33b and a step part polysilicon mask 33c are formed. At this time, the etching selection ratio between the polysilicon film 33 and the silicon nitride film 32 is large.

Next, as shown in FIG. 4C, wet etching with H3 PO4 (hot phosphoric acid at 150 ° C.) is performed using the remaining polysilicon masks 33a, 33b, 33c as masks to remove the silicon nitride film 32. Only the portion covered by each polysilicon mask 33a, 33b, 33c is left and the other portions are removed. At this time, the etching selection ratio between the silicon nitride film 32 and the polysilicon masks 33a, 33b, 33c can be set to about 30: 1. By this step, the gate electrode 7a and the gate wiring 7b
The L-shaped electrode part sidewall 32a, the wiring part sidewall 32b, and the step part sidewall 32c are left on each side of the step part.

Next, as shown in FIG. 4D, the gate electrode 7a, the protective oxide film 31, the electrode portion polysilicon mask 3 are formed.
3a, the electrode portion sidewall 32a, the stepped portion polysilicon mask 33c, and the stepped portion sidewall 32c are used as masks to implant high concentration impurity ions into the silicon substrate 1 in the active region to form high concentration source / drain regions 6b. To do.

Thereafter, as shown in FIG. 4E, the polysilicon masks 33a, 33b, 33c are removed by dry etching or wet etching.

Next, as shown in FIG. 4F, the protective oxide film 31 on the exposed portion on the substrate is removed using an HF-based etching solution. Then, a titanium film is deposited and the first RTA process is performed to form a silicide layer made of a TiSi2 film by the reaction between titanium and silicon.
After removing the titanium film, a second RTA process is performed to form an upper electrode 9a made of a silicide layer having a low resistivity on the gate electrode 7a, the gate wiring 7b, and the source / drain region 6b, an upper wiring 9b, and The source / drain electrodes 9c are formed respectively. Then, an LSI is formed by depositing an interlayer insulating film, flattening, opening a contact hole, depositing a metal wiring film, forming a metal wiring, and the like.

[0073] In the method of this embodiment, in the step shown in FIG. 4 (f), since the step portion sidewall 32c side of the protective oxide film 3 1及 beauty L-shape on the step portion is formed, the active It is possible to effectively prevent the silicide layer from entering the boundary between the silicon substrate 1 and the element isolation 5a in the region.

Further, in the steps shown in FIGS. 4 (c) and 4 (d),
Since the protective oxide film 31 is formed on the element isolation 5a and the silicon substrate 1 in the active region, the element isolation 5 is formed when the L-shaped sidewalls 32a, 32b, 32c are formed.
The film thickness of a does not decrease. Therefore, the step difference between the element isolation 5a and the silicon substrate 1 can be reduced accordingly, and the patterning accuracy of the gate can be improved.

The step of forming the gate electrode may be performed by using the first and second conductive films as in the case of the second embodiment, and in that case, the same effect as that of the present embodiment is obtained. Can be demonstrated.

(Fourth Embodiment) In each of the above embodiments,
Although each of the sidewalls is made of a silicon oxide film or a silicon nitride film which is an insulating material, each of the sidewalls may be made of a conductive material such as a polysilicon film. 5A to 5E are cross-sectional views showing a manufacturing process of a semiconductor device when a conductive sidewall is formed.

Before reaching the state shown in FIG. 5A, the trench type element isolation 5a, the channel stop region 15, the low concentration source / drain region 6a, the gate insulating film 3, the gate electrode 7a, the gate wiring 7b, etc. are formed. After forming by the same process as the first embodiment, a protective oxide film 31 is formed on the substrate,
The sidewall polysilicon film 34 and the polysilicon film 34 are both deposited by the CVD method. However, in the present embodiment, the protective oxide films 10a and 10b are formed on the gate electrode 7a and the gate wiring 7b, respectively. At this time,
The thickness of the polysilicon film forming the gate electrode 7a and the gate wiring 7b is 330 nm, the minimum line width is 0.35 μm, and the thickness of the protective oxide film 31 is about 20 nm.
The thickness of the polysilicon film 34 is about 100 nm.

Next, as shown in FIG. 5B, the polysilicon film 34 is etched back by RIE, and the polysilicon film is formed on each side of the gate electrode 7a, the gate wiring 7b, and the step portion. Electrode part side wall 32a, wiring part side wall 32b, and step part side wall 32
Form c.

Next, as shown in FIG. 5C, the gate electrode 7a, the protective oxide film 31, the electrode side wall 34a.
Using the stepped sidewall 34c as a mask, impurity ions are implanted at high concentration into the silicon substrate 1 in the active region to form the high concentration source / drain regions 6b.

After that, as shown in FIG. 5D, the protective oxide film 31 on the exposed portion on the substrate is removed by using an HF-based etching solution. Then deposit a titanium film and
A second RTA process is performed to form a silicide layer made of a TiSi2 film by the reaction between titanium and silicon. Then, after removing the titanium film, a second RTA process is performed to perform the electrode part sidewall 34a, the high-concentration source / drain region 6b, and the step part sidewall 34.
A source / drain electrode 9d made of a silicide layer extending over c is formed. The wiring side wall 34b
Since the silicide layer is also formed on the above, the silicide layer can be directly connected to the source / drain electrodes. In the present embodiment, etching is performed on the element isolation 5a using a photoresist film or the like to form the gate wiring 7
The wiring part sidewalls 34b on both sides of b and the silicide layer thereon are selectively removed so that the source / drain electrodes 9d in each active region are not connected to each other. However, the sidewall 3 made of a polysilicon film
Immediately after forming 4a, 34b and 34c, only the wiring part sidewalls 34b on both sides of the gate wiring 7b may be selectively removed.

After that, deposition of an interlayer insulating film, planarization, opening of a contact hole, deposition of a metal wiring film, formation of a metal wiring, etc. are performed to form an LSI.

[0082] In this embodiment, the source and drain electrodes 9 d comprising a wide range of final span between the electrode portion side walls 34a- high concentration source and drain regions 6b- step portion sidewall 8c silicide layer is formed . Therefore, due to the presence of the step between the element formation region Refet and the element isolation 5a, the high-concentration source / drain region 6b and the channel stop region 15 at the time of impurity ion implantation are formed.
It is possible to effectively prevent the proximity to. Further, when the source / drain electrodes 9c made of silicide are formed on the high-concentration source / drain regions 6b, the stepped sidewalls 34c are also silicided by a certain amount of thickness, but penetrate into the depth of the silicide layer. Therefore, it is possible to effectively prevent generation of a short-circuit current between the source / drain electrode 9c and the channel stop region 15 due to the penetration of the silicide layer into the interface between the element isolation and the silicon substrate. Moreover, in such an embodiment, since a wide region from the electrode side wall 34a to the stepped side wall 34c via the high-concentration source / drain regions 6b is silicided, contact with the upper first layer wiring is made. It becomes extremely easy to form the portion, and the area of the element formation region Refet can be reduced accordingly. That is,
There is an advantage that the degree of integration of the semiconductor device can be improved. Although the electrode side wall 34a and the wiring side wall 34b are made of polysilicon which is a conductive film, the protective oxide film 31 is formed between each side wall 34a, 34b and the gate electrode 7a and the gate wiring 7b.
Since it is insulated by, there is no possibility that a short circuit or the like will occur between the sidewall and the gate.

The step of forming the gate electrode may be performed by using the first and second conductive films as in the case of the second embodiment, and in that case, the same effect as that of the present embodiment is obtained. Can be demonstrated.

Further, in the present embodiment, each sidewall is made of a polysilicon film, but it may be made of an amorphous silicon film. Furthermore, not only the silicon film,
A side wall made of a conductive material such as another metal may be formed, and it is not always necessary to silicidize the side wall.

[0085]

As described above, according to the first to fourth aspects, in the semiconductor device having the groove type element isolation structure,
A step portion is formed between the semiconductor substrate in the element formation region and the groove-type element isolation so that the groove-type element isolation is stepwise higher.
Since the side wall is formed on the side surface of the stepped portion, deterioration of junction breakdown voltage and increase of junction leakage are prevented, and short circuit current between the source / drain electrode and the substrate region due to silicidation of the source / drain electrode is prevented. Occurrence can be prevented.

[0086] According to claim 5 to 10, as a method of manufacturing a semiconductor device having a trench isolation structure, it an etching stopper film or the gate electrode after forming a trench isolation
When the first conductive film is removed, the stepped portion on the isolation side of the groove type, which is higher than the semiconductor substrate in the element formation region, is exposed,
Since the sidewall is formed on the side surface of the step portion at the same time when the sidewall of the gate electrode is formed, it is possible to facilitate the manufacture of a semiconductor device exhibiting the effects of the first to fourth aspects.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a structure of a semiconductor device according to a first embodiment.

FIG. 2 is a sectional view illustrating a manufacturing process of the semiconductor device according to the first embodiment.

FIG. 3 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment.

FIG. 4 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the third embodiment.

FIG. 5 is a sectional view illustrating a manufacturing process of a semiconductor device according to a fourth embodiment.

FIG. 6 is a cross-sectional view showing the structure of a conventional semiconductor device having a groove-type element isolation structure.

FIG. 7 is a cross-sectional view showing a manufacturing process of a conventional semiconductor device having groove type element isolation.

FIG. 8 is a partial cross-sectional view showing a defect in the impurity ion implantation step and the silicidation step of the conventional semiconductor device having the groove type element isolation.

[Explanation of symbols] 1 silicon substrate (semiconductor substrate) 3 gate oxide film 4 groove part 5 silicon oxide film (insulating film) 5a groove type element isolation 6a low concentration source / drain region 6b high concentration source / drain region 7 polysilicon film ( Conductive film) 7a Gate electrode 7b Gate wiring 8 Silicon oxide film 8a Electrode side wall 8b Wiring side wall 8c Step side wall 9a Upper gate electrode 9b Upper gate wiring 9c Source / drain electrode 11 Interlayer insulating film 12 First layer Metal wiring 13 Contact part 15 Channel stop region 16 Silicon oxide film 17 Silicon nitride film (etching stopper film) 20, 21 Photoresist film

[Procedure amendment 2]

[Document name to be amended] Drawing

[Name of item to be corrected] Figure 7

[Correction method] Change

[Correction contents]

FIG. 7

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Takashi Nakabayashi 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Kyoji Yamashita, 1006 Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd. (72) Inventor Takaaki Ueda 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Inventor, Masatoshi Arai 1006 Kadoma, Kadoma City, Osaka Prefecture (72) Takashi Yamada, Inventor Shun 1006, Kadoma, Kadoma-shi, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Inventor, Doichi Matsumoto, 1006 Kadoma, Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (12)

[Claims] 1. A semiconductor substrate, an element formation region provided in a part of the semiconductor substrate, and a stepped shape surrounding the element formation region and between the element formation region more than the semiconductor substrate in the element formation region. A groove-type element isolation made of an insulating material and having a step portion that becomes higher in height, and a step-portion sidewall formed on a side surface of the step portion between the element forming region and the groove-type element isolation. A semiconductor device characterized by the above. 2. The semiconductor device according to claim 1, wherein the step portion side wall is made of an insulating material. 3. The semiconductor device according to claim 1, wherein a MISFET having a gate electrode and electrode sidewalls on both side surfaces of the gate electrode is formed in the element formation region, and the stepped sidewall is formed. Is a semiconductor device formed at the same time as the electrode part sidewall. 4. The semiconductor device according to claim 3, wherein the electrode side wall is formed in an L-shape having a substantially constant thickness over the side surface of the gate electrode and the semiconductor substrate via a protective oxide film. Formed of a silicon nitride film, the stepped portion sidewall is formed over the side surface of the stepped portion between the element forming region and the trench type element isolation and the semiconductor substrate through a protective oxide film. A semiconductor device comprising an L-shaped silicon nitride film having a constant thickness. 5. The semiconductor device according to claim 3, wherein both the electrode side wall and the stepped side wall are made of a silicon film, and between the electrode side wall and the gate electrode and the silicon substrate. And a source / drain electrode made of silicide, which is formed on a region extending from the electrode side wall to the step side wall through the source / drain region of the element formation region and the insulating film interposed between A semiconductor device further comprising: 6. A first step of forming an oxide film on a semiconductor substrate, a second step of depositing an etching stopper film made of a material different from that of the oxide film on the oxide film, A third step of opening a region of the etching stopper film where element isolation is to be formed and etching the semiconductor substrate in the opening to form a groove, and the depth of the groove and the film thickness of the etching stopper film. A fourth step of depositing an insulating film having a thickness equal to or more than the above value on the entire surface, and planarizing the semiconductor substrate on which the insulating film is deposited at least until the surface of the etching stopper film is exposed. A fifth step of forming a groove-type element isolation surrounding the element formation region in the groove, and removing at least the etching stopper film and the oxide film by etching, A sixth step of exposing a stepped portion between the region and the trench type element isolation where the side of the trench type element isolation is stepwise higher than the semiconductor substrate in the element forming region, and a gate oxide film on the substrate. And a seventh step of patterning at least the gate electrode from the conductive film after depositing the conductive film, and anisotropy etching after depositing an insulating film on the entire surface of the substrate to remove the gate electrode and the step portion. Eighth step of forming sidewalls made of the insulating film on each side surface, and ninth step of forming impurities by introducing impurities into the semiconductor substrate in the element forming regions on both sides of the gate electrode.
And a method for manufacturing a semiconductor device. 7. The method of manufacturing a semiconductor device according to claim 6, wherein in the second step, at least a predetermined value or more in the sixth step is taken into consideration in consideration of the over-etching amount in the eighth step. A method of manufacturing a semiconductor device, wherein a film thickness of an etching stopper film is determined so that a step having a difference is exposed. 8. A first step of forming an oxide film on a semiconductor substrate, a second step of depositing a first conductive film to be a gate electrode on the oxide film, and the first conductive film. A third step of forming an opening in a region where a groove type element isolation is to be formed and etching the semiconductor substrate in the opening to form a groove, and the depth of the groove and the film of the first conductive film. A fourth step of depositing an insulating film having a thickness equal to or larger than a value obtained by adding the thickness on the entire surface, and flattening the semiconductor substrate on which the insulating film is deposited until at least the surface of the first conductive film is exposed. And a fifth step of forming a groove-type element isolation surrounding the element formation region in the groove portion, and a second conductive film which becomes at least an upper gate electrode is deposited on the entire surface of the flattened substrate. 6 and the first and second conductive films A seventh step of patterning at least the gate electrode and exposing a stepped portion between the element formation region and the trench type element isolation, in which the element isolation side is stepwise higher than the semiconductor substrate in the element formation region. An eighth step of depositing an insulating film on the entire surface of the substrate, and then forming a sidewall made of the insulating film on each side surface of the gate electrode and the step portion by anisotropic etching; A source / drain region is formed by introducing impurities into the semiconductor substrate in the element formation region on both sides of the electrode.
And a method for manufacturing a semiconductor device. 9. The method for manufacturing a semiconductor device according to claim 8, wherein in the second step, at least a predetermined value or higher in the seventh step is taken into consideration in consideration of an overetching amount in the eighth step. A method of manufacturing a semiconductor device, characterized in that the film thickness of the first conductive film is determined so that a step having a difference is exposed. 10. The method of manufacturing a semiconductor device according to claim 6, further comprising a step of silicidizing at least a region near the surface of the source / drain region after the completion of the ninth step. A method of manufacturing a semiconductor device, comprising: 11. The method of manufacturing a semiconductor device according to claim 6, further comprising a step of depositing a protective oxide film on the entire surface of the substrate after the seventh step and before the eighth step. In the eighth step, a sidewall forming silicon nitride film and a masking film are sequentially deposited on the protective oxide film, and the masking film is etched back to form the gate electrode and the step portion side. A mask for patterning the silicon nitride film is left on one side, and the L-shaped silicon nitride film to be a sidewall is patterned from the silicon nitride film to the side of the gate electrode and the step portion using the mask, A method for manufacturing a semiconductor device, which is performed so as to remove the mask. 12. The method for manufacturing a semiconductor device according to claim 6, wherein in the seventh step, a first protective insulating film is further deposited on the conductive film, and the first protective insulating film is deposited. The method further comprises the step of patterning the film together with a gate electrode and depositing a second protective insulating film on the entire surface of the substrate after the seventh step and before the eighth step. A sidewall forming silicon film is deposited on the second protective insulating film, and an electrode part sidewall and a step part sidewall made of the above are formed on the side surfaces of the gate electrode and the step part. The method for manufacturing a semiconductor device, further comprising a step of silicidizing a region extending over the electrode side wall, the source / drain region, and the stepped side wall after the step of.