JP2000091417A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, in which element isolation is made by shallow trench isolation(STI) and the resistance of which is reduced by solving the problem of junction leakage caused by recesses in the edge sections of trenches and another problem of the condensation of silicide, and to provide a method of manufacturing of the device. SOLUTION: A semiconductor device has a plurality of element-forming regions, which are isolated from each other with element-forming regions 17. The element isolation regions 17 are formed as trenches filled up with insulating films 19, and an impurity having the same conductivity as that of the charge carrier of semiconductor elements formed in the element-forming regions is diffused in the upper end sections 23 of the interfaces between the element forming regions and trenches.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a method of forming a salicide in which the problem of junction leakage due to a dent at the edge of an STI is solved and which is hardly aggregated and thinned. The present invention relates to a semiconductor device in which the resistance is reduced, miniaturization and speeding up are realized, and a method of manufacturing the same.

[0002]

2. Description of the Related Art With the miniaturization of semiconductor elements, impurity diffusion layers formed in transistors tend to be increasingly shallow. Further, since the width of the gate wiring is reduced, it is necessary to form the diffusion layer shallowly in order to prevent the short channel effect and secure the breakdown voltage between the source and the drain. For example, for a gate wiring width of 0.25 μm, the depth of the diffusion layer needs to be 0.08 μm or less. As the diffusion layer becomes shallower, the sheet resistance of the source / drain increases. As a result, there is a problem that the response speed of the element is reduced. _Assuming that the gate delay time is τ _pd , the operating frequency f is proportional to 1 / τ _pd , so that improvement of the operating frequency cannot be expected. Such a structure is a microprocessor,
This is particularly disadvantageous for MPUs and the like that require high-speed operation.

[0003] Therefore, as a countermeasure against reduction in operation speed due to the above-mentioned increase in resistance, the source / selective low resistance silicide only on the drain, for example, TiSi ₂ and CoSi _2, etc. SALICIDE (self- extracting
Aligned silicide technology is attracting attention. FIG. 3 shows an example of a conventional MOS LSI manufacturing process.
4 will be described below.

First, as shown in FIG. 34A, an element isolation layer (LOCOS) 2 is formed by thermally oxidizing a silicon substrate 1 using a silicon nitride film (not shown) as a mask. A gate electrode 4 made of, for example, polysilicon is formed on a device forming region (active region) separated from each other by the LOCOS 2 via a gate insulating film 3. Further, an impurity having a lower concentration than the source / drain region 5 is diffused, and the LDD region (lightly-d
(Operated drain) 6 is formed. After a sidewall 7 made of an insulator is formed on the gate electrode, impurities are diffused using the sidewall 7 as a mask,
The drain region 5 is formed.

Next, as shown in FIG. 34B, a natural oxide film on the source / drain regions 5 is completely removed by performing a hydrofluoric acid treatment. Thereafter, a Ti layer (not shown) is formed on the entire surface by, for example, sputtering. A heat treatment is performed to silicify Ti, and a low-resistance titanium silicide layer (TiSi ₂ layer) 8 is selectively formed on source / drain region 5 and gate electrode 4. Further, only the unreacted Ti on the insulating film is selectively removed by dipping in ammonia / hydrogen peroxide solution or the like.

As shown in FIG. 34C, an interlayer insulating film 9 is deposited on the upper layer of the MOS transistor.
Then, a contact hole 10 is formed. For example, a tungsten plug 12 is buried in the contact hole 10 via a barrier metal layer 11, and an upper layer such as Al
By forming a metal wiring layer 13 made of an Al-based alloy such as -Si and patterning the metal wiring layer 13,
A wiring region is formed. According to the above process example, since the low-resistance silicide layer 8 is formed on the source / drain region 5 and the gate electrode 4, the source / drain region 5
In addition, the resistance of the gate electrode 4 can be reduced by about one digit as compared with a conventional semiconductor device.

[0007]

However, when the diffusion layer region is miniaturized with miniaturization of the element, it is necessary to form a high melting point metal silicide layer on the narrow source / drain region. . It has been reported that TiSi ₂ aggregates when TiSi ₂ is formed in a narrow portion, and as a result, reduction in resistance of source / drain regions cannot be expected. Also, with the shallower diffusion layer, SALICID
It is also necessary to reduce the thickness of the silicide layer formed by E. However, even when the silicide layer is thinned, aggregation of the silicide easily occurs, which hinders reduction of the sheet resistance. From the above, there is a demand for the development of a SALICIDE technique that hardly causes aggregation even in a narrow portion and can form a thin silicide layer.

On the other hand, the conventional element isolation method using LOCOS as shown in FIG. 34 has a problem that when the element is miniaturized, the area occupied by the element isolation layer (LOCOS) increases due to bird's beak. Therefore, in recent years, an element isolation method using shallow trench isolation (STI) has attracted attention. FIGS. 35 to 37 show an example of a process of forming an STI to perform element isolation and forming a MOS transistor on an active region separated from each other by the STI.

First, as shown in FIG. 35A, a thermal oxide film having a thickness of about 10 nm is formed as a pad oxide film (sacrifice film) 14 on the silicon substrate 1. A silicon nitride film (SiN film) 15 having a thickness of about 150 nm is formed as an upper layer by, for example, a low pressure CVD method.

Next, as shown in FIG. 35B, a resist 16 is deposited on the entire surface, and then the resist 16 is patterned. Using the resist 16 as a mask, the silicon substrate 1 is etched to form a trench 17. Subsequently, as shown in FIG. 36A, after a thin thermal oxide film 18 having a thickness of about 10 nm is formed on the inner wall of the trench 17,
An oxide film 19 having a thickness of about 600 nm is deposited so as to fill the trench 17. The buried oxide film 19 is formed of a high-density plasma (HDP) such as an ECR (Electron Cyclotron) plasma device.
It is formed using a device capable of generating sma).

Since the oxide film 19 is relatively thickly deposited on the upper portion of the wide active region 20, before the planarization by CMP (chemical mechanical polishing), as shown in FIG. Only the oxide film 19 on the active region 20 is removed by etching. As shown in FIG.
The oxide film 19 is left only in the trench 17 by performing CMP. As shown in FIG. 37B, the SiN film 15 is removed by hot phosphoric acid, and then the pad oxide film 14 is removed by light etching using hydrofluoric acid.

Subsequently, an oxide film (not shown) is formed on the surface of the silicon substrate 1 by thermal oxidation, ions are implanted for forming a p-well or an n-well, and the oxide film is removed by etching. As shown in (C), a dent (dip) 21 occurs at the edge of the trench 17.

If a transistor is formed in the active region and a salicide is formed on the source / drain region in a state where the edge of the trench is depressed, the salicide grows excessively at the edge of the trench and causes a junction leak. In addition, since film stress and crystal defects are likely to be concentrated at the edge of the trench, junction leakage also increases due to these factors. Such a junction leak causes a problem that, for example, in the case of a DRAM, the storage retention characteristics are deteriorated.

The present invention has been made in view of the above problems, and therefore, the present invention eliminates the problem of junction leakage caused by a depression at the edge of a trench in a semiconductor device in which elements are separated by STI. It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same. Further, the present invention provides a semiconductor device which has a high speed and is miniaturized by forming a thinned salicide to reduce the resistance by hardly causing agglomeration of silicide even on a narrow active region, and a method of manufacturing the same. The purpose is to provide.

[0015]

In order to achieve the above object, a semiconductor device according to the present invention comprises a semiconductor substrate having a plurality of element formation regions separated from each other by element isolation regions on a semiconductor substrate. The element isolation region is an element isolation groove (trench) formed on the surface of the semiconductor substrate and having an insulating film embedded therein. The element isolation region is formed at an upper end of an interface between the element formation region and the trench. A first conductivity type impurity having the same conductivity type as that of the charge carrier of the formed semiconductor element is diffused. In the semiconductor device of the present invention, preferably, a second conductivity type impurity having a conductivity type opposite to that of the charge carrier of the semiconductor element is diffused in a portion of the semiconductor substrate which is in contact with the trench bottom and the side wall. It is characterized by. The semiconductor device of the present invention is preferably configured such that at least one of the semiconductor elements is provided.
One is an n-channel field-effect transistor, and at least one of the semiconductor elements is a p-channel field-effect transistor.

Thus, the impurity having the same conductivity type as the source / drain region is diffused in the vicinity of the dent formed at the edge of the trench, and the junction leak caused by the dent is suppressed. In addition, when impurities having a conductivity type opposite to that of the source / drain region are diffused into the bottom and side walls of the trench, more sufficient element isolation is performed, so that a junction leak at the edge of the trench can be further suppressed. it can.

Further, according to the semiconductor device of the present invention, in a semiconductor device having a plurality of element formation regions separated from each other by an element isolation region on a semiconductor substrate, the element isolation region is formed on a surface of the semiconductor substrate. A first conductivity type impurity, wherein the first conductivity type impurity is a trench in which an insulating film is buried, and a conductivity type is the same as that of a charge carrier of a semiconductor element formed in the element formation region at an interface between the element formation region and the trench side wall. Are diffused. In the semiconductor device of the present invention, preferably, a second conductivity type impurity having a conductivity type opposite to that of the charge carrier of the semiconductor element is diffused in a portion of the semiconductor substrate which is in contact with the trench bottom and the side wall. It is characterized by.

As a result, impurities having the same conductivity type as the source / drain regions are deeply diffused into the side wall of the trench,
Junction leakage due to the depression in the trench or the edge of the trench is suppressed. In addition, when impurities having a conductivity type opposite to that of the source / drain region are diffused into the bottom and side walls of the trench, more sufficient element isolation is performed, so that a junction leak at the edge of the trench can be further suppressed. it can.

According to a semiconductor device of the present invention, there is provided a semiconductor device having a plurality of element formation regions separated from each other by an element isolation region on a semiconductor substrate, wherein the element isolation region is embedded with an insulating film formed on a surface of the semiconductor substrate. Wherein the surfaces of the element formation region and the element isolation region are planarized to a uniform height.

Further, in the semiconductor device according to the present invention, in a semiconductor device having a plurality of element formation regions separated from each other by an element isolation region on a semiconductor substrate, the element isolation region is formed on a surface of the semiconductor substrate. A trench in which an insulating film is buried, wherein an upper end portion of an interface between the element formation region and the trench and a surface of the element formation region are flattened to a uniform height.

As a result, no dent is formed at the edge of the trench, and the film stress at the edge is reduced, so that the junction leakage is suppressed. Therefore, a semiconductor device with high frequency and low power consumption is realized.

Further, in order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises a step of forming a sacrificial film on a semiconductor substrate, a step of forming a protective layer on the sacrificial film, Forming a device isolation groove (trench) in the substrate for isolating the plurality of device formation regions from each other; and forming an insulating film in the trench so that a part thereof protrudes from the surface of the semiconductor substrate. A method of manufacturing a semiconductor device, comprising: embedding, performing chemical mechanical polishing on the insulating film to form an element isolation region, and forming a semiconductor element in the element formation region. Diffusing a first conductivity type impurity having the same conductivity type as that of the charge carrier of the semiconductor element into the trench forming region and a peripheral portion thereof after forming the trench; That step, the trench edges,
Forming the trench while leaving the first conductivity type impurity diffusion layer at a predetermined interval.

In the method of manufacturing a semiconductor device according to the present invention, preferably, the step of diffusing the first conductivity type impurity is a step of performing oblique ion implantation using a resist having a pattern of the element formation region as a mask. It is characterized by the following. In the method of manufacturing a semiconductor device according to the present invention, preferably, after the formation of the trench, a charge carrier of the semiconductor element and a conductivity type of the semiconductor element are opposite to a portion of the semiconductor substrate that is in contact with the bottom and the side wall of the trench. And a step of diffusing the second conductivity type impurity.

According to the method of manufacturing a semiconductor device of the present invention, a step of forming a sacrificial film on a semiconductor substrate, a step of forming a protective layer on the sacrificial film, and forming a plurality of the element formation regions on the semiconductor substrate Forming an element isolation trench (trench) for isolating each other, and forming an insulating film in the trench;
A step of embedding a part of the semiconductor substrate so as to protrude, a step of performing chemical mechanical polishing on the insulating film to form an element isolation region, and a step of forming a semiconductor element in the element formation region. In a method of manufacturing a semiconductor device having at least a first conductivity type impurity, the conductivity type is the same as that of a charge carrier of the semiconductor element at an interface between the trench side wall and the element formation region after forming the element isolation region. Characterized by having a step of diffusing In the method for manufacturing a semiconductor device according to the present invention, preferably, after the formation of the trench, a portion of the semiconductor substrate in contact with the trench bottom portion and the sidewall portion has a conductivity type opposite to that of a charge carrier of the semiconductor element. A step of diffusing the two-conductivity-type impurity.

According to a method of manufacturing a semiconductor device of the present invention, a step of forming a sacrificial film on a semiconductor substrate, a step of forming a protective layer on the sacrificial film, and forming a plurality of the element formation regions on the semiconductor substrate Forming an element isolation trench (trench) for isolating each other, and forming an insulating film in the trench;
A step of embedding a part of the semiconductor substrate so as to protrude, a step of performing chemical mechanical polishing on the insulating film to form an element isolation region, and a step of forming a semiconductor element in the element formation region. In a method of manufacturing a semiconductor device having at least a step of removing the protective layer after performing chemical mechanical polishing on the insulating film, and applying silicon oxide dispersed in an organic solvent on the entire surface (spin on·
Glass; SOG); forming an oxide film; and performing a second chemical mechanical polishing to flatten the surface of the element formation region and the element isolation region to a uniform height. It is characterized by.

According to a method of manufacturing a semiconductor device of the present invention, a step of forming a sacrificial film on a semiconductor substrate, a step of forming a protective layer on the sacrificial film, and forming a plurality of the element formation regions on the semiconductor substrate Forming an element isolation trench (trench) for isolating each other, and forming an insulating film in the trench;
A step of embedding a part of the semiconductor substrate so as to protrude, a step of performing chemical mechanical polishing on the insulating film to form an element isolation region, and a step of forming a semiconductor element in the element formation region. In a method of manufacturing a semiconductor device having at least a step of performing chemical mechanical polishing on the insulating film, removing the protective layer and exposing the semiconductor substrate in the element formation region, and exposing the semiconductor substrate in the element formation region. Etching the semiconductor substrate, and flattening the upper surface of the interface between the element forming region and the trench, and the surface of the element forming region to a uniform height. Forming the semiconductor element in the element formation region, which is flattened to a uniform height with an upper end portion of the interface between the element formation region and the trench. Characterized in that it is a degree.

According to the method of manufacturing a semiconductor device of the present invention, there are provided a step of forming a sacrificial film on a semiconductor substrate, a step of forming a protective layer on the sacrificial film, and forming a plurality of the element formation regions on the semiconductor substrate. Forming an element isolation groove (trench) for isolation from each other, embedding an insulating film in the trench so that a part thereof protrudes from the surface of the semiconductor substrate, and forming a chemical mechanical device in the insulating film. Polishing, a method of manufacturing a semiconductor device having at least a step of forming an element isolation region and a step of forming a semiconductor element in the element formation region, wherein after forming the semiconductor element, etching is performed on the surface of the semiconductor element. A step of flattening an upper end portion of an interface between the element formation region and the trench and a surface of the element formation region to a uniform height.

According to the method of manufacturing a semiconductor device of the present invention, it is possible to manufacture a semiconductor device in which a junction leak caused by a depression at an edge of a trench is suppressed. Further, according to the method of manufacturing a semiconductor device of the present invention, a transistor can be formed in an element formation region without causing a depression at an edge portion of a trench. This can prevent excessive growth of salicide at the edge of the trench, and can sufficiently suppress junction leakage.

[0029]

Embodiments of a semiconductor device and a method of manufacturing the same according to the present invention will be described below with reference to the drawings. (Embodiment 1) FIG. 1 is a sectional view of a semiconductor device of the present embodiment. In the semiconductor device of FIG.
, An MOS transistor having the source / drain region 5 and the gate electrode 4 is formed.

In the semiconductor device of this embodiment, the S in the n-channel transistor forming region (n region) 22
An n ⁺ -type impurity is ion-implanted into the shallow region 23 of TI,
Further, the low concentration p
Type impurities are ion-implanted. On the other hand, ap ⁺ -type impurity is ion-implanted into a shallow STI region 26 in a p-channel transistor formation region (p region) 25, and a low-concentration n-type impurity is ion-implanted into a deep STI region 27 in the p region. ing. As a result, a thin gate structure having low resistance and suppressing junction leakage is obtained.

Next, a method of manufacturing the semiconductor device of the present embodiment will be described. First, as shown in FIG. 2A, a silicon oxide film having a thickness of 1
A 0 nm thermal oxide film is formed. An SiN film 15 having a thickness of 150 nm is formed thereon by, for example, a low pressure CVD method. Subsequently, as shown in FIG. 2B, a resist 28 is deposited on the entire surface, and then the resist 28 is patterned so as to serve as a mask for forming a trench in the n region.

Next, as shown in FIG. 3A, an n ⁺ impurity ion is implanted into the opening of the resist 28 to form an n ⁺ impurity diffusion region 23. Ion implantation, for example,
As with ion energy of 100 keV, introduced amount of 5 × 10
Rotational ion implantation inclined at 45 ° is performed under the condition of ¹⁵ atoms / cm ² . By oblique ion implantation, ions are also implanted into the lower part of the resist near the opening of the resist.

As shown in FIG. 3B, the silicon substrate 1 is etched using the resist 28 as a mask to form a trench 17 in the n region 22. As a result, the active region near the edge of the trench 17 has n ⁺
An impurity diffusion region 23 is formed. Further, FIG.
As shown in the figure, on the inner wall of the trench formed in the n region,
As a p-type impurity, for example, boron is ion energy 2
Ion implantation is performed under the conditions of 0 keV and a dose of 5 × 10 ¹² atoms / cm ² to form an impurity diffusion layer 24. After that, the resist 28 is removed.

Next, as shown in FIG. 4B, a resist 29 is deposited on the entire surface, and then the resist 29 is patterned so as to serve as a mask for forming a trench in the p region 25. Subsequently, p is applied to the opening of the resist 29.
⁺ Impurity ions are implanted into the p ⁺ impurity diffusion region 26.
To form For example, boron (B) is ion-implanted at an ion energy of 40 keV and a dose of 3 × 10 ¹⁵ atoms.
It is performed by rotating ion implantation inclined at 45 ° under the condition of s / cm ² . By oblique ion implantation, ions are also implanted below the resist 29 near the opening of the resist.

Next, as shown in FIG. 5A, the silicon substrate 1 is etched using the resist 29 as a mask to form a trench 17 in the p region 25. Thus, ap ⁺ impurity diffusion region 26 is formed in the active region near the edge of trench 17. further,
As shown in FIG. 5B, on the inner wall of the trench formed in the p region, for example, phosphorus as an n-type impurity is ion energy of 20 keV and the introduced amount is 5 × 10 ¹² atoms / cm.
Ion implantation is performed under the condition ² to form the impurity diffusion layer 27.

As shown in FIG. 6A, an oxide film (HDP film) 19 is deposited to a thickness of 600 nm so as to fill the trench by using, for example, an ECR plasma CVD apparatus. Here, since the oxide film 19 is thickly deposited on the wide active region 20, the oxide film 19 on the wide active region 20 is removed by etching using the resist 30 as a mask, as shown in FIG. I do.

Subsequently, as shown in FIG.
Polishing is performed on the entire surface under the following conditions, for example, to flatten the surface. Abrasive (slurry): Hydrogen peroxide + silica Slurry flow rate: 20 sccm, polishing head pressure: 4.0 psi Wafer rotation speed: 20 rpm, head rotation speed: 20 rpm

Next, as shown in FIG. 7B, the SiN film 15 is removed by etching using, for example, hot phosphoric acid (70 ° C.). Further, as shown in FIG. 7C, the pad oxide film 14 is removed by, for example, light etching using hydrofluoric acid. After that, an oxide film (not shown) is formed on the surface of the silicon substrate 1 and ion implantation for forming a p-well or an n-well (not shown) is performed.
The oxide film is removed.

Next, as shown in FIG. 8A, a gate oxide film 3 is formed by thermal oxidation, and a polysilicon layer 31 for forming a gate electrode is formed on the gate oxide film 3 with a thickness of, for example, 20 nm.
Deposit at 0 nm. The formation of the polysilicon layer 31 is performed, for example, under the following conditions. Film forming gas: SiH ₄ / He / N ₂ = 100/400/2
00 sccm pressure: 70 Pa, substrate temperature: 610 ° C. Here, in order to prevent oxidation of the polysilicon layer 31, a SiN or SiO ₂ layer having a thickness of 1
You may laminate | stack about 00 nm.

Further, the polysilicon layer 31 (or
After depositing a resist 32 on the upper layer of the polysilicon layer (SiN or SiO ₂ layer), the resist 32 is subjected to predetermined patterning, and the polysilicon layer 31 is etched using the resist 32 as a mask. Thus, the gate electrode 4 is formed as shown in FIG. The etching of the polysilicon layer 31 is performed, for example, under the following conditions. Etching _{gas: Cl 2 / O 2 / HBr} = 75/2/1
20 sccm pressure: 1 Pa, RF power: 60 W, microwave output: 850 W (However, SiN or SiO ₂
In the case where a layer is formed, before etching the polysilicon layer, an etching gas: C ₄ F ₈ = 50 s is set in advance.
Etching is performed under the conditions of ccm, pressure: 2 Pa, and RF power: 1200 W. )

Next, as shown in FIG. 8B, ion implantation is performed using the gate electrode 4 as a mask, and L is implanted in a self-aligned manner.
The DD region 6 is formed. In the n region 22, for example, arsenic is ion energy of 30 keV, and the introduced amount is 1 × 10 ¹³ atom.
Ions are implanted under the condition of ms / cm ² . Also, the p region 2
5 is, for example, boron ion energy of 30 keV,
Ion implantation is performed under the conditions of an introduction amount of 1 × 10 ¹³ atoms / cm ² . Thereby, the LDD region 6 is formed.

Next, as shown in FIG. 8C, in order to provide the sidewalls 7 on the gate electrode 4,
Oxide film of about 0 nm (or single-layer SiN film, Si
It may be an N / SiO ₂ multilayer film. Is deposited, for example, under the following conditions. Film forming gas: TEOS (tetraethoxysilane) = 50s
ccm temperature: 720 ° C, pressure: 40Pa

Thereafter, the entire surface is etched back under the following conditions, for example. Etching gas: C ₄ F ₈ = 50 sccm, pressure: 2
Pa RF power: 1200 W As a result, the insulator sidewall 7 is formed on the gate electrode 4.

Next, as shown in FIG. 9A, ion implantation is performed using the side walls 7 as a mask to form source / drain regions 5. In the n region 22, for example, arsenic is ion energy of 60 keV and the introduced amount is 3 × 10 ¹⁵ at.
Ions are implanted under the condition of oms / cm ² . In the p region 25, for example, BF ₂ is ion energy of 40 ke.
V ions are implanted under the conditions of an introduction amount of 3 × 10 ¹⁵ atoms / cm ² . Thereafter, a short-time heat treatment at about 1000 ° C. is performed to diffuse the ion-implanted impurities into the source / drain regions 5, thereby forming a MOS transistor. Then, apply SALIDE technology,
The resistance of the source / drain region 5 or the gate electrode 4 is reduced.

First, as shown in FIG. 9B, the oxide film on the surface of the silicon substrate 1 is removed by light etching using diluted hydrofluoric acid to expose the Si surface. Thereafter, for example, by sputtering, the refractory metal layer 33 is formed on the entire surface,
For example, a Co single layer, or a Ti / Co laminated film or Ti
An N / Co laminated film is formed. The formation of the refractory metal layer 33 is performed, for example, under the following conditions.

Co single layer; power: 1 kW, gas: Ar = 100 sccm, pressure: 0.47 Pa, film thickness: 20 nm Ti / Co laminated film; (Co layer) power: 1 kW, gas: Ar = 100 sccm, pressure: 0.47 Pa , Thickness: 10 nm (Ti layer) power: 0.5 kW, gas: Ar = 100 sccm pressure: 0.47 Pa, film thickness: 6 nm TiN / Co laminated film; (Co layer) power: 1 kW, gas: Ar = 100 sccm pressure : 0.47 Pa, film thickness: 10 nm (TiN layer) power: 1 kW, gas: Ar = 100 sccm pressure: 0.47 Pa, film thickness: 20 nm

After the refractory metal layer 33 as described above is formed on the entire surface, the first short-time heat treatment (1st RTA; r
Rapid thermal annealing is performed, for example, under the following conditions to silicide the Co layer, and C
o ₂ Si is formed. Gas: N ₂ = 5 L / min, Temperature: 550 ° C., Time: 30 seconds

As shown in FIG. 10A, by immersing in a sulfuric acid / hydrogen peroxide solution, an unreacted unreacted high melting point metal layer 33 of Ti or TiN is removed. Thus, only the silicided portion 34 of the refractory metal layer remains. Subsequently, a heat treatment at 700 ° C. (2
nd RTA), for example, under the following conditions to obtain Co ₂ Si
To CoSi ₂ to form a stable (final phase) silicide. Gas: N ₂ = 5 L / min, Temperature: 700 ° C., Time: 30 seconds

Next, as shown in FIG. 10B, an interlayer insulating film 9 is formed with a thickness of 200 nm on the entire surface. The formation of the interlayer insulating film 9 can be performed under the following conditions, for example, as in the step shown in FIG. Film forming gas: TEOS (tetraethoxysilane) = 50s
ccm Temperature: 720 ° C., Pressure: 40 Pa Further, an SiN film 35 is formed on the interlayer insulating film 9 to a thickness of about 50 nm, for example, under the following conditions. Film forming gas: SiH ₂ Cl ₂ / NH ₃ / N ₂ = 0.05 /
0.2 / 0.2sccm temperature: 760 ° C, pressure: 70Pa

After forming the SiN film 35, dry etching is selectively performed on the SiN film 35 and the interlayer insulating film 9 in the contact hole portion 10 under the following conditions, for example. Etching gas: C ₄ F ₈ = 50 sccm, pressure: 2
Pa RF power: 1200W

Next, as shown in FIG. 1, a second interlayer insulating film 9 ′ is formed on the SiN film 35 to a thickness of, for example, 400 nm.
Formed. The formation of the second interlayer insulating film 9 ′ can be performed under the same conditions as those for the above-described interlayer insulating film 9. A resist (not shown) is deposited on the second interlayer insulating film 9 ′,
Dry etching using a resist as a mask, for example, RI
E (reactive ion etching) is performed to form a contact hole. The etching can be performed under the same conditions as the above-described etching for forming an opening in the interlayer insulating film 9.

Subsequently, a wiring material is buried in the contact hole to form a wiring. First, the barrier metal layer 11
A Ti layer is formed with a thickness of 30 nm, for example, by sputtering, and a TiN layer is stacked thereon with a thickness of 70 nm. Cu layer is 10 nm thick by sputtering
After being formed to a small thickness, the Cu layer 36 is further formed to a thickness of about 600 nm by electroplating. These films can be formed, for example, under the following conditions.

(Ti layer) Ti target used, gas: Ar = 40 sccm, pressure: 0.67 Pa, temperature: 150 ° C. (TiN layer) Ti target used gas: Ar / N ₂ = 30/100 sccm Pressure: 0.67 Pa, Temperature: 150 ° C. (Cu sputtering layer) Cu target used Gas: Ar = 40 sccm Pressure: 0.67 Pa, Temperature: 300 ° C. (Cu electroplating layer) Chemical solution: CuSO ₄ + 5H ₂ O Temperature: 30 ° C., Voltage: 10 V, current ： 30mA / dm ²

Thereafter, the Cu layer 36, the TiN layer, and the Ti layer 11 are subjected to CMP to flatten the surfaces. This CMP can be performed, for example, under the following conditions. Abrasive (slurry): aqueous hydrogen peroxide + Fe (NO ₃ ) Slurry flow rate: 20 sccm, polishing head pressure: 4.0 psi, wafer rotation speed: 20 rpm, head rotation speed: 20 rpm

Further, on the Cu layer, a capping TiN layer 35 'is formed as an antioxidant film under the following conditions, for example. Using a Ti target, gas: Ar / N ₂ = 30/100 sccm, pressure: 0.67 Pa, temperature: 150 ° C.

Alternatively, instead of the capping TiN layer 35 ', a capping SiN film may be formed as an antioxidant film, for example, with a thickness of about 30 nm under the following conditions. Film forming gas: SiH ₄ / NH ₄ / N ₂ = 265/100 /
4000 sccm temperature: 400 ° C, pressure: 565 Pa

Through the above steps, the semiconductor device shown in FIG. 1 is formed. According to the method of manufacturing the semiconductor device of the present embodiment, the impurity diffusion region is formed in the active region near the edge of the trench, and the conductivity type is opposite to that of the source / drain region at the bottom and the side wall of the trench. Since the impurities are diffused, junction leakage is suppressed.

(Embodiment 2) FIG. 11 is a sectional view of a semiconductor device of this embodiment. In the semiconductor device of the present embodiment, an n-channel transistor formation region (n region)
An n ⁺ -type impurity diffusion region 23 is formed in the shallow STI region 22. On the other hand, in a shallow STI region in the p-channel transistor formation region (p region) 25,
A p ⁺ -type impurity diffusion region 26 is formed. As a result, a thin gate structure having low resistance and suppressing junction leakage is obtained.

Next, a method of manufacturing the semiconductor device of the present embodiment will be described. The method of manufacturing a semiconductor device according to the present embodiment is the same as that of the first embodiment up to the step of forming a trench in a silicon substrate (FIGS. 2A to 3B).
As shown in FIG. 2A, a film having a thickness of 10
A pad oxide film (thermal oxide film) having a thickness of nm is formed. An SiN film 15 having a film thickness of 15
Formed at 0 nm. Subsequently, as shown in FIG.
a mask for forming a trench in the n region 22;
A resist 28 is formed.

Next, as shown in FIG. 3A, as an n ⁺ impurity in the opening of the resist 28, for example, As is ion energy of 100 keV, and the introduced amount is 5 × 10 ¹⁵ atoms.
The ion implantation is performed by rotating ion implantation inclined at 45 ° under the condition of / cm ² . By oblique ion implantation, ions are also implanted into the lower portion of the resist near the opening of the resist. Further, as shown in FIG. 3B, when the silicon substrate 1 is etched using the resist 28 as a mask, the n region 2
2, a trench 17 is formed, and an n ⁺ impurity diffusion region 23 is formed in an active region near an edge of the trench.

As shown in FIG. 12A, a resist 29 is deposited on the entire surface, and the resist 29 is patterned so as to serve as a mask for forming a trench in the p region. Subsequently, for example, boron (B) is ion-implanted into the opening of the resist as ap ⁺ impurity by rotating ion implantation inclined at 45 ° under the conditions of an ion energy of 40 keV and an introduction amount of 3 × 10 ¹⁵ atoms / cm ^2. . By oblique ion implantation, ions are also implanted into the lower part of the resist near the opening of the resist.

Next, as shown in FIG. 12B, the silicon substrate 1 is etched using the resist 29 as a mask to form a trench 17 in the p region 25. A p ⁺ impurity diffusion region 26 is formed in the active region near the edge of the trench.

As shown in FIG. 13A, for example, ECR
Using a plasma CVD apparatus, an oxide film (HDP film) 19 is deposited to a thickness of 600 nm so as to fill the trench.
Here, since the oxide film 19 is deposited thickly on the wide active region 20, the oxide film 19 on the wide active region 20 is removed by etching using the resist 30 as a mask, as shown in FIG. I do.

Subsequently, as shown in FIG.
Polishing is performed on the entire surface to flatten the surface. CM
P is performed under the following conditions, for example. Abrasive (slurry): Hydrogen peroxide + silica Slurry flow rate: 20 sccm, polishing head pressure: 4.0 psi Wafer rotation speed: 20 rpm, head rotation speed: 20 rpm

Next, as shown in FIG.
The film 15 is removed by, for example, etching using hot phosphoric acid (70 ° C.). Further, as shown in FIG. 14C, the pad oxide film 14 is removed by light etching using, for example, hydrofluoric acid. Thereafter, an oxide film (not shown) is formed on the surface of the silicon substrate, and ion implantation for forming a p-well or an n-well (not shown) is performed.
The oxide film is removed.

The following steps are for forming MOS transistors on the semiconductor substrate obtained in the above steps, and are common to the first embodiment. Therefore, the cross-sectional views showing the manufacturing steps are omitted, and the final steps are obtained. FIG. 11 is a cross-sectional view of the semiconductor device. According to the method of manufacturing a semiconductor device of the present embodiment, the impurity diffusion regions 23 and 26 are formed in portions (shallow regions) close to the trench edges of the active region. Is suppressed.

(Embodiment 3) FIG. 15 is a sectional view of a semiconductor device of this embodiment. In the semiconductor device of the present embodiment, impurities are ion-implanted into the side wall portion 37 of the STI. As a result, a thin-line gate structure with low resistance and suppressed junction leakage is obtained. FIG. 15 is a cross-sectional view in which an STI is formed in an n-channel transistor formation region. This embodiment is similar to the first and second embodiments.
The present invention can be applied to a semiconductor substrate in which an n-channel transistor formation region and a p-channel transistor formation region are mixed. The semiconductor device according to the present embodiment cannot be applied to a case where gate wirings are formed to intersect on an element isolation region (STI) from the viewpoint of preventing short circuit, but is applicable to a transistor in other cases. Is possible.

Next, a method of manufacturing the semiconductor device of the present embodiment will be described. First, as shown in FIG. 16A, a 10-nm-thick thermal oxide film is formed as a pad oxide film 14 on the silicon substrate 1 and, for example,
The SiN film 15 is formed with a thickness of 150 nm by the VD method. Subsequently, as shown in FIG. 16B, a resist 28 is deposited on the entire surface, and the resist 28 is patterned so as to be used as a mask for forming a trench. Next, FIG.
As shown in FIG. 2C, the silicon substrate 1 is etched using the resist 28 as a mask to form the trench 17.

As shown in FIG. 17A, for example, ECR
Using a plasma CVD apparatus, an oxide film (HDP film) 19 is deposited to a thickness of 600 nm so as to fill the trench.
Here, since the oxide film 19 is thickly deposited on the wide active region 20, as shown in FIG. 17B, the oxide film 19 on the wide active region 20 is removed by etching using the resist 30 as a mask. .

Subsequently, as shown in FIG.
Polishing with P is performed on the entire surface under the following conditions, for example, to flatten the surface. Abrasive (slurry): Hydrogen peroxide + silica Slurry flow rate: 20 sccm, polishing head pressure: 4.0 psi Wafer rotation speed: 20 rpm, head rotation speed: 20 rpm

Next, as shown in FIG.
The film 15 is removed by, for example, etching using hot phosphoric acid (70 ° C.). Further, as shown in FIG. 18C, the pad oxide film 14 is removed by, for example, light etching using hydrofluoric acid. Thereafter, as shown in FIG. 19A, an oxide film 38 is formed on the surface of the silicon
After ion implantation for forming a well or an n-well (not shown), the oxide film 38 is removed as shown in FIG. In this step, a depression 21 occurs at the edge of the trench.

Next, as shown in FIG.
Resist patterning is performed so that ions are implanted only in the peripheral portion of 17 (the interface between the STI side wall and the silicon substrate), and an impurity having the same conductivity type as the source / drain regions is ion-implanted using a resist (not shown) as a mask. I do. For example, in the n-channel MOS transistor formation region, arsenic is ion energy of 40 keV and the introduced amount is 5 ×.
Ion implantation is performed under the conditions of 10 ¹⁵ atoms / cm ² and n ⁺
An impurity diffusion region 37 is formed. In addition, p-channel type M
In the OS transistor formation region, for example, BF ₂ is ion energy of 20 keV and the introduced amount is 3 × 10 ¹⁵ atoms /
Ions are implanted under the condition of cm ² .

Through the above steps, a semiconductor substrate in which junction leakage due to the depression at the edge of the trench is prevented is formed. The subsequent process is a MOS transistor forming process, which is common to the first and second embodiments, and a cross-sectional view showing a manufacturing process is omitted as appropriate. First, a gate oxide film 3 is formed on the surface of a semiconductor substrate by thermal oxidation, and a polysilicon layer 31 for forming a gate electrode is deposited thereon to a thickness of, for example, about 200 nm under the following conditions (FIG. 8).
(A)). Film forming gas: SiH ₄ / He / N ₂ = 100/400/2
00 sccm pressure: 70 Pa, substrate temperature: 610 ° C. Here, in order to prevent oxidation of the polysilicon layer, an SiN or SiO ₂ layer having a thickness of 100 is formed on the polysilicon layer.
It may be laminated by about nm.

Further, the polysilicon layer 31 (or alternatively,
Forming a resist 32 having a gate electrode pattern on the upper layer of the polysilicon layer (SiN or SiO ₂ layer);
When the polysilicon layer 31 is etched using the resist 32 as a mask under the same conditions as in the first embodiment, the gate electrode 4 is formed (see FIG. 8B).

Next, ion implantation is performed using the gate electrode 4 as a mask to form the LDD region 6 in a self-aligned manner (see FIG. 8B). The ion implantation for forming the LDD region 6 can be performed under the same conditions as in the first embodiment. Next, in order to provide the sidewall 7 on the gate electrode, an oxide film (or a single-layer SiN
It may be a film or a SiN / SiO ₂ multilayer film. ) Is deposited. This oxide film is formed, for example, under the following conditions. Film forming gas: TEOS (tetraethoxysilane) = 50s
ccm temperature: 720 ° C, pressure: 40Pa

Thereafter, the entire surface is etched back under the following conditions, for example. Etching gas: C ₄ F ₈ = 50 sccm, pressure: 2
Pa RF power: 1200 W As a result, the sidewall 7 made of an insulator is formed on the gate electrode 4 (see FIG. 8C).

Next, as shown in FIG. 20A, ion implantation is performed using the side wall 7 as a mask,
The drain region 5 is formed. In the n-channel transistor formation region, for example, arsenic is ion energy 60 ke.
V ions are implanted under the conditions of an introduction amount of 3 × 10 ¹⁵ atoms / cm ² . In the p-channel transistor formation region, for example, BF ₂ is ion-implanted under the conditions of an ion energy of 40 keV and a dose of 3 × 10 ¹⁵ atoms / cm ² . After that, heat treatment is performed for about a short time at about 1000 ° C.
By diffusing the impurities implanted into the source / drain regions 5, a MOS transistor is formed.

Subsequently, the resistance of the source / drain region or the gate electrode is reduced by applying the SALICIDE technique. First, the oxide film on the surface of the silicon substrate is removed by light etching using diluted hydrofluoric acid to expose the Si surface (see FIG. 9B). Thereafter, the refractory metal layer 33, for example, a Co single layer, a Ti / Co laminated film, or a TiN / C
o A laminated film is formed. The formation of the refractory metal layer 33 can be performed under the same conditions as in the first embodiment. After the refractory metal layer 33 is formed on the entire surface, 1st RTA is performed, for example, under the following conditions to silicide the Co layer, and the Co ₂ Si
To form Gas: N ₂ = 5 L / min, Temperature: 550 ° C., Time: 30 seconds

Next, as shown in FIG.
Unreacted Ti or TiN is removed by immersion in a hydrogen peroxide solution. As a result, only the silicided portion of the refractory metal layer 33 remains. Then, 70
A heat treatment (2nd RTA) at 0 ° C. is performed, for example, under the following conditions to transfer Co ₂ Si to CoSi ₂ and form stable silicide. Gas: N ₂ = 5 L / min, Temperature: 700 ° C., Time: 30 seconds

Next, an interlayer insulating film 9 is formed on the entire surface, for example, with a thickness of about 200 nm under the same conditions as in the first embodiment (see FIG. 10B). Further, Si is formed on the interlayer insulating film 9 as an upper layer.
The N film 35 is formed to a thickness of 50 under the same conditions as in the first embodiment, for example.
It is formed on the order of nm. After forming the SiN film 35, the first embodiment
Dry etching is performed under the same conditions as described above to form a contact hole.

As shown in FIG. 15, a second interlayer insulating film having a thickness of, for example, 400 nm is formed on the SiN film.
The formation of the second interlayer insulating film can be performed under the same conditions as the above-described interlayer insulating film. A resist (not shown) is deposited on the second interlayer insulating film, and dry etching, for example, RIE is performed using the resist as a mask to form a contact hole. The etching can be performed under the same conditions as the above-described etching for forming an opening in the interlayer insulating film.

Subsequently, a wiring material is buried in the contact hole to form a wiring. First, a 30-nm-thick Ti layer is formed as a barrier metal layer by, for example, sputtering, and a 70-nm-thick TiN layer is stacked thereover. After a Cu layer is formed to be thin to a thickness of about 10 nm by sputtering, a Cu layer is further formed to a thickness of about 600 nm by electroplating. Each of these films can be formed under the same conditions as in the first embodiment.

Thereafter, the above-mentioned Cu layer, TiN layer and T
CMP is performed on the i-layer under the same conditions as in the first embodiment to planarize the surface. This CMP can be performed, for example, under the following conditions. Further, a capping TiN layer is formed on the Cu layer as an antioxidant film. Capping T
The iN layer can be formed, for example, under the following conditions. Using Ti target, gas: Ar / N ₂ = 30/10
0 sccm pressure: 0.67 Pa, temperature: 150 ° C

Alternatively, instead of the capping TiN layer, a capping SiN film having a thickness of 3
It may be formed with a thickness of about 0 nm. When a capping SiN film is formed, for example, it can be performed under the following conditions. Film forming gas: SiH ₄ / NH ₄ / N ₂ = 265/100 /
4000 sccm temperature: 400 ° C, pressure: 565 Pa

Through the above steps, the semiconductor device shown in FIG. 15 is formed. According to the method of manufacturing a semiconductor device of the present embodiment, the impurity diffusion region 37 is formed at the interface between the active region and the trench side wall, so that the junction leak due to the depression at the edge is suppressed.

(Embodiment 4) FIG. 21 is a sectional view of a semiconductor device of this embodiment. In the semiconductor device according to the present embodiment, similarly to the third embodiment, the impurity is ion-implanted into the side wall portion 37 of the STI, and further, the STI deep region 3 is formed.
9 is ion-implanted at a low concentration with impurities of the conductivity type opposite to the channel type of the MOS transistor. As a result, a thin gate structure having low resistance and suppressed junction leakage is obtained. FIG. 21 shows that the S-channel
Although this is a cross-sectional view in which a TI is formed, this embodiment can be applied to a semiconductor substrate in which an n-channel transistor formation region and a p-channel transistor formation region are mixed, as in the first and second embodiments. Further, in the present embodiment, similarly to the third embodiment, from the viewpoint of preventing a short circuit,
The method cannot be applied to the case where gate wirings are formed crossing over the element isolation region (STI), but can be applied to transistors in other cases.

Next, a method of manufacturing the semiconductor device of the present embodiment will be described. First, as shown in FIG. 16A, a 10-nm-thick thermal oxide film is formed as a pad oxide film 14 on a silicon substrate 1, and an SiN film 15 is formed thereon by a low-pressure CVD method, for example, to a thickness of 150 nm. Formed. Subsequently, as shown in FIG. 16B, a resist 28 is formed to serve as a mask for forming a trench. Thereafter, as shown in FIG. 22A, the silicon substrate 1 is etched using the resist 28 as a mask to form the trench 17.

Next, as shown in FIG. 22B, a relatively low concentration impurity is ion-implanted into the inner wall of trench 17. In the trench of the n-channel MOS transistor formation region, for example, boron (B) as a p-type impurity has an ion energy of 100 keV and an introduced amount of 3 × 10 ¹² atoms.
Ions are implanted at s / cm ² . As a result, p-type impurity diffusion regions 39 are formed at the bottom and side wall portions of the trench. Although not shown, for example, phosphorus (P) as an n-type impurity is implanted in the trenches of the p-channel MOS transistor formation region at an ion energy of 100 keV and a dose of 3 ×.
Ion implantation is performed at 10 ¹² atoms / cm ² .

Next, as shown in FIG.
Resist 40 so that the interface between the substrate and the silicon substrate is opened.
To form Subsequently, as shown in FIG. 23B, impurities having the same conductivity type as the source / drain regions are ion-implanted using the resist 40 as a mask. In particular,
For example, arsenic (As) having an ion energy of 40 keV and an introduction amount of 5 × 10 ¹⁵ atoms is implanted as an n-type impurity on the trench sidewall of the n-channel MOS transistor formation region.
/ Cm ² to form an n ⁺ -type impurity diffusion region 37. Although not shown, for example, boron (BF ₂ ) as a p-type impurity has an ion energy of 20 ke on the trench side wall of the p-channel MOS transistor formation region.
V ions are implanted at a dose of 3 × 10 ¹⁵ atoms / cm ² .

Next, as shown in FIG. 24A, an oxide film (HDP film) 19 is deposited to a thickness of 600 nm using an ECR plasma CVD apparatus so as to fill the trench. Since the oxide film 19 is thickly deposited on the wide active region 20, the oxide film on the wide active region 20 is removed by etching using the resist 30 as a mask, as shown in FIG.

Subsequently, as shown in FIG.
Polishing is performed on the entire surface to flatten the surface. Thereafter, as shown in FIG. 25B, the SiN film 15 is removed by etching using hot phosphoric acid, and the pad oxide film 14 is further removed by light etching using hydrofluoric acid. As a result, impurities are ion-implanted into the side wall portion 37 of the STI, and M
A semiconductor substrate is formed in which impurities of a conductivity type opposite to that of the channel type of the OS transistor are ion-implanted at a low concentration. Hereinafter, according to the same process as in the first embodiment, M
By forming the OS transistor, a semiconductor device as shown in FIG. 21 is obtained.

(Embodiment 5) FIG. 26A is a sectional view of a semiconductor device of this embodiment. In the semiconductor device of the present embodiment, there is no depression at the edge of the trench,
The surface of the source / drain region 5 of the OS transistor is flattened, and aggregation of silicide is suppressed. As a result, a thin gate structure having low resistance and suppressed junction leakage is obtained.

Hereinafter, a method for manufacturing the semiconductor device of the present embodiment will be described. The manufacturing method of the semiconductor device of the present embodiment is the same as that of the third embodiment up to the step of providing an STI (element isolation region) in the semiconductor substrate.
This will be described with reference to FIG.

First, as shown in FIG. 16A, a 10-nm-thick thermal oxide film is formed as a pad oxide film 14 on the silicon substrate 1. An SiN film 15 having a thickness of 150 nm is formed thereon by, for example, a low pressure CVD method. Subsequently, as shown in FIG. 16B, a resist 28 is formed to serve as a mask for forming a trench. As shown in FIG. 16C, the silicon substrate 1 is etched using the resist 28 as a mask to form the trench 17. As shown in FIG. 17A, an oxide film (HDP film) 19 is deposited to a thickness of 600 nm so as to fill the trench 17 using, for example, an ECR plasma CVD apparatus.
Since the oxide film 19 is deposited thick on the wide active region 20, the oxide film 19 on the wide active region 20 is removed by etching using the resist 30 as a mask, as shown in FIG.

Subsequently, as shown in FIG.
Polishing is performed on the entire surface to flatten the surface. Thereafter, etching using hot phosphoric acid (70 ° C.) is performed to remove the SiN film 15. Next, as shown in FIG. 27A, an oxide film 41 is formed by SOG (spin-on-glass) to flatten the surface. FIG. 27 (B)
As shown in FIG. 5, C is again formed in a state where the SOG film 41 is formed.
When MP is performed, the oxide film 19 in the trench and the surface of the silicon substrate 1 are uniformly flattened. Then, FIG.
As shown in FIG. 7, the pad oxide film 14 is removed by performing light etching using hydrofluoric acid. Through the above steps, a semiconductor substrate having no depression at the end of the trench is formed. Subsequently, a MOS transistor is formed on a semiconductor substrate according to the same process as that of the first embodiment, whereby the structure shown in FIG.
A semiconductor device as shown in FIG.

(Embodiment 6) FIG. 28A is a sectional view of a semiconductor device of this embodiment. In the semiconductor device of the present embodiment, similarly to the fifth embodiment, there is no depression at the edge portion of the trench, the surface of the source / drain region 5 of the MOS transistor is flattened, and aggregation of silicide is suppressed. As a result, a thin-line gate structure with low resistance and suppressed junction leakage is obtained.

Hereinafter, a method for manufacturing the semiconductor device of this embodiment will be described. The manufacturing method of the semiconductor device of the present embodiment is the same as that of the third embodiment up to the step of providing an STI (element isolation region) in the semiconductor substrate.
This will be described with reference to FIG. First, as shown in FIG. 16A, a 10 nm-thick pad oxide film 1 is formed on a silicon substrate 1.
4 is formed thereon, and S is formed thereon by, for example, low pressure CVD.
An iN film 15 is formed with a thickness of 150 nm. Subsequently, FIG.
As shown in FIG. 6B, a resist 28 is formed to serve as a mask for forming a trench. FIG. 16 (C)
As shown in FIG. 7, a trench 17 is formed in a silicon substrate using the resist 28 as a mask.

As shown in FIG. 17A, for example, ECR
Using a plasma CVD apparatus, an oxide film (HDP film) 19 is deposited to a thickness of 600 nm so as to fill the trench 17. Since the oxide film 19 is thickly deposited on the wide active region 20, as shown in FIG.
Oxide film 1 on wide active area 20 using 0 as a mask
9 is removed by etching. Subsequently, as shown in FIG. 28B, the entire surface is polished by CMP to planarize the surface.

Next, as shown in FIG. 29A, etching using hot phosphoric acid (70 ° C.) is performed to remove the SiN film 15. Further, light etching using hydrofluoric acid is performed to remove the pad oxide film 14. In this step, a depression 21 occurs at the edge of the trench.

As shown in FIG. 29B, the exposed surface of the silicon substrate 1 is etched to flatten the depression 21 at the edge of the trench. This etching can be performed, for example, by immersing the semiconductor substrate in KOH for 10 minutes. Thus, a semiconductor substrate having a flattened surface is obtained. Subsequently, a MOS transistor is formed on a semiconductor substrate according to the same process as in the first embodiment, whereby a semiconductor device as shown in FIG. 28A is obtained. According to the method for manufacturing a semiconductor device of the present embodiment, since the MOS transistor is formed after the trench at the edge of the trench is etched and flattened, the silicide is formed when the salicide is formed on the source / drain region. Aggregation can be prevented. Thereby, junction leak is suppressed.

(Embodiment 7) FIG. 30A is a sectional view of a semiconductor device of this embodiment. In the semiconductor device of the present embodiment, similarly to the fifth or sixth embodiment, there is no depression at the edge portion of the trench, the surface of the source / drain region 5 of the MOS transistor is flattened, and aggregation of silicide is suppressed. I have. As a result, a thin gate structure having low resistance and suppressed junction leakage is obtained.

Hereinafter, a method for manufacturing the semiconductor device of the present embodiment will be described. The method for manufacturing a semiconductor device according to the present embodiment includes a step of providing an STI (element isolation region) in a semiconductor substrate (FIGS. 16A to 17B) and a step of removing a pad oxide film (FIG. 28B )) Are the same as in the third or fifth embodiment. Therefore, description will be made with reference to the above drawings.

First, as shown in FIG. 16A, a pad oxide film 14 having a thickness of 10 nm is formed on a silicon substrate 1, and an SiN film 1 is formed thereon by, for example, a low pressure CVD method.
5 is formed with a thickness of 150 nm. Subsequently, FIG.
As shown in (1), a resist 28 is formed to serve as a mask for forming a trench. Further, FIG.
As shown in (1), the silicon substrate 1 is etched using the resist 28 as a mask to form the trench 17.

As shown in FIG. 17A, for example, ECR
Using a plasma CVD apparatus, an oxide film (HDP film) 19 is deposited to a thickness of 600 nm so as to fill the trench 17. As shown in FIG. 17B, a wide active area 2
The oxide film 19 deposited thickly on the substrate 0 is removed by etching using the resist 30 as a mask. Subsequently, FIG.
As shown in (1), polishing is performed on the entire surface by CMP to flatten the surface.

Next, as shown in FIG. 30B, etching using hot phosphoric acid (70 ° C.) is performed to remove the SiN film 15. Further, light etching using hydrofluoric acid is performed to remove the pad oxide film 14. In this step, a depression 21 is formed at the edge of the trench 17.

Next, as shown in FIG. 31A, a gate oxide film 3 is formed by thermal oxidation, and a polysilicon layer 31 for forming a gate electrode is formed on the gate oxide film 3 with a thickness of, for example, 2 nm.
Deposit at 00 nm. The formation of the polysilicon layer 31
For example, it is performed under the following conditions. Film forming gas: SiH ₄ / He / N ₂ = 100/400/2
00 sccm pressure: 70 Pa, substrate temperature: 610 ° C. Here, in order to prevent oxidation of the polysilicon layer 31, a SiN or SiO ₂ layer having a thickness of about 100 nm may be laminated on the polysilicon layer 31.

Further, the polysilicon layer 31 (or alternatively,
After depositing a resist 32 on the upper layer of the polysilicon layer 31 (SiN or SiO ₂ layer), predetermined patterning is performed on the resist 32. When the polysilicon layer 31 is etched using the resist 32 as a mask, FIG.
As shown in (B), a gate electrode 4 is formed. The etching of the polysilicon layer 31 is performed, for example, under the following conditions. Etching _{gas: Cl 2 / O 2 / HBr} = 75/2/1
20 sccm pressure: 1 Pa, RF power: 60 W, microwave output: 850 W (However, SiN or Si
In the case where the O ₂ layer is formed, before etching the polysilicon layer 31, an etching gas: C ₄ F ₈
= 50 sccm, pressure: 2 Pa, RF power: 1200
Etching is performed under the condition of W. )

Next, as shown in FIG. 31C, ion implantation is performed using the gate electrode 4 as a mask to form the LDD region 6 in a self-aligned manner. In the n-channel transistor formation region, for example, arsenic is ion-energy 30 keV,
Ion implantation is performed under the conditions of an introduction amount of 1 × 10 ¹³ atoms / cm ² . In the p-channel transistor formation region,
For example, boron is ion energy 30 keV, introduction amount 1
Ion implantation is performed under the condition of × 10 ¹³ atoms / cm ² .
Thereby, the LDD region 6 is formed.

Further, as shown in FIG. 31C, in order to provide the sidewalls 7 on the gate electrode 4, an oxide film (or a single-layer SiN film,
It may be a SiN / SiO ₂ multilayer film. ) Is deposited. This oxide film is formed, for example, under the following conditions. Film forming gas: TEOS (tetraethoxysilane) = 50s
ccm temperature: 720 ° C, pressure: 40Pa

Thereafter, the entire surface is etched back under the following conditions, for example. Etching gas: C ₄ F ₈ = 50 sccm, pressure: 2
Pa RF power: 1200 W As a result, the insulator sidewall 7 is formed on the gate electrode 4.

Next, as shown in FIG. 32A, light etching using hydrofluoric acid is performed to remove the gate oxide film 3 in portions other than the gate electrode 4. Further, the exposed surface of the silicon substrate 1 is etched to flatten the depression 21 at the edge of the trench. This etching can be performed, for example, by immersing the semiconductor substrate in KOH for 10 minutes. Or, CF ₄ = 20 sccm,
It can also be performed by chemical dry etching for 60 seconds.

Next, as shown in FIG. 32B, ion implantation is performed using the sidewall 7 as a mask,
The drain region 5 is formed. In the n-channel type MOS transistor formation region, for example, arsenic is ion-energy 6
Ion implantation is performed under the conditions of 0 keV and a dose of 3 × 10 ¹⁵ atoms / cm ² . In the p-channel MOS transistor formation region, for example, BF ₂ is ion-energy 4
Ion implantation is performed under the conditions of 0 keV and a dose of 3 × 10 ¹⁵ atoms / cm ² . Thereafter, a short-time heat treatment at about 1000 ° C. is performed to diffuse the ion-implanted impurities into the source / drain regions 5, thereby forming a MOS transistor.

Subsequently, the resistance of the source / drain region 5 or the gate electrode 4 is reduced by applying the SALICIDE technique. That is, as shown in FIG. 33A, a refractory metal layer 33 such as a Ti / Co layer or a TiN / Co layer is formed on the entire surface by sputtering. Thereafter, a Ti / Co layer or a TiN / C layer on the source / drain region 5 and the gate electrode 4 is formed by the first RTA.
The o layer is silicided. Next, as shown in FIG. 33B, the non-silicided metal layer 3 on the oxide film is formed.
3 was removed using sulfuric acid / hydrogen peroxide solution, and then 2nd
By performing RTA, a low-resistance silicide layer 34 is formed.

Further, by forming an interlayer insulating film, a contact hole, a metal wiring, and the like according to the same steps as those of the first embodiment, a semiconductor device as shown in FIG. 30A is obtained. According to the method for manufacturing a semiconductor device of the present embodiment, after forming the gate electrode, etching is performed to flatten the depression at the edge of the trench. The etching for eliminating the depression at the edge portion may be performed after the formation of the gate electrode as in the present embodiment, or may be performed in the sixth embodiment.
It may be performed before forming the gate electrode as described above.

The semiconductor device and the method of manufacturing the same according to the present invention are not limited to the above embodiments. For example, the metal layer can be formed by a CVD method other than the sputtering. Further, by the semiconductor device and the method of manufacturing the same according to the present invention, it is possible to form a device other than the MOS transistor, for example, a bipolar transistor or a CCD, on the semiconductor substrate in which the depression at the edge of the STI is eliminated. The metal to be silicided in the SALICIDE step is T other than Co.
High melting point transition metals such as i, Ni, W, Mo, Pt, Zr, and Hf may be used. In addition, various changes can be made without departing from the gist of the present invention.

[0116]

According to the semiconductor device of the present invention, the problem of junction leakage caused by the depression at the edge of the trench is eliminated in the semiconductor device in which element isolation is performed by STI. Further, the problem of junction leak due to film stress at the edge of the trench and concentration of crystal defects is also solved. Further, according to the method for manufacturing a semiconductor device of the present invention, salicide which is hard to cause agglomeration of silicide even on a narrow active region and has a reduced thickness can be formed.
Thus, the resistance of the source / drain region is reduced, and a semiconductor device with high integration, high frequency characteristics, and low power consumption can be manufactured.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a manufacturing step of the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating a manufacturing step of the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view illustrating a manufacturing step of the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a sectional view illustrating a manufacturing step of the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 6 is a sectional view illustrating a manufacturing step of the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 7 is a cross-sectional view illustrating a manufacturing step of the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 8 is a cross-sectional view illustrating a manufacturing step of the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 9 is a cross-sectional view illustrating a manufacturing step of the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 10 is a sectional view illustrating a manufacturing step of the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 11 is a sectional view of a semiconductor device according to a second embodiment of the present invention.

FIG. 12 is a cross-sectional view illustrating a manufacturing step of the method for manufacturing a semiconductor device according to the second embodiment of the present invention.

FIG. 13 is a cross-sectional view illustrating a manufacturing step of the method for manufacturing a semiconductor device according to the second embodiment of the present invention.

FIG. 14 is a sectional view illustrating a manufacturing step of the method for manufacturing a semiconductor device according to the second embodiment of the present invention.

FIG. 15 is a sectional view of a semiconductor device according to a third embodiment of the present invention.

FIG. 16 is a cross-sectional view illustrating a manufacturing step of the manufacturing method of the semiconductor device according to the third embodiment of the present invention.

FIG. 17 is a cross-sectional view illustrating a manufacturing step of the method for manufacturing a semiconductor device according to the third embodiment of the present invention.

FIG. 18 is a cross-sectional view illustrating a manufacturing step of the method for manufacturing a semiconductor device according to the third embodiment of the present invention.

FIG. 19 is a sectional view illustrating a manufacturing step of the method for manufacturing a semiconductor device according to the third embodiment of the present invention.

FIG. 20 is a cross-sectional view illustrating a manufacturing step of the manufacturing method of the semiconductor device according to the third embodiment of the present invention.

FIG. 21 is a cross-sectional view of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 22 is a sectional view illustrating a manufacturing step of the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention.

FIG. 23 is a sectional view illustrating a manufacturing step of the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention.

FIG. 24 is a cross-sectional view illustrating a manufacturing step of the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention.

FIG. 25 is a sectional view illustrating a manufacturing step of the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention.

FIG. 26A is a cross-sectional view of a semiconductor device according to a fifth embodiment of the present invention, and FIG. 26B is a cross-sectional view illustrating manufacturing steps of a method of manufacturing the semiconductor device according to the fifth embodiment of the present invention. .

FIG. 27 is a sectional view illustrating a manufacturing step of the method for manufacturing a semiconductor device according to the fifth embodiment of the present invention.

FIG. 28A is a cross-sectional view of a semiconductor device according to Embodiment 6 of the present invention, and FIG. 28B is a cross-sectional view illustrating manufacturing steps of a method of manufacturing a semiconductor device according to Embodiment 6 of the present invention; .

FIG. 29 is a cross-sectional view illustrating a manufacturing step of the manufacturing method of the semiconductor device according to the sixth embodiment of the present invention.

FIG. 30A is a cross-sectional view of a semiconductor device according to a seventh embodiment of the present invention, and FIG. 30B is a cross-sectional view illustrating a manufacturing process of the method of manufacturing a semiconductor device according to the seventh embodiment of the present invention. .

FIG. 31 is a cross-sectional view illustrating a manufacturing step of the method for manufacturing a semiconductor device according to the seventh embodiment of the present invention.

FIG. 32 is a cross-sectional view illustrating a manufacturing step of the manufacturing method of the semiconductor device according to the seventh embodiment of the present invention.

FIG. 33 is a cross-sectional view illustrating a manufacturing step of the manufacturing method of the semiconductor device according to the seventh embodiment of the present invention.

FIG. 34 is a cross-sectional view illustrating a manufacturing step of a conventional semiconductor device manufacturing method.

FIG. 35 is a cross-sectional view illustrating a manufacturing step of a conventional semiconductor device manufacturing method.

FIG. 36 is a cross-sectional view illustrating a manufacturing step of a conventional semiconductor device manufacturing method.

FIG. 37 is a cross-sectional view illustrating a manufacturing step of a conventional semiconductor device manufacturing method.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Element isolation layer (LOCOS), 3
... Gate insulating film, 4 gate electrode, 5 source / drain region, 6 LDD region, 7 sidewall, 8 titanium silicide layer, 9 interlayer insulating film, 10 contact hole, 11 barrier metal layer, 12: tungsten plug, 13: metal wiring layer, 14: pad oxide film, 15,
35: silicon nitride film (SiN film), 16, 28, 2
9, 30, 32, 40: resist, 17: trench, 1
8, 19, 38: oxide film, 20: wide active area,
21: recess (dip) at trench edge, 22: n-channel transistor forming region (n region), 23 ... n ⁺ impurity diffusion region at shallow portion of n region, 24, 39 ... p-type impurity at deep portion of n region Diffusion regions, 25: p-channel transistor formation region (p region); 26, p ⁺ impurity diffusion region in a shallow portion of p region; 27, n-type impurity diffusion region in a deep portion of p region; 31: polysilicon layer; 33 ...
High melting point metal layer, 34 ... High melting point metal silicide layer, 36 ...
Cu layer, 37 ⁺ n ⁺ impurity diffusion region on the side wall of trench in n region, 41 ··· oxide film (SOG film).

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/108 H01L 27/14 B 21/8242 27/148 F-term (Reference) 4M118 FA27 5F032 AA35 AA44 AB01 AC01 BB01 CA17 CA18 DA10 DA24 DA33 DA43 DA77 DA78 5F048 BB05 BB08 BC06 BF06 BF07 BF12 BF16 BG01 BG14 BG15 DA25 5F082 AA17 BA05 EA09 EA27 5F083 GA06 JA37 JA39 JA40 MA05 MA19 NA01 PR05 PR23 PR37 PR38 PR40

Claims (15)

[Claims] 1. A semiconductor device having a plurality of element formation regions separated from each other by an element isolation region on a semiconductor substrate, wherein the element isolation region is formed by embedding an insulating film formed on a surface of the semiconductor substrate. At the upper end of the interface between the device forming region and the trench.
A semiconductor device in which a first conductivity type impurity is diffused and has the same conductivity type as a charge carrier of a semiconductor element formed in the element formation region. 2. The semiconductor device according to claim 1, wherein a second conductivity type impurity having a conductivity type opposite to that of the charge carrier of said semiconductor element is diffused in a portion of said semiconductor substrate which is in contact with said trench bottom and side wall. Semiconductor device. 3. The semiconductor device according to claim 1, wherein at least one of said semiconductor elements is an n-channel field-effect transistor, and at least one of said semiconductor elements is a p-channel field-effect transistor. 4. A semiconductor device having a plurality of element formation regions separated from each other by an element isolation region on a semiconductor substrate, wherein the element isolation region is formed by embedding an insulating film formed on a surface of the semiconductor substrate. A first conductivity type impurity having the same conductivity type as that of a charge carrier of a semiconductor element formed in the element formation region is diffused at an interface between the element formation region and the trench side wall. Semiconductor device. 5. The semiconductor substrate according to claim 4, wherein a second conductivity type impurity having a conductivity type opposite to that of a charge carrier of said semiconductor element is diffused in a portion of said semiconductor substrate which is in contact with said trench bottom and side wall. Semiconductor device. 6. A semiconductor device having a plurality of element formation regions separated from each other by an element isolation region on a semiconductor substrate, wherein the element isolation region is embedded with an insulating film formed on a surface of the semiconductor substrate. A semiconductor device, wherein the surfaces of the element formation region and the element isolation region are planarized to a uniform height. 7. A semiconductor device having a plurality of element formation regions separated from each other by an element isolation region on a semiconductor substrate, wherein the element isolation region is an insulating film embedded in a trench formed on a surface of the semiconductor substrate. An upper end portion of an interface between the device forming region and the trench;
A semiconductor device in which a surface of the element formation region is flattened to a uniform height. 8. A process for forming a sacrificial film on a semiconductor substrate, a process for forming a protective layer on the sacrificial film, and a device for separating the plurality of device formation regions from each other in the semiconductor substrate. Forming an isolation groove (trench); embedding an insulating film in the trench so that a part thereof protrudes on the surface of the semiconductor substrate; performing chemical mechanical polishing on the insulating film; Forming a semiconductor element in the element forming region, and forming a semiconductor element in the element forming region. After forming the protective layer, the charge of the semiconductor element is stored in the trench forming region and its peripheral portion. Diffusing a first conductivity type impurity having the same conductivity type as that of the carrier, wherein the step of forming the trench includes forming the first conductivity type impurity diffusion layer on an edge of the trench. A method of manufacturing a semiconductor device, wherein the trench is formed while leaving at a predetermined interval. 9. The step of diffusing the first conductivity type impurity is a step of performing oblique ion implantation using a resist having a pattern of the element formation region as a mask.
The manufacturing method of the semiconductor device described in the above. 10. A step of diffusing an impurity of a second conductivity type, which has a conductivity type opposite to that of charge carriers of the semiconductor element, into a portion of the semiconductor substrate in contact with a bottom portion and a side wall portion of the trench after forming the trench. 9. The method for manufacturing a semiconductor device according to claim 8, comprising: 11. A method for forming a sacrificial film on a semiconductor substrate, forming a protective layer on the sacrificial film, and forming an element for separating the plurality of element formation regions from each other on the semiconductor substrate. Forming an isolation groove (trench); embedding an insulating film in the trench so that a part thereof protrudes on the surface of the semiconductor substrate; performing chemical mechanical polishing on the insulating film; Forming a semiconductor element in the element formation region, and forming a semiconductor element in the element formation region, after forming the element isolation region, at an interface between the trench sidewall portion and the element formation region, A method of manufacturing a semiconductor device, comprising: diffusing a first conductivity type impurity having the same conductivity type as a charge carrier of the semiconductor element. 12. A step of diffusing a second conductivity type impurity having a conductivity type opposite to that of a charge carrier of the semiconductor element into a portion of the semiconductor substrate in contact with a bottom portion and a side wall portion of the trench after forming the trench. The method of manufacturing a semiconductor device according to claim 11, further comprising: 13. A process for forming a sacrificial film on a semiconductor substrate, a process for forming a protective layer on the sacrificial film, and a device for separating the plurality of device formation regions from each other in the semiconductor substrate. Forming an isolation groove (trench); embedding an insulating film in the trench so that a part thereof protrudes on the surface of the semiconductor substrate; performing chemical mechanical polishing on the insulating film; Forming a semiconductor device in the element forming region, and a step of removing the protective layer after performing a chemical mechanical polishing on the insulating film; A step of applying silicon oxide dispersed in an organic solvent (spin-on-glass; SOG) on the entire surface to form an oxide film; and performing a second chemical mechanical polishing to form the element formation region; Previous The method of manufacturing a semiconductor device having a step of the surface of the isolation region, thereby flattening the uniform height. 14. A method for forming a sacrificial film on a semiconductor substrate, forming a protective layer on the sacrificial film, and forming an element for separating the plurality of element formation regions from each other on the semiconductor substrate. Forming an isolation groove (trench); embedding an insulating film in the trench so that a part thereof protrudes on the surface of the semiconductor substrate; performing chemical mechanical polishing on the insulating film; Forming a semiconductor device in the element forming region, and performing a chemical mechanical polishing on the insulating film, removing the protective layer, Exposing the semiconductor substrate in the element formation region; etching the semiconductor substrate exposed in the element formation region to form an upper end portion of an interface between the element formation region and the trench; Flattening the surface of the element formation region to a uniform height, and forming the semiconductor element in the element formation region,
A method of manufacturing a semiconductor device, comprising forming the semiconductor element in the element formation region, which is flattened to a uniform height with an upper end portion of an interface between the element formation region and the trench. 15. A device for forming a sacrificial film on a semiconductor substrate, a process for forming a protective layer on the sacrificial film, and a device for separating the plurality of device forming regions from each other in the semiconductor substrate. Forming an isolation groove (trench); embedding an insulating film in the trench so that a part thereof protrudes on the surface of the semiconductor substrate; performing chemical mechanical polishing on the insulating film; Forming a semiconductor element in the element forming region, and forming a semiconductor element in the element forming region. The method according to claim 1, further comprising: etching the surface of the semiconductor element after forming the semiconductor element, A method for manufacturing a semiconductor device, comprising: flattening an upper end portion of an interface with the trench and a surface of the element formation region to a uniform height.