KR100365409B1 - Method for forming a gate electrode in semiconductor device - Google Patents

Abstract

The present invention discloses a method for forming a gate electrode of a semiconductor device having a silicide film capable of preventing electrical shorts due to misalignment of self align contacts. The disclosed invention comprises forming a gate electrode composed of a gate insulating film, a doped polysilicon film, and a transition metal silicide film on a semiconductor substrate; And oxidizing the surface of the transition metal silicide film of the gate electrode by a predetermined thickness to form a self-aligning barrier oxide film.

Description

METHODE FOR FORMING A GATE ELECTRODE IN SEMICONDUCTOR DEVICE

The present invention relates to a method for forming a gate electrode of a semiconductor device, and more particularly to a method for forming a gate electrode of a semiconductor device having a metal silicide film.

In general, the gate electrode is an electrode for selecting a MOS transistor, and is mainly formed of a polysilicon film doped with impurities or a laminated film of a polysilicon film and a tungsten silicide film WSi ₂ doped with impurities.

However, the above-described impurity doped polysilicon film and impurity-doped polysilicon film / tungsten silicide film are easily used in semiconductor devices having low integration, but have low resistance value characteristics as the fine gate electrodes of the current highly integrated semiconductor devices. There is a difficulty in using it because it is not satisfied.

Accordingly, a method of forming a gate electrode by stacking a titanium silicide layer (TiSi ₂ ) having superior conductivity than a tungsten silicide layer on a polysilicon layer has been proposed, which will be described with reference to FIGS. 1A to 1D. .

Referring to FIG. 1A, a gate insulating film 3, a polysilicon film doped with impurities, and a hard mask film 5 are sequentially deposited on the semiconductor substrate 1 having the field oxide film 2. A predetermined partial pattern is formed to form a gate electrode structure composed of a hard mask film 5, a doped polysilicon film 4, and a gate insulating film 3. Subsequently, spacers 6 are formed on the sidewalls of the gate electrode structure by a known method. Next, predetermined impurities are implanted into the semiconductor substrate 1 outside the spacer 6 to form source and drain regions 7a and 7b.

Thereafter, as shown in FIG. 1B, an interlayer insulating film 8 is formed over the resulting product of the semiconductor substrate 1 on which the gate electrode structure and the source and drain regions 7a and 7b are formed. The interlayer insulating film 8 is then chemically mechanically polished to expose the surface of the doped polysilicon film 3 of the gate electrode structure. By this chemical mechanical polishing process, part of the upper part of the spacer 6 is removed, and the surface of the resultant semiconductor substrate 1 is flattened. Thereafter, a titanium metal film 9 is deposited on the planarized semiconductor substrate 1 to a predetermined thickness.

Next, as shown in FIG. 1C, the resultant semiconductor substrate 1 is rapidly heat treated at a predetermined temperature. Then, the titanium metal film 9 on the polysilicon film 4 is reacted with the doped polysilicon film 4 below and converted into the titanium silicide film 10. Meanwhile, the titanium metal film 9 on the interlayer insulating film 8 and the spacer 6 is not changed to the titanium silicide film 10 and remains as it is.

Thereafter, as illustrated in FIG. 1D, the titanium metal film 9 and the titanium silicide film 10 are chemically mechanically polished so that the interlayer insulating film 8 is exposed, thereby providing a gate electrode having the titanium silicide film 10 ( g) is completed. Then, although not shown in the figure, an interlayer insulating film covering the completed gate electrode is formed, and then a contact hole for exposing a source or drain region is formed in the interlayer insulating film. Thereafter, a conductive film is formed in the interlayer insulating film including the contact hole, and then the conductive film is etched back to form a contact plug.

In the related art, since the insulating film for the self-aligned contact is not provided at the time of forming the contact and the contact plug, the insulating film must be deposited separately on the gate electrode g after the gate electrode g is formed.

However, when a process of depositing a self-aligning barrier oxide film and a patterning process separately on the minute gate electrode g is thus easily performed, misalignment easily occurs during the patterning process, and misalignment of the self-aligning barrier oxide film occurs. The short circuit between the metal wires, the metal wires, and the gate electrode g has occurred due to misalignment of the self-aligned contact forming process.

Accordingly, an object of the present invention is to provide a method for forming a gate electrode of a semiconductor device, which can prevent the electrical short circuit caused by misalignment of a self-aligned contact.

1A to 1D are cross-sectional views of respective processes for explaining a method of forming a gate electrode of a conventional semiconductor device.

2A to 2F are cross-sectional views of respective processes for explaining a method of forming a gate electrode of a semiconductor device according to an embodiment of the present invention.

Figure 3a and Figure 3b is a cross-sectional view for each process for explaining another embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

21-semiconductor substrate 23-gate insulating film

24-doped polysilicon film 27a, 27b-source, drain region

29-titanium metal film 30-titanium silicide film

34,40-Self Aligning Barrier Oxides

In order to achieve the above object of the present invention, according to an embodiment of the present invention, forming a gate electrode structure consisting of a gate insulating film, a doped polysilicon film and a hard mask film on a semiconductor substrate; Forming spacers on both sidewalls of the gate electrode structure; Forming a source / drain region in the semiconductor substrate on both sides of the gate electrode structure; Forming a first interlayer insulating film over the semiconductor substrate resultant; Chemical mechanical polishing the first interlayer insulating film to expose the doped polysilicon film of the gate electrode structure; Selectively forming a transition metal silicide film over the exposed doped polysilicon film and within the spacer; Forming a second interlayer insulating film over the entire substrate including the transition metal silicide film; Etching the first and second interlayer insulating films to form a contact hole exposing any one of the source / drain regions and a portion of the transition metal silicide film of the gate electrode; Oxidizing the exposed transition metal silicide film surface to form a self-aligning barrier oxide film; And forming a contact plug filling the contact hole.

Further, according to another embodiment of the present invention, forming a gate electrode structure consisting of a gate insulating film, a doped polysilicon film and a hard mask film on a semiconductor substrate; Forming spacers on both sidewalls of the gate electrode structure; Forming a source / drain region in the semiconductor substrate on both sides of the gate electrode structure; Forming a first interlayer insulating film over the semiconductor substrate resultant; Chemical mechanical polishing the first interlayer insulating film to expose the doped polysilicon film of the gate electrode structure; Selectively forming a transition metal silicide film over the exposed doped polysilicon film and within the spacer; Oxidizing the surface of the transition metal silicide film to form a self-aligning barrier oxide film; Forming a second interlayer insulating film on the resulting substrate; Etching the first and second interlayer insulating films until one of the source / drain regions and a predetermined portion of the self-aligning barrier oxide film is exposed to form contact holes; And forming a contact plug filling the contact hole.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2F are cross-sectional views of respective processes for explaining a method of forming a gate electrode of a semiconductor device according to an embodiment of the present invention, and FIGS. 3A and 3B are diagrams for describing another embodiment of the present invention. It is sectional drawing by each process.

Referring to FIG. 2A, a field oxide film 22 is formed on the semiconductor substrate 21 by a known method. Thereafter, the gate insulating film 23, the polysilicon film 24 doped with impurities and the hard mask film 25 are sequentially deposited on the semiconductor substrate 21, and then patterned by a predetermined portion to form the hard mask film 25. ), A gate electrode structure composed of the doped polysilicon film 24 and the gate insulating film 23 is formed. Subsequently, a screen oxide film (not shown) is formed on the semiconductor substrate resultant surface, and low concentration impurities are implanted into the semiconductor substrates on both sides of the gate electrode structure. Thereafter, spacers 6 are formed on both sidewalls of the gate electrode structure by a known method, and then high concentration impurities are implanted into the semiconductor substrate into which the low concentration impurities are ion implanted, thereby forming a lightly doped drain (LDD) type source and drain region. 27a, 27b).

Thereafter, as shown in FIG. 2B, a first interlayer insulating film 28 is formed to have a thickness of 5000 to 7000 에 on the resulting product of the semiconductor substrate 21 on which the gate electrode structure and the source and drain regions 27a and 27b are formed. Then, the first interlayer insulating film 28 is chemically mechanically polished to expose the surface of the doped polysilicon film 23 of the gate electrode structure. By this chemical mechanical polishing process, a part of the upper portion of the spacer 26 is removed, and the surface of the resultant semiconductor substrate 21 is flattened. Thereafter, a transition metal film, for example, a titanium metal film 29, is deposited on the planarized semiconductor substrate 21 to a thickness of 500 to 1000 Å.

Next, as shown in FIG. 2C, the resultant semiconductor substrate 1 is subjected to rapid thermal processing (RTP) for 10 to 30 seconds in a nitrogen atmosphere in a chamber maintaining a temperature of 800 to 850 ° C. In this RTP process, the titanium metal film 29 on the polysilicon film 24 is reacted with the doped polysilicon film 24 thereon to form a self-aligned titanium silicide film 30. Meanwhile, the titanium interlayer 28 and the titanium metal layer 29 on the spacer 26 do not react with each other and remain in the titanium metal layer 29.

Thereafter, as shown in FIG. 2D, the remaining titanium metal film 29 and the titanium silicide film 30 are chemically mechanically polished so that the first interlayer insulating film 28 is exposed, and the titanium silicide film 30 is provided. One gate electrode G is completed.

Next, as shown in FIG. 2E, a second interlayer insulating film 32 is deposited on the first interlayer insulating film 28. Thereafter, predetermined portions of the first and second interlayer insulating films 28 and 32 are etched to expose one of the source and drain regions 27a and 27b to form a contact hole H. When etching the contact hole H, a predetermined portion of the titanium silicide layer 30 of the gate electrode G is exposed. Subsequently, the exposed titanium silicide layer 30 is oxidized at a temperature of 800 to 900 ° C. to form a self-aligning barrier oxide layer 34 of about 100 to about 300 kPa on the exposed surface.

Thereafter, referring to FIG. 2F, a conductive layer, for example, a polysilicon film is deposited so that the contact hole H is sufficiently filled, and then chemically mechanically polished or etched back to form the contact plug 35. At this time, a self-aligning barrier oxide film 34 is formed between the contact plug 35 and the gate electrode G, and the contact plug 35 and the gate electrode G are electrically insulated from each other.

3A and 3B are cross-sectional views for describing another embodiment of the present invention. The processes of FIGS. 2A to 2D are the same as the above-described embodiment, and the subsequent steps will be described.

First, referring to FIG. 3A, the titanium silicide layer 30 of the exposed gate electrode G is oxidized at a temperature of 800 to 900 ° C. to form a self-aligning barrier oxide layer 40 on the titanium silicide layer 30. .

Thereafter, as illustrated in FIG. 3B, after the second interlayer insulating film 32 is deposited, the first and second interlayer insulating films 28 and 32 are exposed so that any one of the source and drain regions 27a and 27b is exposed. Is etched to form contact holes. When forming the contact hole, a portion of the self-aligning barrier oxide layer 40 on the gate electrode G is exposed. Thereafter, a contact plug 35 is formed in the contact hole.

As described in detail above, according to the present invention, a gate electrode is formed of a laminated film of a polysilicon film and a titanium silicide film, and then the upper portion of the titanium silicide film is oxidized to form a self-aligning barrier oxide film. As a result, a separate deposition and patterning process for forming the self-aligning barrier oxide film is excluded, thereby preventing misalignment. Accordingly, it is possible to prevent a short between the contact plug and the gate electrode.

In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (10)

delete delete Forming a gate electrode structure composed of a gate insulating film, a doped polysilicon film, and a hard mask film on the semiconductor substrate; Forming spacers on both sidewalls of the gate electrode structure; Forming a source / drain region on the semiconductor substrate on both sides of the gate electrode structure; Forming a first interlayer insulating film on the semiconductor substrate product; Chemical mechanical polishing the first interlayer insulating film to expose the doped polysilicon film of the gate electrode structure; Selectively forming a transition metal silicide layer on the exposed doped polysilicon layer and in the spacer; Forming a second interlayer insulating film on an entire surface of the substrate including the transition metal silicide film; Etching the first and second interlayer insulating films to form contact holes exposing any one of the source / drain regions and a portion of the transition metal silicide film of the gate electrode; Oxidizing the exposed transition metal silicide film surface to form a self-aligning barrier oxide film; And And forming a contact plug filling the contact hole. The method of claim 3, wherein the forming of the transition metal silicide layer comprises: Depositing a transition metal film on the first interlayer insulating film including the exposed polysilicon film: Heat treating the transition metal film at a predetermined temperature to selectively form a transition metal silicide film on the exposed polysilicon film; And And chemically mechanically polishing the remaining transition metal film and the transition metal silicide film until a point at which the first interlayer insulating film is exposed. The gate electrode formation of the semiconductor device according to claim 4, wherein the heat treatment process for forming the selective silicide film is performed for 10 to 30 seconds in a nitrogen atmosphere in a chamber maintaining a temperature of 800 to 850 ° C. Way. The method of claim 3, wherein the oxidation process for forming the self-aligning barrier oxide film is performed at a temperature of 800 to 900 ° C. until the thickness of the oxide film is about 100 to 300 kPa. Forming a gate electrode structure composed of a gate insulating film, a doped polysilicon film, and a hard mask film on the semiconductor substrate; Forming spacers on both sidewalls of the gate electrode structure; Forming a source / drain region on the semiconductor substrate on both sides of the gate electrode structure; Forming a first interlayer insulating film on the semiconductor substrate product; Chemical mechanical polishing the first interlayer insulating film to expose the doped polysilicon film of the gate electrode structure; Selectively forming a transition metal silicide layer on the exposed doped polysilicon layer and in the spacer; Oxidizing a surface of the transition metal silicide film to form a self-aligning barrier oxide film; Forming a second interlayer insulating film on the resulting substrate; Forming a contact hole by etching the first and second interlayer insulating films until one of the source / drain regions and a predetermined portion of the self-aligning barrier oxide film is exposed; And And forming a contact plug filling the contact hole. The method of claim 7, wherein the forming of the transition metal silicide film, Depositing a transition metal film on the first interlayer insulating film including the exposed polysilicon film: Heat treating the transition metal film at a predetermined temperature to selectively form a transition metal silicide film on the exposed polysilicon film; And And chemically mechanically polishing the remaining transition metal film and the transition metal silicide film until a point at which the first interlayer insulating film is exposed. The semiconductor device of claim 8, wherein the heat treatment step for selectively forming the transition metal silicide film is performed for 10 to 30 seconds in a nitrogen atmosphere in a chamber maintaining a temperature of 800 to 850 ° C. 10. Gate electrode formation method. The method of claim 7, wherein the oxidation process for forming the self-aligning barrier oxide film is performed at a temperature of 800 to 900 ° C. until the oxide film is formed to about 100 to 300 kPa.