JPH06216151A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide a minute semiconductor device having the high reliability by reducing the diffusion of impurities, and enhancing the dielectric strength of a sidewall with respect to a conductor film. CONSTITUTION:The first sidewall comprising an SiO2 film 22 formed by high- temperature CVD is formed on the side surfaces of a polycide film 16 and an SiO2 film 17. The second sidewall comprising an SiO2 film 24 formed by low-temperature CVD is formed on the outer surface of the SiO2 film 22. Therefore, heat treatment to be applied is less and the diffusion of impurities 21 and 23, which are already introduced, is less in comparison with the case, wherein the entire sidewall is formed of the SiO2 film 22. The etching of the SiO2 film 22 having the excellent film quantity can be prevented with the SiO2 film 24.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a sidewall formed on a side surface of a conductive film such as a gate electrode and a method for manufacturing the same.

[0002]

2. Description of the Related Art An LD for relaxing the electric field concentration in the drain of a field effect semiconductor device and increasing the drain breakdown voltage.
In the D structure and the self-aligned contact structure for making it unnecessary to secure a margin area when opening the contact hole, the side wall made of an insulating film is formed on the side surface of the conductive film such as the gate electrode. And conventionally, this side wall was formed with a single insulating film.

[0003]

By the way, the sidewall formed on the side surface of the conductive film plays at least part of the interlayer breakdown voltage between this conductive film and the upper conductive film. Therefore, from the standpoint of dielectric strength, a high temperature CV of about 800 ° C or higher under reduced pressure is used.
An insulating film formed of D and having a low pinhole density and good film quality is preferable. However, in high temperature CVD, not only a large amount of heat is applied per unit time, but also the deposition rate is slow.
For example, even if a SiO ₂ film is formed at 820 ° C., 2 nm /
It only deposits at the rate of minutes.

Therefore, in the case of CVD at 820 ° C., S having a film thickness of about 100 nm in 50 minutes is added in view of the amount of heat applied.
Only the iO ₂ film can be deposited. For this reason, particularly in the self-aligned contact structure, the side wall formed is further etched when the contact hole is opened, so that the withstand voltage of the side wall may not be sufficient. However, when a SiO ₂ film having a film thickness larger than this is formed, the amount of heat applied becomes too large, and the diffusion of impurities already introduced becomes too large.

As a result, in particular, since boron for forming a P-type impurity layer has a large diffusion coefficient, punch-through easily occurs in a P-channel transistor. Therefore, in the conventional example in which the sidewall insulating film is formed only by high temperature CVD,
It was not possible to provide a highly reliable semiconductor device which is fine and has high withstand voltage of the side wall.

On the other hand, when a SiO ₂ film is formed by low temperature CVD at a temperature of about 800 ° C. or less under reduced pressure and about 400 ° C. or less under normal pressure, the SiO ₂ film has high pinhole density and poor film quality. To secure the dielectric strength, 4
It is necessary to deposit it to a film thickness of about 00 nm.

However, in the LDD structure, a low concentration impurity layer is formed under the side wall. In particular, arsenic for forming the N-type impurity layer has a small diffusion coefficient, so if the width of the side wall is about 400 nm, the width of the low-concentration impurity layer is also 40.
The current driving capability of the N-channel transistor is drastically reduced when the value is close to 0 nm. Therefore, in the conventional example in which the sidewall insulating film is formed only by the low temperature CVD, it is not possible to provide a semiconductor device having a high current driving capability.

[0008]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a first side wall made of a first insulating film 22 formed at a relatively high temperature is formed on a side surface of the conductive film 16. And the second insulating film 24 formed at a relatively low temperature
The second side wall of the conductive film 16 on the first side wall.
And a step of forming the side surface on the opposite side.

According to another aspect of the semiconductor device of the present invention, the first sidewall is formed of the first insulating film 22 generated at a relatively high temperature, and the first sidewall is formed on the side surface of the conductive film 16. The second sidewall is formed of the second insulating film 24 generated at the temperature, and the second sidewall is formed on the side surface of the first sidewall opposite to the conductive film 16.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a step of forming a gate electrode 16 on the first and second conductivity type regions 12 and 13 of the semiconductor substrate 11 and the first conductivity type region 12 are performed.
Using the gate electrode 16 as a mask, and introducing the second conductivity type impurity 21 into the first conductivity type region 12 at a relatively low concentration; and after introducing the second conductivity type impurity 21, The first and second conductive regions 12 and 13 formed on the side surface of the gate electrode 16 at a relatively high temperature.
Forming a first side wall of the insulating film 22 of the second conductive type region 13, and using the gate electrode 16 and the first side wall of the second conductive type region 13 as a mask, the second conductive type region 13 of the first conductive type is formed. The step of introducing the type impurity 23 in a relatively low concentration, and the step of introducing the first conductivity type impurity 23, and then the gate electrode 16 on the first sidewall of the first and second conductivity type regions 12 and 13. A second side wall made of a second insulating film 24 formed at a relatively low temperature on a side surface opposite to the side surface, and the gate electrode 16 of the first conductivity type region 12 and the first side wall of the first conductivity type region 12. And using the second sidewall as a mask,
Introducing a second conductivity type impurity 26 into the first conductivity type region 12 in a relatively high concentration; and the second conductivity type region 13
Using the gate electrode 16 and the first and second side walls as a mask, and introducing the first conductivity type impurity 27 into the second conductivity type region 13 at a relatively high concentration.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a step of forming a gate electrode 16 on the first and second conductivity type regions 12 and 13 of the semiconductor substrate 11 and the first conductivity type region 12 are performed.
Using the gate electrode 16 as a mask, and introducing the second conductivity type impurity 21 into the first conductivity type region 12 at a relatively low concentration; and after introducing the second conductivity type impurity 21, The first and second conductive regions 12 and 13 formed on the side surface of the gate electrode 16 at a relatively high temperature.
Forming a first side wall made of the insulating film 22 of the first conductive type region 12, and using the gate electrode 16 and the first side wall of the first conductive type region 12 as a mask, a second conductive type region is formed in the first conductive type region 12. The second conductivity type region 1 is formed by using the step of introducing the type impurities 26 in a relatively high concentration and the gate electrode 16 and the first sidewall of the second conductivity type region 13 as a mask.
3, a step of introducing the first conductivity type impurity 23 at a relatively low concentration, and a step of introducing the second conductivity type impurity 26 at a relatively high concentration and introducing the first conductivity type impurity 23,
A second insulating film 24 formed at a relatively low temperature is formed on a side surface of the first sidewall of the first and second conductivity type regions 12 and 13 opposite to the gate electrode 16. A step of forming a side wall, and using the gate electrode 16 and the first and second side walls of the second conductivity type region 13 as a mask, the first conductivity type impurity 27 is formed in the second conductivity type region 13.
Is introduced in a relatively high concentration.

[0012]

According to the method of manufacturing a semiconductor device of the first aspect, the first side wall made of the first insulating film 22 formed at a relatively high temperature and the second insulating film 24 formed at a relatively low temperature are used. Since the second side wall is formed, the amount of heat treatment to be applied is smaller than that of the method of forming the entire side wall with the insulating film formed at a high temperature, and the impurity 2 which has already been introduced is used.
There is little diffusion of 1, 23, and 26.

Further, the first side wall of the first insulating film 22 formed at a relatively high temperature is covered with the second side wall of the second insulating film 24 formed at a relatively low temperature. Therefore, even if the side wall is subsequently etched, the second side wall can prevent the first side wall having good film quality from being etched. Therefore, a method of forming the entire sidewall with an insulating film formed at a low temperature or covering the sidewall formed of an insulating film formed at a relatively low temperature with a sidewall formed of an insulating film formed at a relatively high temperature As compared with the above, it is possible to form a sidewall having a higher dielectric strength voltage with respect to the conductive film 16.

According to another aspect of the semiconductor device of the present invention, the first side wall made of the first insulating film 22 formed at a relatively high temperature and the second side insulating film 24 formed at a relatively low temperature are formed. Since the second side wall is formed, the heat treatment applied is smaller and the impurities 21, 23, and 23 are formed as compared with the structure in which the entire side wall is formed of an insulating film formed at a high temperature.
26 is less diffused.

Further, the first produced at a relatively high temperature
Since the first side wall of the insulating film 22 is covered with the second side wall of the second insulating film 24 generated at a relatively low temperature, even if the side wall is etched later,
The second side wall can prevent the first side wall having good film quality from being etched. Therefore, the entire sidewall is formed of an insulating film formed at a low temperature, or the sidewall formed of an insulating film formed at a relatively low temperature is formed by an insulating film formed at a relatively high temperature. The withstand voltage of the side wall with respect to the conductive film 16 is higher than that of the covered structure.

In the method of manufacturing a semiconductor device according to the third aspect, the gate electrode 16 is used as a mask for introducing the impurity 21 of the second conductivity type into the first conductivity type region 12 at a relatively low concentration. First conductivity type impurity 23 for region 13
The introduction of a relatively low concentration of is performed by using not only the gate electrode 16 but also the first sidewall as a mask. Therefore, even if the diffusion coefficient of the first conductivity type impurity 23 is larger than the diffusion coefficient of the second conductivity type impurity 21, it is possible to prevent the first conductivity type impurity layers 33 from being too close to each other from both sides of the gate electrode 16. You can

Further, the first side wall made of the first insulating film 22 formed at a relatively high temperature is covered with the second side wall made of the second insulating film 24 formed at a relatively low temperature. Therefore, even if the side wall is subsequently etched, the second side wall can prevent the first side wall having good film quality from being etched. Therefore, a method of forming the entire sidewall with an insulating film formed at a low temperature or covering the sidewall formed of an insulating film formed at a relatively low temperature with a sidewall formed of an insulating film formed at a relatively high temperature It is possible to form a sidewall having a higher withstand voltage with respect to the gate electrode 16 as compared with.

In the method of manufacturing a semiconductor device according to the fourth aspect, the gate electrode 16 is used as a mask for introducing the impurity 21 of the second conductivity type into the first conductivity type region 12 at a relatively low concentration. First conductivity type impurity 23 for region 13
The introduction of a relatively low concentration of is performed by using not only the gate electrode 16 but also the first sidewall as a mask. Therefore, even if the diffusion coefficient of the first conductivity type impurity 23 is larger than the diffusion coefficient of the second conductivity type impurity 21, it is possible to prevent the first conductivity type impurity layers 33 from being too close to each other from both sides of the gate electrode 16. You can

The introduction of the first conductivity type impurity 27 into the second conductivity type region 13 at a relatively high concentration is required for the gate electrode 1.
6 and the first and second sidewalls are used as a mask, the introduction of the second conductivity type impurity 26 into the first conductivity type region 12 at a relatively high concentration uses only the gate electrode 16 and the first sidewall as a mask. Therefore, the width of the second-conductivity-type impurity layer 31 having a relatively low concentration is narrower than that of the method in which the second sidewall is also used as a mask.

Further, the first side wall of the first insulating film 22 formed at a relatively high temperature is covered with the second side wall of the second insulating film 24 formed at a relatively low temperature. Therefore, even if the side wall is subsequently etched, the second side wall can prevent the first side wall having good film quality from being etched. Therefore, a method of forming the entire sidewall with an insulating film formed at a low temperature or covering the sidewall formed of an insulating film formed at a relatively low temperature with a sidewall formed of an insulating film formed at a relatively high temperature It is possible to form a sidewall having a higher withstand voltage with respect to the gate electrode 16 as compared with.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First and second embodiments of the present invention applied to a CMOS transistor having an LDD structure and a self-aligned contact structure will be described below with reference to FIGS. FIG. 1 shows the manufacturing method of the first embodiment in the order of steps. In the first embodiment, as shown in FIG.
First, the P well 12 and the N well 13 are formed on the substrate 11. Then, Si is formed on the surface of the element isolation region of the Si substrate 11.
An O ₂ film 14 is formed, and a SiO ₂ film 15 as a gate oxide film is formed on the surface of the element active region.

After that, the SiO ₂ films 14 and 15 are formed by the CVD method.
An impurity is added to the polycrystalline Si film by a pre-deposition method or the like in which a polycrystalline Si film is deposited and exposed to vapor of POCl ₃ to thermally diffuse phosphorus from the vapor. And CV
A WSi _x film is deposited on the polycrystalline Si film by the D method, and the polycide film 16 is formed by the polycrystalline Si film and the WSi _x film.

After that, SiO for offset is formed by the CVD method.
₂ film 17 is deposited on polycide film 16 and
_{2 On the} film 17, a resist (not shown) is processed into a gate electrode pattern. Then, the SiO ₂ film 17 and the polycide film 16 are continuously processed into a pattern of the gate electrode by RIE using this resist as a mask. While up to this point is the same as conventionally known production method, in the present embodiment, then the SiO ₂ film 14 and 17 and the polycide film 16 of the P-well 12 as a mask, only the device active region of the P-well 12 Arsenic 21 is ion-implanted at a low concentration.

Next, the SiO ₂ film 22 is formed by the above-mentioned high temperature CVD.
Is deposited on the entire surface, the entire surface of the SiO ₂ film 22 is etched back, and as shown in FIG.
A side wall made of the SiO ₂ film 22 is formed on the side surface of the SiO ₂ film 17. Then, the SiO ₂ film 1 of the N well 13
Using 4, 17, 22 and the polycide film 16 as a mask,
Boron 23 is ion-implanted at a low concentration only in the element active region of the N well 13.

Next, the SiO ₂ film 24 is formed by the above-mentioned low temperature CVD.
Was deposited on the entire surface, the entire surface of the SiO ₂ film 24 is etched back, as shown in FIG. 1 (c), to form the sidewall of SiO ₂ film 24 on the outer surface of the SiO ₂ film 22. As a result, the contact hole 25 surrounded by the SiO ₂ films 14 and 24 is opened in a self-aligned manner with respect to the polycide film 16.

After that, the SiO ₂ film 14 of the P well 12 is
Using the 22, 17 and 24 and the polycide film 16 as masks, phosphorus 26 is highly ion-implanted into the element active region of the P well 12, and the SiO ₂ films 14, 17 of the N well 13 are formed.
By using 22 and 24 and the polycide film 16 as a mask, boron 27 is ion-implanted at a high concentration into the element active region of the N well 13.

Next, after forming wiring (not shown), annealing is performed to form the P well 12 as shown in FIG. 1 (d).
Then, the N ⁻ -type impurity layer 31 containing the arsenic 21 is formed into SiO ₂
Formed under the films 22 and 24, an N ⁺ type impurity layer 32 mainly containing phosphorus 26 is formed outside the SiO ₂ films 22 and 24. In the N well 13, a P ⁻ type impurity layer 33 containing boron 23 is formed under the SiO ₂ film 24, and a P ⁺ type impurity layer 34 mainly containing boron 27 is formed in the SiO ₂ film 22.
It is formed outside 24.

As a result, an N channel transistor 35 is formed in the P well 12 and a P channel transistor 36 is formed in the N well 13. Then, the conventionally known process is executed again to complete the first embodiment. Also in the first embodiment, the P ⁻ -type impurity layer 33 is also diffused laterally to some extent, but at least the polycide film 1 is formed.
It is offset from 6. Therefore, punch-through is unlikely to occur in the P-channel transistor 36, and even if the impurity layer 33 is offset from the polycide film 16, the P-channel transistor 36 does not affect the current drive capability.

FIG. 2 shows the manufacturing method of the second embodiment in the order of steps. Also in this second embodiment, as shown in FIGS. 2A and 2B, until the side wall of the SiO ₂ film 22 is formed on the side surface of the polycide film 16 and the SiO ₂ film 17, the above-described first embodiment is performed. Substantially the same steps are performed.

However, in this second embodiment, from this state, the boron 23 is lowered in the element active region of the N well 13 by using the SiO ₂ films 14, 17, 22 of the N well 13 and the polycide film 16 as a mask. Not only is the concentration of ions implanted, but phosphorus 26 is also implanted at a high concentration in the element active region of the P well 12 using the SiO ₂ films 14, 17, 22 of the P well 12 and the polycide film 16 as a mask.

Therefore, as shown in FIG. 2C, the low temperature CV
Ion implantation performed in the SiO ₂ film 24 by D while forming a sidewall on the outer surface of the SiO ₂ film 22, SiO ₂ film 14,17,22,24 and polycide film 16 of the N-well 13
Using as a mask, only high-concentration ion implantation of boron 27 is performed on the element active region of the N well 13. Thereafter, the steps substantially similar to those of the first embodiment described above are executed again to complete the second embodiment as shown in FIG.

As is apparent from the comparison between FIG. 1D and FIG. 2D, the impurity layer 3 of the N-channel transistor 35 is shown.
2, in the first embodiment described above are formed on the outside of the SiO ₂ film 22, in this second embodiment are formed on the outside of the SiO ₂ film 22. Therefore, N of the second embodiment
In the channel transistor 35, the width of the impurity layer 31 is narrower and the current driving capability is higher.

Although both the first and second embodiments described above apply the invention of the present application to a CMOS transistor having an LDD structure and a self-aligned contact structure, it is applied to a transistor not having a self-aligned contact structure. If so, the offset Si on the polycide film 16
The O ₂ film 17 is unnecessary.

[0034]

According to the method of manufacturing a semiconductor device of claim 1,
Since the diffusion of impurities is small, a fine semiconductor device can be manufactured. Moreover, since a sidewall having a high withstand voltage with respect to the conductive film can be formed, a highly reliable semiconductor device can be manufactured.

In the semiconductor device according to the second aspect, since the diffusion of impurities is small, miniaturization is possible. Further, since the side wall has a high withstand voltage against the conductive film, the reliability is high.

In the method of manufacturing a semiconductor device according to the third aspect, even if the diffusion coefficient of the first conductivity type impurity is larger than the diffusion coefficient of the second conductivity type impurity, the first conductivity type impurity layers are close to each other from both sides of the gate electrode. Since it is possible to prevent the excessive conduction, it is possible to manufacture a complementary semiconductor device in which punch-through hardly occurs in the first conductivity type channel transistor.
In addition, since a sidewall having a high withstand voltage with respect to the gate electrode can be formed, a highly reliable semiconductor device can be manufactured.

In the method of manufacturing a semiconductor device according to the fourth aspect, even if the diffusion coefficient of the first conductivity type impurity is larger than the diffusion coefficient of the second conductivity type impurity, the first conductivity type impurity layers are close to each other from both sides of the gate electrode. Since it is possible to prevent the excessive conduction, it is possible to manufacture a complementary semiconductor device in which punch-through hardly occurs in the first conductivity type channel transistor.
Further, since the width of the second conductivity type impurity layer having a relatively low concentration is narrow, it is possible to manufacture a complementary semiconductor device in which the current conductivity of the second conductivity type channel transistor is high. Further, since the side wall having high withstand voltage against the gate electrode can be formed, a highly reliable semiconductor device can be manufactured.

[Brief description of drawings]

FIG. 1 is a side sectional view showing a first embodiment of the present invention in the order of steps.

FIG. 2 is a side sectional view showing a second embodiment of the invention of the present application in the order of steps.

[Explanation of symbols]

11 Si substrate 12 P-well 13 N-well 16 Polycide film 21 Arsenic 22 SiO ₂ film 23 Boron 24 SiO ₂ film 26 Phosphorus 27 Boron

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical indication H01L 21/31 C 27/092

Claims (4)

[Claims] 1. A step of forming a first side wall made of a first insulating film formed at a relatively high temperature on a side surface of a conductive film, and a step of forming a second insulating film formed at a relatively low temperature. Second
A side wall of the first side wall opposite to the conductive film of the first side wall. 2. A first insulating film formed at a relatively high temperature, the first insulating film being formed on a side surface of the conductive film.
And a second sidewall formed of a second insulating film formed at a relatively low temperature and formed on a side surface of the first sidewall opposite to the conductive film. Semiconductor device. 3. A step of forming gate electrodes in first and second conductivity type regions of a semiconductor substrate; and using the gate electrodes of the first conductivity type regions as a mask,
Introducing a second conductivity type impurity into the first conductivity type region at a relatively low concentration; and, after introducing the second conductivity type impurity, a side surface of the gate electrode in the first and second conductivity type regions. And forming a first side wall made of a first insulating film formed at a relatively high temperature, and using the gate electrode and the first side wall of the second conductivity type region as a mask, Introducing a first conductivity type impurity into the second conductivity type region at a relatively low concentration; and introducing the first conductivity type impurity into the second conductivity type region, and then introducing the first conductivity type impurity into the first sidewall of the first and second conductivity type regions. Forming a second side wall made of a second insulating film formed at a relatively low temperature on a side surface opposite to the gate electrode; the gate electrode in the first conductivity type region; Using the second sidewall as a mask, the second conductivity type is applied to the first conductivity type region. Introducing a relatively high concentration of type impurities, and using the gate electrode and the first and second sidewalls of the second conductivity type region as a mask to form the first conductivity type impurity in the second conductivity type region. A method of manufacturing a semiconductor device, the method comprising: 4. A step of forming a gate electrode in first and second conductivity type regions of a semiconductor substrate, and using the gate electrode of the first conductivity type region as a mask,
Introducing a second conductivity type impurity into the first conductivity type region at a relatively low concentration; and, after introducing the second conductivity type impurity, a side surface of the gate electrode in the first and second conductivity type regions. A step of forming a first side wall made of a first insulating film formed at a relatively high temperature, and using the gate electrode and the first side wall of the first conductivity type region as a mask, Introducing a second conductivity type impurity into the first conductivity type region in a relatively high concentration, and using the gate electrode and the first sidewall of the second conductivity type region as a mask to form the second conductivity type region. Introducing a first conductivity type impurity in a relatively low concentration; and introducing the second conductivity type impurity in a relatively high concentration and introducing the first conductivity type impurity, and thereafter, the first and second impurities
Forming a second side wall of a second insulating film formed at a relatively low temperature on a side surface of the first side wall of the conductivity type region opposite to the gate electrode; A step of introducing a first conductivity type impurity into the second conductivity type region in a relatively high concentration using the gate electrode and the first and second sidewalls of the mold region as a mask. Method.