JP2508782B2 - Method for manufacturing CMOS semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device including a CMOS (complementary insulated gate semiconductor) element, and particularly to an impurity region in which a semiconductor substrate is formed, a metal silicide layer, and an upper aluminum wiring. To a method for forming a contact with.

[Conventional technology]

Conventionally, in CMOS type semiconductor devices, p-channel MOS
A method shown in FIGS. 3 (a) and 3 (b) has been proposed as a method for contacting an aluminum wiring with each impurity region of (pMOS) or n-channel MOS. (NMOS) or a metal silicide layer.

That is, as shown in FIG. 3A, the n-well 2 is formed in the p-type silicon substrate 1 and the element isolation region 3 is formed to define the element region. Then, a gate electrode such as tungsten silicide and a wiring 5 are formed on the element isolation region 3 and the gate insulating film, and an n-type region 6 as a source / drain of an nMOS is formed on the substrate 1 and a pMOS is formed on the n well 2. A p-type basin 7 is formed as the source / drain of.

 Then, an interlayer insulating film 8 such as BPSG is formed on the front surface.

Then, a mask for contact opening is formed on the interlayer insulating film 8 using the photoresist 9, and isotropic etching (mainly wet etching using buffered hydrofluoric acid) is performed using this. Then, anisotropic etching (mainly dry etching using plasma such as RIE) is performed to reach the wiring 5, the n-type region 6, and the p-type region 7, respectively, with the contact holes 21 that are laterally widened upward. It will be opened in the state where it has been done.

After that, as shown in FIG. 3 (b), a conductive thin film 14 such as polysilicon is deposited on the entire surface to take measures against electrostatic breakdown,
The p-type region 6 is ion-implanted with boron and the n-type region 7 is ion-implanted with phosphorus or arsenic to form a contact region, and the aluminum thin film 15 is deposited on the entire surface by means such as sputtering or vapor deposition, and then the conductivity is obtained. The thin film 14 and the aluminum thin film 15 are formed in a desired pattern to form electrodes.

[Problems to be Solved by the Invention]

In the conventional contact formation method described above, in order to cope with the improvement in electrical characteristics due to the reduction in capacitance between wiring layers and the increase in integration due to the increase in wiring layers, when the thickness of the insulating film becomes thicker, finer contacts are formed. Then, there arises a problem that sufficient step coverage of aluminum wiring cannot be obtained. That is, as described above, conventionally, the step difference is alleviated by the taper formed by isotropic etching, but this alone causes a poor portion of the boundary between the isotropic and anisotropic etching surfaces. Step coverage is compromised.

To deal with this, if the isotropic etching is excessively performed, the distance between the contact and the wiring layer in the vicinity of the contact is shortened and the insulating property is deteriorated. Further, although there is a measure to alleviate a portion having an inferior boundary by heat treatment, if this method is applied to a CMOS type semiconductor device, the following problems occur.

In other words, if this type of heat treatment is performed in an inert atmosphere such as nitrogen gas after opening the p-channel side contact, PSG
Alternatively, phosphorus is out-diffused from an inter-layer insulating film containing phosphorus such as BPSG, and is introduced into the p-type region of the contact portion to form an n-type diffusion layer in some cases, thereby damaging the ohmic property of the cotact. Increase the leak in the section. Therefore, it is necessary to perform the step relaxation treatment while oxidizing the substrate surface in an oxidizing atmosphere.

On the other hand, when the treatment in the oxidizing atmosphere is performed in this way,
In the contact opening portion where the metal silicide layer is exposed, the oxidation of the silicide proceeds rapidly to form an insulative oxide film, greatly impairing the contact property. Therefore, it is necessary to perform this treatment in an inert atmosphere.

However, since the heat treatment cannot be performed simultaneously in the oxidizing atmosphere and the inert atmosphere, the heat treatment is not performed in the conventional method. Therefore, in the CMOS type semiconductor integrated circuit according to the conventional method, there is a problem in the step coverage of aluminum in the contact portion.

It is an object of the present invention to provide a method for manufacturing a CMOS type semiconductor device that can solve the above-mentioned problems and improve the step coverage of aluminum.

[Means for solving the problem]

A method of manufacturing a CMOS semiconductor device according to the present invention includes a step of first forming a contact hole connected to a p-type region in an interlayer insulating film, and a heat treatment in an oxidizing atmosphere to determine the inner surface shape of the contact hole. Improving and forming an oxide film on the surface of the p-type region, opening a contact hole connected to the n-type region and the metal silicide wiring in the interlayer insulating film, and performing heat treatment in an inert atmosphere. The method includes a step of improving the inner surface shape of the lever contact hole, and a step of removing an oxide film in the p-type region and then forming an upper wiring layer in each contact hole.

[Action]

In the method described above, since the inner surface shape of the contact hole in the p-type region is improved in an oxidizing atmosphere, an oxide film is formed on the surface of the p-type region, and the oxide film causes n-type impurities contained in the interlayer insulating film. Prevent the spread of. Further, since the inner surface shape of the contact hole of the n-type region and the metal silicide layer is improved in an inert atmosphere, the formation of an oxide film on the surface of the metal silicide layer is prevented. This makes it possible to effectively perform the heat treatment for alleviating the step difference in the contact hole.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

1 (a) to 1 (h) are longitudinal sectional views showing the first embodiment of the present invention in the order of manufacturing steps.

First, as shown in FIG. 1A, an n well 2 is formed on a p-type silicon substrate 1, and an element region is defined by an element isolation region 3 made of a thick oxide film. Further, a gate oxide film 4 is formed in the element region, and a polycide gate 5 made of tungsten silicide is formed on the gate oxide film 4 and the element isolation region 3. Then, by selectively introducing arsenic into the p-type silicon substrate 1, the n-type region 6 of the nMOS is formed.
Then, boron is similarly introduced into the n-well 2 to form the p-type region 7 as the source / drain of the pMOS.

Then, as shown in FIG. 1 (b), a BPSG (boron / phosphorus glass) thin film 8 is deposited by a normal pressure CVD method (chemical vapor deposition method) to a thickness of 1 μm, and this is applied in a nitrogen atmosphere. It heat-treats in and reduces the level difference of the surface.

Next, as shown in FIG. 1C, a photoresist 9 is applied to the entire surface, and a contact hole 10 on the pMOS side is formed in the BPSG thin film 8 by a photolithography process using the photoresist 9. At the time of this opening, the surface of the BPSG film 8 is isotropically etched with a mixed solution of hydrofluoric acid and ammonium fluoride and anisotropically opened to the p-type region 7 by reactive ion etching.

Then, as shown in FIG. 1 (d), the photoresist 9
And then followed by an oxidizing atmosphere, for example 90
Heat treatment is performed in a steam atmosphere at 0 ° C. to reduce the step difference of the contact hole 10. At this time, an oxide film 11 is grown on the exposed surface of the p-type region 7 to serve as a diffusion barrier.
Due to the barrier function of the oxide film 11, phosphorus that is outdiffused from the BPSG film 8 is not introduced into the p-type region 7.

After that, although not shown in the figure, a polysilicon thin film is deposited on the entire surface by the current pressure CVD method, and boron ions are implanted on the entire surface, and the BPSG film 8 is used as a mask to self-align in the contact hole 10. Boron is introduced only to form a contact region. The thin film of polysilicon is removed with hydrofluoric acid or the like. At this time, the substrate surface on the pMOS side is protected by the oxide film 11 and is not etched.

Then, as shown in FIG. 1E, a contact hole 13 is formed on the nMOS side and the polycide gate 5 by a photolithography process using a photoresist 12. At this time as well, the etching is performed in two steps of wet and dry as in the contact hole 10 of the pMOS.

Next, after removing the photoresist 12, FIG. 1 (f)
As described above, heat treatment is performed in an inert atmosphere to reduce the step difference on the inner surface of the contact hole 13 in the BPSG film 8. Also at this time, the contact hole 10 portion of the surface of the p-type region 7 is covered with the oxide film 11, and phosphorus released from the BPSG film 8 is not introduced.

Next, as shown in FIG. 1 (g), the oxide film 11 in the contact hole 10 is removed with a mixed solution of hydrofluoric acid and ammonium fluoride, and a polysilicon thin film is formed on the entire surface by using a reduced pressure CVD method. 14
To wear.

At this stage, the contact hole 10 is covered with a mask material formed of photoresist, for example, and the mask material and BPSG
Using the film 8 as a mask, phosphorus is ion-implanted into each contact hole 13 of the n-type region 6 and the polycide gate 5 in a partially self-aligning manner to form a contact region.

Incidentally, electrostatic breakdown may occur when it is injected into the gate of the MOS structure or when the injection amount is large, but in this example, both the pMOS and the nMOS are connected by the conductive polysilicon thin film 14. Therefore, the charge-up is prevented.

Then, as shown in FIG. 1 (h), an aluminum thin film 15 is deposited on the entire surface, and the polysilicon thin film 14 and the aluminum thin film 15 are simultaneously patterned by a photolithography process using a photoresist or the like to form an electrode. To do.

In this way, the metal silicide was used for the gate electrode.
In the CMOS device, diffusion of n-type impurities in the p-type region 7 can be prevented, and formation of an oxide film in other contacts can be prevented, and heat treatment for alleviating the step difference in the contact hole can be effectively performed. , Good aluminum step coverage is obtained.

2 (a) to 2 (g) are longitudinal sectional views showing a second embodiment of the present invention in the order of steps. The second embodiment shows an example having a polycide wiring layer of metal silicide in addition to the polycide gate in the first embodiment, and the same parts as those in the first embodiment are designated by the same reference numerals. There is.

First, as shown in FIG. 2A, after forming an n-well 2 on a p-type silicon substrate 1, an element isolation region 3 and a gate oxide film are formed.
The polysilicon wiring 16 integrated with the 4, n-type region 6, the p-type region 7 and the polysilicon gate (not shown) is formed similarly to the first embodiment. Further, a first interlayer insulating film 17 of BPSG, a polycide wiring 18 containing molybdenum silicide, and a second interlayer insulating film 19 of BPSG are sequentially formed on this.

Hereinafter, similar to the first embodiment, as shown in FIG. 2 (b),
A contact hole 10 is formed in the first and second interlayer insulating films 17 and 19 on the p-type region 7, and then heat-treated in an oxidizing atmosphere to form an inner surface of the contact hole 10 as shown in FIG. 2 (c). An oxide film 11 is formed on the p-type region 7 while improving the shape.

Then, as shown in FIG. 2D, the contact hole 1 is formed in the first and second interlayer insulating films 17 and 19 on the n-type region 6 and the polycide wiring 18.
3 is opened, and heat treatment is performed in an inert atmosphere to improve the shape of the inner surface of the contact hole 13 as shown in FIG.

After that, the oxide film 11 is removed by etching, and molybdenum silicide 20 is deposited on the entire surface as shown in FIG. At this stage, boron is introduced into the contact holes of the p-type region 6 and phosphorus is introduced into the other contact holes by ion implantation at this stage.

Then, as shown in FIG. 2 (g), an aluminum thin film 15 is deposited on the entire surface, and then the molybdenum silicide film 20 is formed into a desired pattern to form an electrode.

Also in the second embodiment, like the first embodiment, it is possible to prevent the diffusion of the n-type impurity in the p-type region 7 and to prevent the formation of an oxide film in the other contact, and to make the step of the contact hole suitable. It is possible to relax.

In the embodiment, the metal silicide is only tungsten or molybdenum, but other metal silicide may be used. Further, it may have a polycide structure as in the embodiment, or may have a single layer. Furthermore, the conductive thin film is not limited to molybdenum silicide, but a tungsten silicide alloy or the like is also possible.
The aluminum wiring is not limited to pure aluminum and may include impurities such as silicon and copper.

〔The invention's effect〕

As described above, according to the present invention, the inner surface shape of the contact hole in the p-type region is improved in an oxidizing atmosphere, so that an oxide film is generated on the surface of the p-type region and the oxide film is included in the interlayer insulating film. The diffusion of n-type impurities is prevented. Also, n
Since the inner surface shape of the contact hole of the mold region and the metal silicide layer is improved in an inert atmosphere, formation of an oxide film on the surface of the metal silicide layer is prevented. As a result, the heat treatment for alleviating the step difference of the contact hole can be effectively performed, and the aluminum coverage can be improved. Further, this method has an advantage that a conductive film as a countermeasure against electrostatic breakdown can be incorporated into one reasonably continuous process, and a semiconductor device excellent in shape and characteristics can be manufactured at low cost.

In the method of the present invention, the number of photolithography steps for opening contact holes is increased to two, but boron can be introduced into the p-type region in a self-aligned manner by using the interlayer insulating film as a mask. In a manufacturing method that requires a step of introducing impurities, the number of photolithography steps as a whole can be suppressed to the same number as before.

[Brief description of drawings]

1 (a) to 1 (h) are longitudinal sectional views showing the first embodiment of the present invention in the order of steps, and FIGS. 2 (a) to 2 (g).
Is a longitudinal sectional view showing a second embodiment of the present invention in the order of steps, and FIGS. 3 (a) and 3 (b) are longitudinal sectional views showing the conventional method in the order of steps. 1 ... p-type silicon substrate, 2 ... n-well, 3 ... element isolation region, 4 ... gate oxide film, 5 ... polycide gate, 6 ... n-type region, 7 ... p-type region, 8 …… BPSG interlayer insulation film, 9 …… Photoresist, 10 …… Contact hole,
11 …… Oxide film, 12 …… Photoresist, 13 …… Contact hole, 14 …… Polysilicon thin film, 15 …… Aluminum thin film, 16 …… Polysilicon wiring, 17 …… First BPSG interlayer insulating film, 18 …… Polycide wiring, 19 …… Second BPSG interlayer insulating film, 20 …… Molybdenum silicide.

Claims (1)

(57) [Claims] 1. A p-type region and an n-type region formed on a semiconductor substrate and a metal silicide wiring formed on the semiconductor substrate are n-typed.
In manufacturing a CMOS semiconductor device covered with an interlayer insulating film containing a type impurity, a step of first opening a contact hole connected to the p-type region in the interlayer insulating film, and a heat treatment in an oxidizing atmosphere And improving an inner surface shape of the contact hole and forming an oxide film on the surface of the p-type region, and forming a contact hole connected to the n-type region and the metal silicide wiring in the interlayer insulating film. And a step of performing a heat treatment in an inert atmosphere to improve the inner surface shape of the contact hole, and a step of removing the oxide film in the p-type region and then forming an upper wiring layer in each contact hole. A method of manufacturing a CMOS type semiconductor device, comprising: