JPS56118356A - Preparation of semiconductor device - Google Patents

Preparation of semiconductor device

Info

Publication number
JPS56118356A
JPS56118356A JP2143280A JP2143280A JPS56118356A JP S56118356 A JPS56118356 A JP S56118356A JP 2143280 A JP2143280 A JP 2143280A JP 2143280 A JP2143280 A JP 2143280A JP S56118356 A JPS56118356 A JP S56118356A
Authority
JP
Japan
Prior art keywords
layer
film
psg
sio
diffusion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2143280A
Other languages
Japanese (ja)
Inventor
Izumi Tanaka
Kazunari Shirai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2143280A priority Critical patent/JPS56118356A/en
Publication of JPS56118356A publication Critical patent/JPS56118356A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To make it possible to prevent the P diffusion into the P type diffusion layer, by forming a penetrating hole through the PSG film on the substrate and evaporating an insulating film prior to glass flow. CONSTITUTION:According to the normal method, a channel stopper 5, a field oxidized film 6, a P type diffusion layer 9, a gate oxidized film 7 and a polycrystalline Si gate 8 are formed and after an SiO2 10 and a PSG11 are stacked, a resist-mask 8 is formed and a window is opened. Then an SiO 13 is evaporated. Thereafter at the temperature of 1,050-1,100 deg.C the PSG is flowed to make the opening part smoother. At this time, the SiO film prevents the P diffusion into the N layer 9. Then the SiO is etched by HF solution and Al electrode 14 is formed. With such an arrangement, no breakdown of Al wirings occurs and the P diffusion from the PSG is prevented, resulting in a device of high reliability. Using BSG on the N layer can likewise be performed.
JP2143280A 1980-02-22 1980-02-22 Preparation of semiconductor device Pending JPS56118356A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2143280A JPS56118356A (en) 1980-02-22 1980-02-22 Preparation of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2143280A JPS56118356A (en) 1980-02-22 1980-02-22 Preparation of semiconductor device

Publications (1)

Publication Number Publication Date
JPS56118356A true JPS56118356A (en) 1981-09-17

Family

ID=12054814

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2143280A Pending JPS56118356A (en) 1980-02-22 1980-02-22 Preparation of semiconductor device

Country Status (1)

Country Link
JP (1) JPS56118356A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61251054A (en) * 1985-04-27 1986-11-08 Pioneer Electronic Corp Manufacture of semiconductor device
JPH01191468A (en) * 1988-01-27 1989-08-01 Nec Corp Manufacture of cmos type semiconductor device
US5284800A (en) * 1992-02-19 1994-02-08 Integrated Device Technology, Inc. Method for preventing the exposure of borophosphosilicate glass to the ambient and stopping phosphorus ions from infiltrating silicon in a semiconductor process

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61251054A (en) * 1985-04-27 1986-11-08 Pioneer Electronic Corp Manufacture of semiconductor device
JPH01191468A (en) * 1988-01-27 1989-08-01 Nec Corp Manufacture of cmos type semiconductor device
US5284800A (en) * 1992-02-19 1994-02-08 Integrated Device Technology, Inc. Method for preventing the exposure of borophosphosilicate glass to the ambient and stopping phosphorus ions from infiltrating silicon in a semiconductor process

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