JPS5461490A - Multi-layer wiring forming method in semiconductor device - Google Patents

Multi-layer wiring forming method in semiconductor device

Info

Publication number
JPS5461490A
JPS5461490A JP12750177A JP12750177A JPS5461490A JP S5461490 A JPS5461490 A JP S5461490A JP 12750177 A JP12750177 A JP 12750177A JP 12750177 A JP12750177 A JP 12750177A JP S5461490 A JPS5461490 A JP S5461490A
Authority
JP
Japan
Prior art keywords
layer
film
etching
oxide film
polysilicon layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12750177A
Other languages
Japanese (ja)
Inventor
Minoru Fujita
Hiroshi Kawamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP12750177A priority Critical patent/JPS5461490A/en
Publication of JPS5461490A publication Critical patent/JPS5461490A/en
Pending legal-status Critical Current

Links

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: To make adaptive the device for massproduction, by surely remaining the conductive layer of lower layer without taking different work as conventional etching works, through the electrical connection of the external wiring layer to the lower conductive layer via the upper conductive layer, at the window opening of the in sulaton film between layers.
CONSTITUTION: After forming the field oxide film 3 with the selective oxidation for the silicon wafer (substrate) 1, the silicon oxide film 2a, first(lower layer) layer polysilicon layer 4, insulation film between layers 5, and second gate oxide film 2b are formed. Next, the window opening 8 is made on the insulation film between layer 5, forming the second (upper layer) polysilicon layer 6 on the entire surface, and it is connected to the first polysilicon layer 4 via the window opening 8. Succeedingly, the gate oxide film 2b and the part other than the parts 6a and 6b of the second polysilicon layer are removed by etching, forming the source and drain region 10. Further, the phosphorus silicate glas film 11 is coated and the second layer polysilicon layer 6a is exposed by etching. Finally, the aluminum electrode (wiring) 7 is formed by evaporation and etching of aluminum
COPYRIGHT: (C)1979,JPO&Japio
JP12750177A 1977-10-26 1977-10-26 Multi-layer wiring forming method in semiconductor device Pending JPS5461490A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12750177A JPS5461490A (en) 1977-10-26 1977-10-26 Multi-layer wiring forming method in semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12750177A JPS5461490A (en) 1977-10-26 1977-10-26 Multi-layer wiring forming method in semiconductor device

Publications (1)

Publication Number Publication Date
JPS5461490A true JPS5461490A (en) 1979-05-17

Family

ID=14961523

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12750177A Pending JPS5461490A (en) 1977-10-26 1977-10-26 Multi-layer wiring forming method in semiconductor device

Country Status (1)

Country Link
JP (1) JPS5461490A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS571532U (en) * 1980-06-02 1982-01-06
JPS57126148A (en) * 1981-01-29 1982-08-05 Toshiba Corp Semiconductor integrated circuit
JPS57166048A (en) * 1981-04-06 1982-10-13 Nippon Telegr & Teleph Corp <Ntt> Semiconductor integrated circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS571532U (en) * 1980-06-02 1982-01-06
JPS57126148A (en) * 1981-01-29 1982-08-05 Toshiba Corp Semiconductor integrated circuit
JPS57166048A (en) * 1981-04-06 1982-10-13 Nippon Telegr & Teleph Corp <Ntt> Semiconductor integrated circuit

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