JPS577948A - Semiconductor device and its manufacture - Google Patents

Semiconductor device and its manufacture

Info

Publication number
JPS577948A
JPS577948A JP8313780A JP8313780A JPS577948A JP S577948 A JPS577948 A JP S577948A JP 8313780 A JP8313780 A JP 8313780A JP 8313780 A JP8313780 A JP 8313780A JP S577948 A JPS577948 A JP S577948A
Authority
JP
Japan
Prior art keywords
layer
contact holes
wiring
insulating
bored
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8313780A
Other languages
Japanese (ja)
Inventor
Shiyouji Ariizumi
Makoto Segawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP8313780A priority Critical patent/JPS577948A/en
Priority to DE19813123348 priority patent/DE3123348A1/en
Priority to US06/274,197 priority patent/US4544941A/en
Publication of JPS577948A publication Critical patent/JPS577948A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5286—Arrangements of power or ground buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

PURPOSE:To form a plurality of contact holes accurately in the same process by approximately uniformalizing the thickness of an insulating layer to which the contact holes for forming electrode extracting wiring are bored. CONSTITUTION:An N type source diffusion layer 22 is formed in one region of a P type semiconductor substrate 20 partitioned by a separating layer 21 among elements. Wiring layers 23 consisting of polycrystal silicon are made up on the element separating layer 21, and the first insulating layers 24 consisting of oxide films are built up on the exposed surface of the wiring layers 23. A gate oxide film 25 is formed on another region of the substrate 20. A gate electrode 26 and a conductor layer 28 for extracting an electrode connected to the wiring layer 23 through a window 27 bored to the first insulating film 24 are made up by a polycrystal silicon layer. The second insulating layer 29 consisting of an oxide film is built up on these whole surface. The contact holes 22a, 28a are formed by means of the same photo- etching process and etching process.
JP8313780A 1980-06-19 1980-06-19 Semiconductor device and its manufacture Pending JPS577948A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP8313780A JPS577948A (en) 1980-06-19 1980-06-19 Semiconductor device and its manufacture
DE19813123348 DE3123348A1 (en) 1980-06-19 1981-06-12 Semiconductor chip and method of producing it
US06/274,197 US4544941A (en) 1980-06-19 1981-06-16 Semiconductor device having multiple conductive layers and the method of manufacturing the semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8313780A JPS577948A (en) 1980-06-19 1980-06-19 Semiconductor device and its manufacture

Publications (1)

Publication Number Publication Date
JPS577948A true JPS577948A (en) 1982-01-16

Family

ID=13793810

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8313780A Pending JPS577948A (en) 1980-06-19 1980-06-19 Semiconductor device and its manufacture

Country Status (1)

Country Link
JP (1) JPS577948A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS638153U (en) * 1986-07-04 1988-01-20
US5244832A (en) * 1985-10-16 1993-09-14 Texas Instruments Incorporated Method for fabricating a poly emitter logic array and apparatus produced thereby

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5244832A (en) * 1985-10-16 1993-09-14 Texas Instruments Incorporated Method for fabricating a poly emitter logic array and apparatus produced thereby
JPS638153U (en) * 1986-07-04 1988-01-20

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