JPS57133637A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS57133637A
JPS57133637A JP1908181A JP1908181A JPS57133637A JP S57133637 A JPS57133637 A JP S57133637A JP 1908181 A JP1908181 A JP 1908181A JP 1908181 A JP1908181 A JP 1908181A JP S57133637 A JPS57133637 A JP S57133637A
Authority
JP
Japan
Prior art keywords
region
gettering
single crystal
diffusion
circumference
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1908181A
Other languages
Japanese (ja)
Inventor
Sakatoshi Okubo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP1908181A priority Critical patent/JPS57133637A/en
Publication of JPS57133637A publication Critical patent/JPS57133637A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering

Abstract

PURPOSE:To obtain an IC which withstands high voltage by a method wherein, when the single crystal region provided in the inside of a semiconductor element structure is insulation-isolated using a dielectric, a gettering region with a high density of phosphorus doping on the circumference of a single crystal region is formed, and a uniform gettering effect is given to elements. CONSTITUTION:A plurality of concaved sections, to be used for the formation of semiconductor elements, are provided on a polycrystalline Si region 101, the side wall and the bottom face are covered by an SiO2 layer 102, and an N<+> type region 11 is formed along the region 101 and the layer 102 to obtain a high withstand voltage. Then, an Si single crystal region 103 is coated on the region 11 and used as a substrate 1, the whole surface is covered by an SiO2 film 21 which will be used for surface protection, an aperture is provided, and a P<+> type functional regions 12 and 13 are formed by diffusion in the region 103. Besides, an N<+> type region 14, which will be located on the circumference of the region 103 and will be contacting the upper inside of the region 11, is formed by diffusion using phosphorus, and this region is used as a gettering region. Through these procedures, the gettering effect of each substrate 1 is made uniform and the withstand voltage of which is improved.
JP1908181A 1981-02-13 1981-02-13 Semiconductor integrated circuit device Pending JPS57133637A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1908181A JPS57133637A (en) 1981-02-13 1981-02-13 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1908181A JPS57133637A (en) 1981-02-13 1981-02-13 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS57133637A true JPS57133637A (en) 1982-08-18

Family

ID=11989486

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1908181A Pending JPS57133637A (en) 1981-02-13 1981-02-13 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS57133637A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4985745A (en) * 1988-01-05 1991-01-15 Kabushiki Kaisha Toshiba Substrate structure for composite semiconductor device
JPH06163862A (en) * 1992-11-27 1994-06-10 Nec Corp Soi substrate structure and its manufacture
JP2007273999A (en) * 1999-03-04 2007-10-18 Fuji Electric Device Technology Co Ltd Method for manufacturing semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4985745A (en) * 1988-01-05 1991-01-15 Kabushiki Kaisha Toshiba Substrate structure for composite semiconductor device
JPH06163862A (en) * 1992-11-27 1994-06-10 Nec Corp Soi substrate structure and its manufacture
JP2007273999A (en) * 1999-03-04 2007-10-18 Fuji Electric Device Technology Co Ltd Method for manufacturing semiconductor device

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