JPS5453869A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5453869A
JPS5453869A JP12039677A JP12039677A JPS5453869A JP S5453869 A JPS5453869 A JP S5453869A JP 12039677 A JP12039677 A JP 12039677A JP 12039677 A JP12039677 A JP 12039677A JP S5453869 A JPS5453869 A JP S5453869A
Authority
JP
Japan
Prior art keywords
regions
sio
diffused
film
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12039677A
Other languages
Japanese (ja)
Inventor
Reiji Takashina
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP12039677A priority Critical patent/JPS5453869A/en
Publication of JPS5453869A publication Critical patent/JPS5453869A/en
Pending legal-status Critical Current

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  • Bipolar Transistors (AREA)

Abstract

PURPOSE: To eliminate the need for stabilizing resistances provided on the outside of transistor regions and reduce floating capacities by forming the emitter region with a high impurity concentration region in the central part and the composite regions of a low impurity concentration region encircling this.
CONSTITUTION: After a SiO2 film 3 is deposited on a semiconductor substrate composed of an N- type layer 1A and N+ type layer 1B, windows are opened therein and boron is diffused to form P+ type base regions 2, after which thermal oxidation is applied. Next, the SiO2 films 4 and 3 having been formed are removed, and again boron is diffused to provide P- type active base regions 5, with the regions 2 in-between. Again thermal oxidation is prformed and windows are opened in the SiO2 film having been formed. Thereafter, arsenic is diffused to form an N- type emitter region 6 within the regions 6 encircled by the regions 2, and the surface is covered with a SiO2 film 8. Next, an opening is etched here, where phosphorus is diffused to form an N+ type emitter region 9 in the region 6, after which the surface is covered with a SiO2 film 10, and is windowed for electrode lead-out, where base and emitter electrodes 11, 12 are respectively mounted
COPYRIGHT: (C)1979,JPO&Japio
JP12039677A 1977-10-05 1977-10-05 Semiconductor device Pending JPS5453869A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12039677A JPS5453869A (en) 1977-10-05 1977-10-05 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12039677A JPS5453869A (en) 1977-10-05 1977-10-05 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5453869A true JPS5453869A (en) 1979-04-27

Family

ID=14785163

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12039677A Pending JPS5453869A (en) 1977-10-05 1977-10-05 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5453869A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6119171A (en) * 1984-06-29 1986-01-28 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Vertical npn transistor structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6119171A (en) * 1984-06-29 1986-01-28 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Vertical npn transistor structure

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