JPS5640256A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5640256A
JPS5640256A JP11769979A JP11769979A JPS5640256A JP S5640256 A JPS5640256 A JP S5640256A JP 11769979 A JP11769979 A JP 11769979A JP 11769979 A JP11769979 A JP 11769979A JP S5640256 A JPS5640256 A JP S5640256A
Authority
JP
Japan
Prior art keywords
layer
collector
type
ion implantation
base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11769979A
Other languages
Japanese (ja)
Other versions
JPS641933B2 (en
Inventor
Katsuhiro Tsukamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP11769979A priority Critical patent/JPS5640256A/en
Publication of JPS5640256A publication Critical patent/JPS5640256A/en
Publication of JPS641933B2 publication Critical patent/JPS641933B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H01L21/7621—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region the recessed region having a shape other than rectangular, e.g. rounded or oblique shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

PURPOSE:To prevent an increase in junction capacity across base and collector by surrounding the circumference of an n type buried collector on a p type substrate with a p layer wherein an n opitaxial layer is grown and the occurrence of a layer fault is controlled by selectively forming an oxide film on the upper part of the p layer around the buried layer. CONSTITUTION:An n<+> buried collector 2 is nade on a p type Si substrate and a p<+> layer 16 is made around the collector 2 by ion implantation. An n epitaxial layer is placed on the collector 2 and the p<+> layer 16. And photo etching is applied as far as a predetermined depth by a two-layer mask of SiO2 4 and Si3N4 5 and an n layer 3b is formed. Next, selective ion implantation is applied to the n layer 3b to form a p<+> layer 3c and an SiO2 isolating layer 7 is formed by oxidation in O2 at high temperature. Next, the mask 6 is removed. Then, a p base 9 and an n<+> emitter 10 are provided in a normal process to form electrodes. In this composition, the interface between the isolating layer 7 and the p<+> layer 16 will not be converted into n type because of the high concentration of the p<+> layer 16 and the n layer 3b minimizes the amount of ion implantation. Therefore, a layer fault occurs infrequently. In this way, high speed operation will be attempted without increasing junction capacity across base and collector.
JP11769979A 1979-09-11 1979-09-11 Manufacture of semiconductor device Granted JPS5640256A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11769979A JPS5640256A (en) 1979-09-11 1979-09-11 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11769979A JPS5640256A (en) 1979-09-11 1979-09-11 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5640256A true JPS5640256A (en) 1981-04-16
JPS641933B2 JPS641933B2 (en) 1989-01-13

Family

ID=14718107

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11769979A Granted JPS5640256A (en) 1979-09-11 1979-09-11 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5640256A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58148325A (en) * 1982-02-28 1983-09-03 Matsushita Electric Works Ltd Floor heating device
JPS5990925A (en) * 1982-11-17 1984-05-25 Matsushita Electronics Corp Manufacture of semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53117988A (en) * 1977-03-25 1978-10-14 Hitachi Ltd Production of bipolar ic

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53117988A (en) * 1977-03-25 1978-10-14 Hitachi Ltd Production of bipolar ic

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58148325A (en) * 1982-02-28 1983-09-03 Matsushita Electric Works Ltd Floor heating device
JPS5990925A (en) * 1982-11-17 1984-05-25 Matsushita Electronics Corp Manufacture of semiconductor device

Also Published As

Publication number Publication date
JPS641933B2 (en) 1989-01-13

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