JPS57134956A - Manufacture of semiconductor integrated circuit - Google Patents
Manufacture of semiconductor integrated circuitInfo
- Publication number
- JPS57134956A JPS57134956A JP2035181A JP2035181A JPS57134956A JP S57134956 A JPS57134956 A JP S57134956A JP 2035181 A JP2035181 A JP 2035181A JP 2035181 A JP2035181 A JP 2035181A JP S57134956 A JPS57134956 A JP S57134956A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- type
- emitter
- integrated circuit
- diffusion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
- 238000009792 diffusion process Methods 0.000 abstract 3
- 238000005468 ion implantation Methods 0.000 abstract 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 2
- 238000005530 etching Methods 0.000 abstract 1
- 239000012535 impurity Substances 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 238000007254 oxidation reaction Methods 0.000 abstract 1
- 230000001590 oxidative effect Effects 0.000 abstract 1
- 239000007790 solid phase Substances 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
- 238000007669 thermal treatment Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Transistors (AREA)
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
PURPOSE:To eliminate the primary factor of an unstable threshold voltage and improve the controllability of hFE by a method wherein after gate oxide film of a BI-MOS integrated circuit is formed, an emitter layer is formed by diffusing impurity from polycrystalline Si. CONSTITUTION:An N<+> type buried layer 2 and N type epitaxial layers 3a and 3b are formed on a P type Si substrate 1. Then a P type base layer 8 is formed by ion-implantation and separated regions 5 are formed by selective oxidization. Then, after gate oxide film 14 and diffusion mask are formed by oxidizing the surface, a doped polycrystalline silicon layer is formed on the whole surface and a gate electrode 21c and an emitter diffusion layer 21a are formed by etching. Then, after a source 9a, a drain 10a and a base layer 8a and so forth are formed by ion-implantation, an emitter region 3a1 is formed by solid phase diffusion by thermal treatment. With this constitution, the threshold voltage can be made stable and the controllability of hFE can be improved.
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2035181A JPS6052591B2 (en) | 1981-02-14 | 1981-02-14 | Method for manufacturing semiconductor integrated circuit device |
US06/348,541 US4445268A (en) | 1981-02-14 | 1982-02-12 | Method of manufacturing a semiconductor integrated circuit BI-MOS device |
DE19823205022 DE3205022A1 (en) | 1981-02-14 | 1982-02-12 | METHOD FOR PRODUCING AN INTEGRATED SEMICONDUCTOR CIRCUIT |
US06/478,590 US4486942A (en) | 1981-02-14 | 1983-03-24 | Method of manufacturing semiconductor integrated circuit BI-MOS device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2035181A JPS6052591B2 (en) | 1981-02-14 | 1981-02-14 | Method for manufacturing semiconductor integrated circuit device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57134956A true JPS57134956A (en) | 1982-08-20 |
JPS6052591B2 JPS6052591B2 (en) | 1985-11-20 |
Family
ID=12024695
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2035181A Expired JPS6052591B2 (en) | 1981-02-14 | 1981-02-14 | Method for manufacturing semiconductor integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6052591B2 (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6072255A (en) * | 1983-09-28 | 1985-04-24 | Toshiba Corp | Semiconductor ic device and manufacture thereof |
JPS6080267A (en) * | 1983-10-07 | 1985-05-08 | Toshiba Corp | Semiconductor ic device and manufacture thereof |
JPS60217657A (en) * | 1984-04-12 | 1985-10-31 | Mitsubishi Electric Corp | Manufacture of semiconductor integrated circuit device |
JPS61139057A (en) * | 1984-12-11 | 1986-06-26 | Toshiba Corp | Manufacture of semiconductor integrated circuit device |
JPS61206250A (en) * | 1985-03-08 | 1986-09-12 | Toshiba Corp | Semiconductor integrated circuit device |
-
1981
- 1981-02-14 JP JP2035181A patent/JPS6052591B2/en not_active Expired
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6072255A (en) * | 1983-09-28 | 1985-04-24 | Toshiba Corp | Semiconductor ic device and manufacture thereof |
JPH0148661B2 (en) * | 1983-09-28 | 1989-10-20 | Tokyo Shibaura Electric Co | |
JPS6080267A (en) * | 1983-10-07 | 1985-05-08 | Toshiba Corp | Semiconductor ic device and manufacture thereof |
JPH0315346B2 (en) * | 1983-10-07 | 1991-02-28 | Tokyo Shibaura Electric Co | |
JPS60217657A (en) * | 1984-04-12 | 1985-10-31 | Mitsubishi Electric Corp | Manufacture of semiconductor integrated circuit device |
JPS61139057A (en) * | 1984-12-11 | 1986-06-26 | Toshiba Corp | Manufacture of semiconductor integrated circuit device |
JPH0369179B2 (en) * | 1984-12-11 | 1991-10-31 | Tokyo Shibaura Electric Co | |
JPS61206250A (en) * | 1985-03-08 | 1986-09-12 | Toshiba Corp | Semiconductor integrated circuit device |
JPH0350422B2 (en) * | 1985-03-08 | 1991-08-01 | Tokyo Shibaura Electric Co |
Also Published As
Publication number | Publication date |
---|---|
JPS6052591B2 (en) | 1985-11-20 |
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