JPH0369179B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention combines a polycrystalline silicon gate complementary MOS transistor with excellent high-speed characteristics and a low power consumption bipolar transistor with a high cut-off frequency on the same chip. The present invention relates to an improvement in a method for manufacturing a semiconductor integrated circuit device that coexists within a semiconductor integrated circuit device.

[Technical background of the invention]

Semiconductor integrated circuits in which bipolar transistors and complementary MOS transistors (hereinafter referred to as CMOS) coexist on the same semiconductor substrate are generally
Referred to as Bi-CMOS, it is a relatively new semiconductor integrated circuit device (IC) that was introduced to meet the demand for coexistence of analog and digital functions within the same chip.

Incidentally, the process for manufacturing bipolar semiconductor devices and the process for manufacturing CMOS have been developed independently, and both are manufactured using unique processes suitable for their respective structures. Therefore, when manufacturing the above-mentioned Bi-CMOS by combining bipolar process and CMOS process, it is difficult to satisfy the characteristics of both bipolar transistor and CMOS. Achieving characteristics similar to those of electric power is extremely difficult. Therefore, in order to meet such demands, the applicant filed a patent application for a method for manufacturing Bi-CMOS having the structure shown in FIG. 2, for example.
It was previously proposed as No. 108069.

As described below, the basic idea of the above method proposed by the applicant is included in the present invention as it is,
The main points will be explained in accordance with the structure shown in FIG. 2 as follows.

The first point is to separate the element regions of the CMOS and bipolar transistors by the combination of the P-type substrate 11, the N ⁺ type buried regions 12 ₁ , 12 ₂ , and the N-type well regions 14 ₁ , 14 ₂ . . That is,
By employing the ^N type well regions 14 ₁ and 14 ₂ in contact with the N + type buried regions 12 ₁ and 12 ₂ , the heat treatment time for forming the N well can be shortened, and the N ⁺
It is possible to prevent impurities from diffusing upward from the mold buried region and changing the impurity concentration in the N well region. Therefore, the characteristics of the NPN transistor formed using the N well 14 ₁ as the collector region can be improved, and the characteristics of the P channel formed in the N well region 14 ₂ can be improved.
The threshold voltage of MOS transistors can be stabilized.

The second point is to separate the formation of the N ⁺ type emitter region 36 of the NPN transistor from the formation of the N ⁺ type source and drain regions 38, 38' of the N channel MOS transistor in CMOS, and to separate the formation of the N ⁺ type emitter region 36 of the NPN transistor. is to form by thermal diffusion using the extraction electrode 33 made of a polycrystalline silicon layer as a diffusion source. As a result, N ⁺ type emitter region 3
6 is made shallow to give the NPN transistor high cut-off frequency characteristics and low power consumption characteristics, and at the same time, the source and drain regions 38 and 38' of the N-channel MOS transistor are made sufficiently large to prevent electrode penetration when forming the aluminum electrode. It becomes possible to form the film with a diffusion depth that is as large as possible.

[Problems with background technology]

However, the above conventional Bi-
The CMOS manufacturing method includes the steps shown in FIGS. 3A and 3B, and the following problems have arisen at that time.

FIG. 3A shows a stage in which an N ⁺ type emitter region 36 of an NPN transistor is formed using an extraction electrode 33 made of arsenic-doped polycrystalline silicon as a diffusion source. From this state, the CMOS N-channel MOS transistor portion is covered with a resist pattern 26, as shown in FIG. 3B. Next, using the resist pattern 26, field oxide film 20, gate electrode 31, emitter lead-out electrode 33, and collector lead-out electrode 34 as a blocking mask, ions are implanted over the entire surface to form the P ⁺ type source region and drain region of the P channel MOS transistor. 39, 39' and are formed in self-alignment with the P ⁺ type external base region 40 of the NPN transistor. In addition,
The gate electrode 31 and the lead-out electrodes 33 and 34 are all formed of a polycrystalline silicon layer, and an oxide film 37 is formed on the surface thereof.

However, the oxide film 37 covering each electrode is formed by thermally oxidizing the surface of these polycrystalline silicon patterns, and since it is necessary to keep the ρ _s of these electrodes small, it cannot be made that thick. Boron is also injected into 33. The boron thus implanted into the emitter extraction electrode 33 is diffused into the N ⁺ type emitter region 36 during subsequent heat treatment, resulting in the problem that the desired current amplification factor cannot be obtained in the NPN transistor. .

[Purpose of the invention]

The present invention has been made in view of the above-mentioned circumstances, and improves the conventional Bi-CMOS manufacturing method proposed by the applicant in the previous application. The present invention provides a method for manufacturing a semiconductor device that can solve the problems described above and obtain a desired current amplification factor in a bipolar transistor.

[Summary of the invention]

A method for manufacturing a semiconductor device according to the present invention includes selectively forming a plurality of second conductivity type high concentration buried regions in a surface layer of a first conductivity type semiconductor substrate, and then forming a first conductivity type high concentration buried region covering a main surface of the semiconductor substrate. a step of growing an epitaxial semiconductor layer, and a second step of selectively diffusing second conductivity type impurities from the surface of the epitaxial semiconductor layer to reach each of the plurality of second conductivity type high concentration buried regions. By forming a conductive well region and selectively forming a field oxide film on the surface of the epitaxial semiconductor layer,
forming a first conductivity type element region and a second conductivity type element region surrounded by the field oxide film;
By covering the surfaces of all these device regions with a thin insulating film to serve as a gate insulating film and selectively doping first conductivity type impurities into some of the second conductivity type device regions, the first conductivity of the bipolar transistor is forming an active base region of conductivity type; forming an emitter diffusion window in the thin insulating film covering the active base region; selectively forming a first resist pattern on the polycrystalline silicon layer, and selectively etching the polycrystalline silicon layer using the first resist pattern as a mask. A gate electrode of an insulated gate field effect transistor is formed via the thin oxide film on the second conductivity type element region and the first conductivity type element region where the active base region is not formed, and the active base region is A step of forming an emitter extraction electrode in contact with the active base region through the emitter diffusion window on the formed second conductivity type element region, and a step of forming the emitter lead-out electrode on the formed second conductivity type element region without removing the first resist pattern. forming a second conductivity type element region in which no active base region is formed and a second resist pattern having an opening on the active base region; and blocking the first and second resist patterns. By ion-implanting impurities of the first conductivity type as a mask, a high concentration external base region of the same conductivity type is formed in the active base region in a self-aligned manner, and at the same time, a high concentration external base region of the second conductivity type where the active base region is not formed is formed. In the device region, there is a step of forming self-aligned first conductivity type source and drain regions on both sides of the gate electrode, and after removing the first and second resist patterns, the emitter lead-out electrode is formed as a diffusion source. forming an emitter region of a second conductivity type in the active base region of the first conductivity type by thermally diffusing impurities; The present invention is characterized by comprising a step of doping a second conductivity type impurity to form self-aligned second conductivity type source and drain regions on both sides of the gate electrode.

The manufacturing method according to the present invention includes forming the second resist pattern without removing the first resist pattern, and using these resist patterns as a blocking mask for ion implantation when forming the external base region. This solves the problem explained in FIGS. 3A and 3B. The other configurations are basically the same as the previous manufacturing method proposed by the applicant, and have the same effects as the prior invention.

[Embodiments of the invention]

Hereinafter, with reference to FIGS. 1 A to I, according to the present invention
An example of a method for manufacturing Bi-CMOS will be described.

(1) First, as shown in Figure 1A, the substrate concentration is 10 ¹⁴ ~
After forming an insulating film for diffusion, such as a thermal oxide film, on a P-type silicon substrate 11 of about 10 ¹⁷ cm ^-3 and patterning the necessary parts, antimony (Sb) or arsenic (As) is applied using this as a diffusion mask. )
are selectively diffused and have an ^impurity concentration of 10 ¹⁸ to ₁₀ ² /cm ² .
form ₂ . Subsequently, after removing the above insulating film, a P-type epitaxial layer 1 is deposited on the entire surface of the wafer.
3 is deposited and formed. The P-type epitaxial layer 1
The thickness of 3 is 1 to 5 μm, and the specific resistance is 0.5 to 10 Ω.
cm. However, this is a fixed standard and is a value that should naturally be changed depending on the specific conditions of the element. Next, N-well regions 14 ₁ and 14 ₂ are formed as a bipolar transistor formation region and a PMOSFET formation region, respectively, in the following manner. First, the surface of the wafer is thermally oxidized to form a thermal oxide film 15 having a thickness of 500 to 1000 Å, and after forming a diffusion source by implanting phosphorus ions, thermal diffusion is performed. For example, if ion implantation of phosphorus is performed at a dose of 2×10 ¹² and an acceleration voltage of 150 keV, and the subsequent thermal process diffuses it to a depth of about 1 to 3 μm, the surface impurity concentration will be 8 to 10 μm.
An N-well region of ×10 ¹⁵ cm ^-3 is formed. This thermal diffusion may be performed using a high temperature thermal process of 1000° C. or higher. At that time, N ⁺ type buried regions 12 ₁ , 12
Since upward diffusion of impurities using N well regions 14 ₁ and 14 2 occurs at the same time, the diffusion length (i.e., diffusion time) required to form N well regions 14 1 and 14 ₂ is shortened, and N wells can be _easily formed. .

(2) Next, define the element region as shown in FIG. 1B. First, the surface of the P-type epitaxial layer 13 is thermally oxidized to form a thermal oxide film 16 with a thickness of 300 to 2000 Å, and then, for example, by CVD method.
An oxidation-resistant insulating film 17 made of Si ₃ N ₄ or the like is approximately 1000 Å thick.
Only layered and deposited. Subsequently, this laminated film 16,1
7 is patterned, and the laminated film is left only in the area where the element is to be formed. Thereafter, if necessary, boron or phosphorus ions are implanted using the laminated films 16 and 17 as masks to form channel cuts 18 and 19.

(3) Next, selective oxidation is performed using the oxidation-resistant insulating film 17 as a mask to form a field oxide film 20 with a thickness of approximately 0.7 to 1.2 μm as shown in FIG. A P-type element region and an N-type element region are separately formed. Subsequently, after removing the laminated films 16 and 17 to expose the surface of the element region, the surface of the element region is thermally oxidized again to form a thermal oxide film 21 with a thickness of 200 to 1000 Å, which will become the gate oxide film of the MOS transistor. form.

Note that the reason why the thick insulating isolation film 20' is formed also in the element region (N-well region 12 ₁ ) for the bipolar transistor is to form a bipolar transistor having a wall base structure.

(4) Next, boron ions are selectively implanted into the bipolar transistor element region to form a P-type active base region (internal base region of draft base structure) 23 as shown in FIG. 1D. This ion implantation is carried out by masking unnecessary parts with a resist pattern and by masking the field oxide film 20 and insulating isolation film 20' in the bipolar transistor part.
is used as a blocking mask. Ion implantation followed by annealing or as required
Diffusion slumping is performed at a temperature of 1000 to 1100° C. to obtain an active base region 23 having a sheet resistance ρs of approximately 500 to 1000 Ω/□. After that, channel ion implantation 24,2 to control the threshold voltage of PMOSFET and NMOSFET as required.
Apply 5.

(5) Next, as shown in FIG. 1E, an N ⁺ type collector contact region 27 is formed and a polycrystalline silicon layer 28 is deposited as an electrode material. This is done as follows.

First, the emitter diffusion window 29 ₁ and collector diffusion window 29 ₂ of the bipolar transistor are opened in the thermal oxide film 21 covering the surface of each element region. Next, undoped Si was deposited by CVD method,
An undoped polycrystalline silicon layer 28 having a thickness of 2000 to 6000 Å is formed. Furthermore, after forming a CVD-SiO ₂ film 30 with a thickness of about 5000 Å, the collector diffusion window 29 ₂ of the bipolar transistor is formed.
Covers over PMOSFET and NMOSFET parts
The CVD-SiO ₂ film 30 is selectively removed. Next, by using the remaining CVD-SiO ₂ film 30 as a mask and using POCl ₃ as a diffusion source to selectively diffuse highly concentrated phosphorus into the polycrystalline silicon layer 28, its sheet resistance (ρs) is reduced to ρs. ==20Ω／□
to a certain extent. At this time, since the diffusion coefficient in the polycrystalline silicon layer is large, the highly concentrated phosphorous penetrates through the polycrystalline silicon layer 28 and is diffused into the epitaxial layer via the collector diffusion window ₂₉₂ . As _a result, N ⁺
An N ⁺ type collector contact region 27 reaching the type buried region 12 ₁ is formed. In addition, the above POCl ₃
The concentration setting and thermal process are performed so that the N ⁺ type region collector contact region 27 sufficiently reaches the N ⁺ type buried region 12 ₁ .

Next, after removing the CVD-SiO ₂ film 30 that had masked the bipolar transistor part by the above-mentioned phosphorus diffusion, only the masked part was
Alternatively, the entire polycrystalline silicon layer 28 is doped with arsenic. When doping arsenic, for example, ions are implanted at a dose of 5 to 20×10 ¹⁵ cm ⁻² and an acceleration voltage of 150 keV, and then annealing is performed to equalize the arsenic concentration in the polycrystalline silicon layer. As a result, the bipolar transistor portion is doped only with arsenic, and the other portions are formed with a polycrystalline silicon layer 28 doped with only phosphorus or with phosphorus and arsenic. Alternatively, a polycrystalline silicon layer 2 doped with arsenic
After depositing 8 on the entire surface, it is also possible to perform high concentration diffusion of phosphorus by masking the bipolar transistor portion in the same manner as described above.

(6) Next, first resist patterns 51 ₁ to 51 ₄ are selectively formed on the polycrystalline silicon layer 28 formed as described above, and using the first resist patterns as a mask, the polycrystalline silicon layer is By patterning 28, CMOS gate electrodes 31 and 32, an emitter lead electrode 33 and a collector lead electrode 34 of a bipolar transistor are formed as shown in FIG. 4F.

(7) Next, as shown in FIG. 1G, without removing the first resist patterns 51 ₁ to 51 ₄ , an opening is formed over the PMOSFET portion and the active base region 23 of the bipolar transistor. A second resist pattern 52 is formed. Subsequently, the second resist pattern 5
2, by implanting boron ions using the first resist pattern and the exposed portion of the field oxide film as a blocking mask,
P ⁺ type source and drain regions 39, 39' are formed in the PMOSFET part by self-alignment, and at the same time, P ⁺ type sources and drain regions 39, 39' are formed in the bipolar transistor part.
The external base region 40 of the mold is formed in self-alignment.

Note that the first resist patterns 51 ₁ to 51 ₄
By curing the material in advance by irradiating it with ultraviolet rays or the like, the blocking effect against boron ion implantation can be further improved.

(8) Next, first and second resist patterns 5
After removing 1 ₁ to 51 ₄ and 52, from now on
Protect the PMOSFET part and bipolar transistor part with a resist pattern,
Phosphorus ions are selectively implanted into the NMOSFET portion. As a result, N ⁺ type source and drain regions 38 and 38' are formed in a self-aligned manner using the gate electrode 32 and field oxide film 20 as a blocking mask. Subsequently, the resist pattern is removed and heat treatment is performed to diffuse arsenic using the emitter electrode 33 as a diffusion source, forming an N ⁺ type emitter region 36 with a shallow junction to ensure a high current amplification factor of the bipolar transistor. . Thereafter, the surfaces of the various polycrystalline silicon electrodes 31 to 34 are thermally oxidized to form an oxide film 37 (as shown in FIG. 1H).

(9) After that, as shown in FIG. 1I, after adding passivation films 41 and 42 such as PSG film (phosphorus-doped silicate glass film) or BPSG film (boron and phosphorus-doped silicate glass film), each element is By opening the contact portions and performing vapor deposition and patterning of electrode metal to form various electrodes 43, a semiconductor integrated circuit device in which bipolar transistors and CMOS coexist is completed.

According to the manufacturing method of the above embodiment, a high-speed performance CMOS and a high cut-off frequency (r=3 to 6 GHz), low power consumption, and low noise bipolar transistor can coexist in a relatively simple process. In the bipolar transistor portion, since diffusion of arsenic from polycrystalline silicon is used to form the emitter region 36, a high current amplification factor can be ensured with a shallow junction. In addition, N ⁺ formed by diffusion from a polycrystalline silicon layer containing a high concentration of phosphorus
Due to the presence of the type collector contact region 27,
Because it is possible to reduce the collector resistance of a bipolar transistor and lower its on-resistance,
As a result, the present invention still has the advantages of the conventional manufacturing method proposed by the applicant, such as being able to suppress the saturation voltage of the bipolar transistor to a low level.

Moreover, as is clear from the explanation with respect to FIGS. 1F and 1G, the manufacturing method of the above embodiment prevents boron from being introduced into the emitter region 36 when forming the external base region 40. Therefore, it is possible to ensure the desired current amplification factor for the bipolar transistor formed in the same substrate as the CMOS.

〔Effect of the invention〕

As detailed above, the method for manufacturing a semiconductor device according to the present invention, similar to the conventional manufacturing method proposed earlier by the applicant, uses a CMOS with excellent high-speed operation characteristics and a bipolar transistor with a high cut-off frequency. They can be manufactured together in a simple process, solve problems in conventional manufacturing methods, and have remarkable effects such as being able to obtain a stable and desired current amplification factor in bipolar transistors.

[Brief explanation of drawings]

Figures A to I are Bi-
2 and 3 A and B are cross-sectional views showing a method for manufacturing a CMOS semiconductor integrated circuit device in the order of steps, for explaining the conventional method for manufacturing a semiconductor integrated circuit device proposed by the present applicant and its problems. FIG. 11...P-type silicon substrate, 12 ₁ , 12 ₂ ...
N ⁺ type buried region, 13...P type epitaxial layer,
14 ₁ , 14 ₂ ... N well region, 20 ... Field oxide film, 21 ... Gate oxide film, 23 ... P
type active base region, 27...N ⁺ type collector contact region, 28... polycrystalline silicon layer, 29 ₁
~29 ₃ ...Diffusion window, 31, 32...Gate electrode,
33... Emitter electrode, 34... Collector extraction electrode, 36... N ⁺ type emitter extraction electrode, 38,
38'...N ⁺ type source and drain region, 39,
39'...P ⁺ type source and drain region, 40...
... P ⁺ type external base region, 41, 42 ... Passivation film, 43 ... Metal electrode, 26, 51
₁ to 51 ₂ ...Resist pattern.

Claims (1)

[Claims] 1. After selectively forming a plurality of second conductivity type high concentration buried regions in the surface layer of a first conductivity type semiconductor substrate, growing an epitaxial semiconductor layer of a first conductivity type covering the main surface of the semiconductor substrate. and forming a second conductivity type well region reaching each of the plurality of second conductivity type high concentration buried regions by selectively diffusing a second conductivity type impurity from the surface of the epitaxial semiconductor layer. , forming a first conductivity type element region and a second conductivity type element region surrounded by the field oxide film by selectively forming a field oxide film on the surface of the epitaxial semiconductor layer; The first conductivity type of the bipolar transistor is activated by covering the surface of the device region with a thin insulating film to serve as a gate insulating film and selectively doping first conductivity type impurities into a portion of the second conductivity type device region. a step of forming a base region, a step of opening an emitter diffusion window in the thin insulating film covering the active base region, and a step of forming a polycrystalline silicon layer doped with a second conductivity type impurity at a high concentration on the element region. selectively forming a first resist pattern on the polycrystalline silicon layer;
By selectively etching the polycrystalline silicon layer using the first resist pattern as a mask, the thin layer is etched onto the second conductivity type device region and the first conductivity type device region where the active base region is not formed. In addition to forming the gate electrode of an insulated gate field effect transistor through an oxide film,
a step of forming an emitter extraction electrode in contact with the active base region through the emitter diffusion window on the second conductivity type element region in which the active base region is formed; forming a second conductive type element region on which the active base region is not formed and a second resist pattern having an opening on the active base region; First, use the pattern as a blocking mask.
By ion-implanting conductivity type impurities, a high concentration external base region of the same conductivity type is formed in the active base region in a self-aligned manner, and at the same time, a second conductivity type element region where the active base region is not formed is formed with a high concentration external base region of the same conductivity type. After forming self-aligned first conductivity type source and drain regions on both sides of the gate electrode and removing the first and second resist patterns, heat of impurities is removed using the emitter extraction electrode as a diffusion source. forming an emitter region of a second conductivity type in the active base region of the first conductivity type by performing diffusion; and applying an impurity of a second conductivity type to the device region of the first conductivity type using the gate electrode as a blocking mask; A method for manufacturing a semiconductor integrated circuit device, comprising the step of forming self-aligned source and drain regions of a second conductivity type on both sides of the gate electrode by doping.