JP3121629B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, particularly a semiconductor device in which a bipolar transistor (NPN transistor) is formed on the same substrate together with a MOS transistor and the like.

[0002]

2. Description of the Related Art As a conventional example of the above-mentioned semiconductor device, for example, a document "1989 Symposium on VSI Technology (1989 Symposium)"
ONVLSI TECHNOLOGY) P37-P3
8 ". A conventional method for manufacturing such a semiconductor device will be described with reference to FIGS. Here, the NPN Tr, the CMOS Tr, and the EPROM are formed on the same substrate.

[0003] First, as shown in FIG.
The P-type Si substrate 1 of about Ω · cm 1000 ℃ 20 minutes, O ₂
Heat treatment is performed in an atmosphere to form a SiO ₂ film 2 of about 450 °.

Next, by photolithography technology,
A resist 3 is formed in a region other than the NPN Tr formation region 5 and the PMOS Tr formation region 6.

[0005] Next, Sb 4 is accelerated by an ion implantation technique at an acceleration voltage of 40 KeV and a dose of 3 × 10 4
Ion implantation is performed under the condition of ¹⁵ ions / cm ² to introduce Sb 4 into the P-type Si substrate 1 in the NPN Tr formation region 5 and the PMOS Tr formation region 6.

Next, as shown in FIG. 7B, the resist 3 is removed, and heat treatment is performed at 1200 ° C. for 500 minutes in an N ₂ atmosphere to obtain a sheet resistance of 30Ω / □ and a junction depth of 4.5 μm.
An N ⁺ buried layer 7 of about m is formed, and the SiO ₂ film 2 is removed.

Next, as shown in FIG. 7C, a P-type epitaxial layer 8 having a specific resistance of 2 Ω · cm and a thickness of about 12 μm is formed by an epitaxial technique.

Then, oxidation is performed at 1,000 ° C. for about 5 minutes in a steam atmosphere by an oxidation technique, and the
An O ₂ film 9 is formed.

Next, by photolithography technology,
A resist 10 is formed in a region other than the NPN Tr formation region 5 and the PMOS Tr formation region 6.

Next, P (phosphorus) 11 is ion-implanted at an acceleration voltage of 100 KeV and a dose of about 2 × 10 ¹³ ions / cm ^{2 by} ion implantation technology, and the P-type of the NPN Tr forming region 5 and the PMOS Tr forming region 6 Phosphorus 11 is introduced into the epitaxial layer 8.

Next, as shown in FIG. 8A, the resist 10 is removed. Then, at 1200 ° C. 120 in N ₂ atmosphere.
By performing a heat treatment for about 0 minutes, a sheet resistance of 800
An N-well layer 12 of Ω / □ and a junction depth of about 6 μm is formed and connected to the N ⁺ buried layer 7. Next, the SiO ₂ film 9 is removed.

Next, oxidation is performed at 950 ° C. for about 50 minutes in an O ₂ atmosphere to form a SiO ₂ film 13 of about 300 ° C.
A Si ₃ N ₄ film 14 is formed to a thickness of about 2000 ° by the CVD technique.

Next, as shown in FIG. 8B, the Si ₃ N ₄ film 1 in the element isolation region 15 is formed by photolithography.
4 is removed.

Next, as shown in FIG. 8C, oxidation is performed at 1000 ° C. for about 200 minutes in a steam atmosphere,
An isolation oxide film 16 of about 00 ° is formed, and the Si ₃ N ₄ film 14 is removed.

Next, as shown in FIG. 8D, a resist 17 is formed by photolithography in a region other than the control gate forming region 18 of the EPROM.

Next, phosphorus 20 is accelerated by an ion implantation technique at an acceleration voltage of 60 KeV and a dose of 1 × 1.
Ion implantation is performed under conditions of about 0 ¹⁵ ions / cm ² , and phosphorus 20 is added to the control gate formation region 18.
Is introduced.

Next, as shown in FIG. 9A, the resist 17 is removed, and a heat treatment is performed at 1100 ° C. for 120 minutes in an N ₂ atmosphere to obtain a control gate having a ρs of 60Ω / □ and a junction depth of about 2 μm. 21 are formed.

Next, as shown in FIG. 9B, the SiO ₂ film 13 is removed by etching, and then oxidized at 850 ° C. for about 30 minutes in a steam atmosphere to form a gate oxide film 23 at about 350 °. I do.

Next, NPNT is formed by photolithography.
A resist 24 is formed in a region other than the base formation region 25 of r.

Next, B (boron) 26 is accelerated by an ion implantation method at an acceleration voltage of 40 KeV and a dose of 1
Ion implantation is performed under conditions of about × 10 ¹⁴ ions / cm ² , and boron 26 is introduced into the base formation region 25 of NPNTr.

Next, as shown in FIG. 9C, the resist 24 is removed, and a heat treatment at 1000 ° C. for about 30 minutes is performed in an N ₂ atmosphere, so that ρs 500 Ω / □, junction depth
A base 27 of about 0.8 μm is formed.

Next, the polysilicon 2 is formed by the CVD method.
8 is formed at about 2000 °.

Next, by a thermal diffusion method using POCl ₃ ,
Phosphorus is diffused to form a phosphorus-doped polysilicon 28 of about ρs20Ω / □.

Next, as shown in FIG. 9D, the polysilicon 28 is processed by the photolithographic etching technique.
The gate electrode 2 of the PMOSTr is formed in the PMOSTr formation region 6.
9, a gate electrode 31 of the NMOS Tr in the NMOS Tr formation region 30, and a floating gate 33 in the EPROM formation region 32. The dotted line portion of the floating gate 33 indicates that the left and right gates of the dotted line are connected.

Next, as shown in FIG. 10A, the EPRO excluding the collector electrode take-out region 19, the emitter formation region 34, the NMOS Tr formation region 30, and the control gate formation region 18 of the NPN Tr is formed by the photolithography technique.
A resist 46 is formed in a region other than the M formation region 32.

Next, As (arsenic) 35 is ion-implanted at an acceleration voltage of 40 KeV and a dose of about 1 × 10 ¹⁶ ions / cm ^{2 by} ion implantation, and As 3 is deposited in a region not covered with the resist 46.
5 is introduced.

Next, as shown in FIG. 10B, the resist 46 is removed, and a heat treatment is performed at 950 ° C. for about 100 minutes in an N ₂ atmosphere to obtain a sheet resistance of 35 Ω / □ and a diffusion depth of 0.3 μm.
By forming a diffusion layer of about m, the source 36 and the drain 37 in the EPROM formation region 32, the source 38 and the drain 39 in the NMOS Tr formation region 30, the emitter 40 in the NPN Tr formation region 5, and the N ⁺ for collecting the collector electrode.
The layer 41 is formed.

Next, as shown in FIG. 10C, a resist 42 is formed in a region other than the PMOS Tr forming region 6 by a photolithography technique.

Then, BF ₂ 43 was accelerated by an ion implantation method at an acceleration voltage of 40 KeV and a dose of 1 × 10 4
Perform ion implantation of about ¹⁶ ions / cm ² ,
Boron is introduced into the PMOS Tr formation region 6.

Next, as shown in FIG. 10 (d), the resist 42 is removed, and a heat treatment is performed at 900 ° C. for 20 minutes in an N ₂ atmosphere, ρs 150Ω / □, junction depth 0.25 μm
The source 44 and the drain 45 are formed in the PMOS Tr formation region 6 by forming a diffusion layer of a degree.

By performing the above steps, NPNTr
NPNTr is formed in the formation region 5, PMOSTr is formed in the PMOSTr formation region 6, and NMOSTr formation region 30 is formed.
The NMOS Tr and the EPRO in the EPROM formation area 32.
M are formed respectively.

At this time, the carrier concentration profile of the NPN transistor portion is as shown in FIG.
The distance from the lower part A of the base 27 to the upper part B of the N ⁺ buried layer 7 is about 5 μm. At this time, the concentration of the isolation region 47 of the NPN Tr (shown in FIG. 10D) remains at the concentration of 7 × 10 ¹⁵
about atoms / cc.

[0033]

However, in the above-described conventional manufacturing method, the upward diffusion of the N ⁺ buried layer 7 due to the heat treatment at the time of forming the N well layer 12 in FIG.
Degree, and as a result, the base 2 of the NPN transistor
There is a problem that the distance from the N ⁺ buried layer 7 to the N ⁺ buried layer 7 is about 5 μm, and a collector-base breakdown voltage of only about 10 to 20 V can be obtained.

It is conceivable to increase the thickness of the P-type epitaxial layer 8 in order to increase the collector-base breakdown voltage. In this case, however, the N-well layer 12 is added to the thickened P-type epitaxial layer 8. Since the amount of heat treatment increases to form the N ⁺ buried layer 7 and the upward diffusion increases, it is difficult to increase the breakdown voltage, and a collector-base breakdown voltage of 40 to 100 V in a driver such as a fluorescent display tube is obtained. I couldn't do that.

Further, in the above conventional manufacturing method, the NPN
The collector concentration of the transistor is about 1E16 atoms / cc, and the isolation region 4 of the NPN transistor is used.
Since the concentration of 7 is about 7E15 atoms / cc,
If a voltage is applied to the collector of the transistor, the isolation will punch through even at low voltages. If an attempt is made to increase the punch-through withstand voltage, the area of the isolation region 47 of the NPN transistor increases.
There is a drawback that the degree of integration is reduced.

In the above conventional manufacturing method, since the distance between the N ⁺ layer 41 for taking out the collector electrode and the N ⁺ buried layer 7 for lowering the collector resistance is large, the collector series resistance is reduced. There is a disadvantage that the saturation voltage of the NPN transistor increases and the speed decreases.

The present invention has the disadvantages that the breakdown voltage of the NPN transistor cannot be increased, the disadvantage that the breakdown voltage of the isolation is low, the disadvantage that the collector series resistance of the NPN transistor is high, the saturation voltage is large, and the speed is low. It is an object of the present invention to provide a method of manufacturing a semiconductor device capable of obtaining an NPN transistor having a high withstand voltage and a low collector series resistance and a high withstand voltage isolation.

[0038]

According to the present invention, an N-type epitaxial layer and a P-type epitaxial layer are formed on a P-type semiconductor substrate having an N-type buried layer, and only the P-type epitaxial layer in an NPN transistor formation region is formed. Next, an N-type well layer is formed.

When an N-type well layer is formed in the PMOS transistor formation region of the P-type epitaxial layer, a second N-type well layer is simultaneously formed in a region of the P-type epitaxial layer where the NPN transistor collector electrode is taken out. I do.

Further, a first P-type buried layer is formed on the surface of the substrate, and a second P-type buried layer is formed on the surface of the N-type epitaxial layer. , Said N
The isolation region of the NPN transistor is formed by being diffused up and down by heat treatment at the time of forming the mold well layer and penetrating the N-type epitaxial layer to be integrally connected.

[0041]

In the present invention, since the epitaxial layer has the two-layer structure of the N-type layer and the P-type layer, the N-type well layer of the NPN transistor is formed to have a depth corresponding to the thickness of the P-type epitaxial layer. It is only necessary to form the N-type buried layer, so that the amount of heat treatment at that time can be reduced.

Further, when the N-type well layer of the PMOS transistor part having a high concentration is formed, a second N-type well layer is simultaneously formed in the collector electrode take-out region of the NPN transistor to provide a deep collector layer. NPN
The collector series resistance of the transistor drops.

Further, the first and second P-type buried layers allow the NP
An isolation region for an N-transistor is formed. The first and second P-type buried layers are formed on the surface of the substrate and the N-type epitaxial layer, and these buried layers are diffused from both upper and lower directions to be integrated. Since the connection is made, the diffusion distance at this time can be short. In addition, the carrier concentration of the N-type epitaxial layer serving as the collector of the NPN transistor is about 1E15 atoms / cc. However, if the isolation region is formed as described above, the carrier concentration of the isolation region is at least 1E16 atoms / cc. And a density difference of about 10 times is obtained.

[0044]

An embodiment of the present invention will be described below with reference to the drawings. 1 to 4 are process sectional views showing an embodiment of the present invention. First, as shown in FIG.
A P-type Si substrate 51 having a thickness of about Ω · cm is prepared, and a protection oxide film 52 having a thickness of about 450 ° is formed on the surface of the substrate 51 at 1000 ° C. for 20 minutes in an O ₂ atmosphere by a known oxidation technique. Next, the substrate 51 other than the NPN Tr formation region 53 and the PMOS Tr formation region 54 is formed by a known photolithography technique.
A resist 55 is formed on the surface. Then, using the resist 55 as a mask, Sb (antimony) is accelerated by a known ion implantation technique at an acceleration voltage of 40 KeV and a dose of 3E15 ions / cm.
Ions are implanted into the substrate 51 under about ^two conditions.

Next, the resist 55 is removed, and drive-in is performed in an N ₂ atmosphere at 1200 ° C. for about 500 minutes, thereby forming the PMOST on the substrate 51 as shown in FIG.
N ⁺ buried layers 56 and 57 having a sheet resistance of 30Ω / □ and a junction depth of about 4.5 μm are formed on the surface of the r formation region and the surface of the NPN Tr formation region.

Next, by the known photolithography technique, FIG.
As shown in (c), a resist 59 is formed on the substrate 51 other than the isolation region 58 of the NPN Tr. Next, using the resist 59 as a mask, the isolation region 58 is used.
B (boron) is ion-implanted into the substrate portion at a condition of about 40 KeV and 2E14 ions / cm ² by a known ion implantation technique.

Next, the resist 59 is removed, and a heat treatment is performed in an N ₂ atmosphere at 1080 ° C. for about 60 minutes, so that a sheet resistance of 300 Ω / □ is applied to the surface of the isolation region of the substrate 51 as shown in FIG. A first P ⁺ buried layer 60 having a depth of about 1.5 μm is formed. Next, the protection oxide film 52 is removed.

Next, by the known epitaxial technology,
As shown in FIG. 1 (e), a specific resistance of 5Ω ·
An N-type epitaxial layer 61 having a thickness of about 9 μm and a thickness of about 9 μm is formed.

Then, 1000 is obtained by a known oxidation technique.
1000 ° C., 7 minutes, thickness 1000 mm under wet O ₂ atmosphere
As shown in FIG. 1 (f), the protection oxide film 62
It is formed on the surface of the type epitaxial layer 61. Next, a resist 63 is formed on the surface of the epitaxial layer 61 other than the isolation region 58 by a known photolithography technique. Then, using the resist 63 as a mask, B (boron) is implanted into the surface of the N-type epitaxial layer 61 in the isolation region 58 by a known ion implantation technique at 100 KeV and 1E.
Ions are implanted under conditions of about 13 ions / cm ² .

Next, the resist 63 is removed and 1000
Annealing at 20 ° C. for 20 minutes under N ₂
As shown in FIG. 1G, a second P ⁺ buried layer 64 having a sheet resistance of 2 KΩ / □ and a depth of about 1 μm is formed on the surface of the isolation region of the N-type epitaxial layer 61. Next, the protection oxide film 62 is removed.

Next, by a known epitaxial technique,
As shown in FIG. 2A, a P-type epitaxial layer 65 having a specific resistance of 20 Ω · cm and a thickness of about 3 μm is formed on the entire surface of the N-type epitaxial layer 61.

[0052] Then, by a known oxidation technique, 1000
1000 ° C., 7 minutes, thickness 1000 mm under wet O ₂ atmosphere
As shown in FIG. 2 (b), the protection oxide film 66 of about
It is formed on the surface of the type epitaxial layer 65. Next, a resist 67 is formed on the surface of the P-type epitaxial layer 65 other than the NPN Tr formation region 53 by a known photolithography technique. Then, using the resist 67 as a mask, P (phosphorus) is implanted into the P-type epitaxial layer 65 in the NPN Tr formation region 53 by a known ion implantation technique at 120 KeV and 7E11 ions.
/ Cm ² ions are implanted.

Next, the resist 67 is removed. Then, as shown in FIG. 2C, a resist 69 is formed on the surface of the P-type epitaxial layer 65 other than the PMOSTr formation region 54 and the NPNTr collector electrode extraction region 68 by a known photolithography technique. Then, using the resist 69 as a mask, P (phosphorus) is added to the P-type epitaxial layer 65 in the PMOS Tr forming region 54 and the collector electrode take-out region 68 by a known ion implantation technique at 150 KeV and 4.7E.
Ions are implanted under the conditions of 12 ions / cm ² . The order of the ion implantation and the ion implantation for the NPN Tr formation region 53 may be reversed.

Next, after the resist 69 is removed, drive-in is performed in an N ₂ atmosphere at 1200 ° C. for about 300 minutes. By this drive-in, the P-type epitaxial layer 65 is removed by the phosphorus impurity as shown in FIG.
N-type epitaxial layer 6
The first N-well layer 70 is formed so as to be connected to the first N-well layer 70. Further, second N-well layers 71 and 72 are formed in the PMOS Tr formation region of the P-type epitaxial layer 65 and the collector electrode extraction region of the NPN Tr. In addition, the N ⁺ buried layers 56 and 57
Spreads upward. Similarly, the first P ⁺ buried layer 60 and the second
P ⁺ buried layer 64 is also diffused in the vertical direction, and first P ⁺ buried layer 60 and second P ⁺ buried layer 64 are integrally connected through N-type epitaxial layer 61.

Next, as shown in FIG. 2E, the surface of the P-type epitaxial layer 65 and each of the well layers 70 to 72 is formed by a known oxidation technique under the conditions of 1000 ° C., 20 minutes and O _2. A pad oxide film 73 of about 450 ° is formed. Further, a known CVD technique and a photo-etching technique are used to form an active area and an NPN Tr.
A nitride film 74 having a thickness of about 1500 ° is formed in the isolation region.

Then, 1000 by a known oxidation technique.
By oxidizing at 120 ° C. for 120 minutes under the condition of wet O ₂ , as shown in FIG.
A field oxide film 75 of about 00 ° is formed. Next, the nitride film 74 is removed.

Next, as shown in FIG. 3B, a resist 77 is formed by a known photolithography technique, except for the base region 76 and the isolation region 58 of the NPN Tr. Next, using resist 77 as a mask, the base region and isolation region 5 of first N-well layer 70 are formed.
B (boron) is injected into the P-type epitaxial layer 65 of FIG. 8 by a known ion implantation technique at 40 KeV and 1.3E13 ions.
/ Cm ² ions are implanted.

Next, the resist 77 is removed, and annealing is performed in an N ₂ atmosphere at 1000 ° C. for 20 minutes, thereby isolating the inside of the first N-well layer 70 with the isolation, as shown in FIG. A P-type diffusion layer 78 as a base diffusion layer and an isolation layer is formed in the P-type epitaxial layer 65 in the region 58. Next, pad oxide film 7
3 is removed and the exposed surface is exposed to 85 by known oxidation techniques.
A first gate oxide film 79 having a thickness of about 300 ° is formed at 0 ° C. for 30 minutes under wet O ₂ conditions. Further over the floating gate of the EPROM and the NMOS by well-known CVD and photo-etch techniques.
A polysilicon electrode 80 having a thickness of about 3000 mm is formed on the gates of the Tr and PMOS Tr. Next, by a known oxidation technique, under the conditions of 950 ° C., 20 minutes, and O ₂ atmosphere,
A second gate oxide film 81 having a thickness of about 170 ° is formed on the surface of the polysilicon electrode 80 or the like. Then the known C
VD, a polysilicon electrode 8 having a thickness of about 2000 mm is formed on the control gate portion of the EPROM by photoetching technology.
Form 2 Then, 950 is obtained by a known oxidation technique.
° C., 25 minutes, O at ₂ atmosphere conditions, the thickness of about 200Å like electrodes under other semiconductor layer surface mask oxide film 8
Form 3

Next, EPROM, NMOSTr, NPN
As shown in FIG. 3D, a resist 84 is formed in a region other than the collector and the emitter of the Tr by a known photolithography technique. Then, using a resist 84 as a mask, As (arsenic) is implanted at 60 KeV and 1E16 ions /
Ion implantation is performed under conditions of about cm ² .

Next, the resist 84 is removed,
As shown in FIG. 4A, the source of the EPROM was subjected to As annealing for 40 minutes in an N ₂ atmosphere.
Drain layer 85, source / drain layer 8 of NMOSTr
6, the NPNTr collector electrode extraction layer 87 and the NPNTr emitter layer 88 are
5, are formed in the second N-well layer 72 and the P-type diffusion layer 78 as a base, respectively. Then PMOST
r, a resist 89 is formed in a region other than the isolation region and the base electrode extraction region by a known photolithography technique.
To form Then, using resist 89 as a mask, B (boron) is applied at 70 KeV, 1.2E by a known ion implantation technique.
Ions are implanted under the condition of 15 ions / cm ² .

Next, the resist 89 is removed,
By performing annealing in an N ₂ atmosphere for 20 minutes, as shown in FIG. 4B, the source / drain layer 90 of the PMOSTr, the P ⁺ diffusion layer 91 in the isolation region, and the base electrode extraction layer 92 of the NPNTr. The second N-well layer 71, the P-type diffusion layer 78 in the isolation region,
And a P-type diffusion layer 78 as a base.

After that, an interlayer insulating film is formed on the entire surface at a thickness of about 5000.degree., And then a contact hole is formed, and a metal wiring is formed.

The NPNT of the device completed as described above
FIG. 5 shows the carrier concentration profile of the r portion.
The distance from the base lower part of mold diffusion layer 78 to the upper part of N ⁺ buried layer 57 is about 8 μm. FIG. 6 shows a carrier concentration profile in the isolation region.

[0064]

As described above in detail, according to the manufacturing method of the present invention, since the epitaxial layer has the two-layer structure of the N-type layer and the P-type layer, the N-type well layer of the NPN transistor is It is only necessary to form the N-type buried layer in the N-type buried layer at a depth corresponding to the thickness of the N-type buried layer, so that the amount of heat treatment at that time can be reduced. As a result, the breakdown voltage of the NPN transistor can be sufficiently secured.

Further, when forming the N-type well layer of the PMOS transistor portion having a high concentration, a second N-type well layer is formed at the same time in the collector electrode take-out region of the NPN transistor to provide the deep collector layer. NPN
The collector series resistance of the transistor drops. As a result, the saturation voltage of the NPN Tr can be reduced and the speed can be improved.

Further, the first and second P-type buried layers form NP
An isolation region for an N-transistor is formed. The first and second P-type buried layers are formed on the surface of the substrate and the N-type epitaxial layer, and these buried layers are diffused from both upper and lower directions to be integrated. Since the connection is made, the diffusion distance at this time can be short. In addition, the carrier concentration of the N-type epitaxial layer serving as the collector of the NPN transistor is about 1E15 atoms / cc. However, if the isolation region is formed as described above, the carrier concentration of the isolation region is at least 1E16 atoms / cc. And a density difference of about 10 times can be provided.
The punch-through withstand voltage can be significantly improved by the high concentration difference, and the width of the isolation region can be narrowed due to the short diffusion distance and the high concentration difference. Can be

[Brief description of the drawings]

FIG. 1 is a process sectional view showing a part of one embodiment of a method of manufacturing a semiconductor device of the present invention.

FIG. 2 is a process sectional view showing a part of one embodiment of a method of manufacturing a semiconductor device according to the present invention;

FIG. 3 is a process sectional view showing a part of one embodiment of a method of manufacturing a semiconductor device according to the present invention;

FIG. 4 is a process sectional view showing a part of one embodiment of a method of manufacturing a semiconductor device according to the present invention;

FIG. 5 is a characteristic diagram showing a carrier concentration profile of an NPN Tr portion in one embodiment of the present invention.

FIG. 6 is a characteristic diagram showing a carrier concentration profile in an isolation region in one embodiment of the present invention.

FIG. 7 is a process sectional view showing a part of a conventional manufacturing method.

FIG. 8 is a process sectional view showing a part of the conventional manufacturing method.

FIG. 9 is a process sectional view showing a part of the conventional manufacturing method.

FIG. 10 is a process sectional view showing a part of the conventional manufacturing method.

FIG. 11 is a characteristic diagram showing a carrier concentration profile of an NPN Tr portion in a conventional manufacturing method.

[Explanation of symbols]

51 P-type Si substrate 53 NPN Tr formation region 54 PMOSTr formation region 57 N ⁺ buried layer 58 Isolation region 60 First P ⁺ buried layer 61 N-type epitaxial layer 64 Second P ⁺ buried layer 65 P-type epitaxial Layer 68 Collector electrode extraction region 70 First N-well layer 71 Second N-well layer 72 Second N-well layer

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-3-286562 (JP, A) JP-A-60-250664 (JP, A) JP-A-48-103184 (JP, A) JP-A-1- 226172 (JP, A) JP-A-2-112271 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/331 H01L 21/8222 H01L 21/8249 H01L 27/06 H01L 29/73

Claims (2)

(57) [Claims] A step of forming an N-type buried layer on the surface of an NPN transistor formation region of a P-type semiconductor substrate, and then forming an N-type epitaxial layer and a P-type epitaxial layer on the substrate; Introducing a first N-type impurity into the NPN transistor formation region of the P-type epitaxial layer; and before or after this first N-type impurity introducing step,
Introducing a second N-type impurity into the PMOS transistor formation region of the P-type epitaxial layer, and simultaneously introducing a second N-type impurity into a region of the P-type epitaxial layer which is to be a collector electrode extraction portion of the NPN transistor; Then, by performing an impurity diffusion heat treatment, the P
In the NPN transistor formation region of the
Forming a first N-type well layer and forming a second N-type well layer in a PMOS transistor formation region of a P-type epitaxial layer and a region serving as a collector electrode extraction portion of an NPN transistor. Device manufacturing method. 2. A step of forming an N-type buried layer on a surface of an NPN transistor forming region of a P-type semiconductor substrate and forming a first P-type buried layer on a surface of an isolation region of the NPN transistor. Forming an N-type epitaxial layer on the P-type semiconductor substrate having these buried layers; and forming a second P-type buried layer on the surface of the NPN transistor isolation region of the N-type epitaxial layer. Forming a P-type epitaxial layer on the N-type epitaxial layer; and forming an N-type well layer in the NPN transistor formation region of the P-type epitaxial layer. 2. A method of manufacturing a semiconductor device, comprising: vertically diffusing a P-type buried layer and connecting them together.