JP3400234B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power IC in which a high breakdown voltage power element and a control circuit element are monolithically integrated.

[0002]

2. Description of the Related Art The development of power ICs has become very active in recent years. With regard to insulation isolation technology, development of pn junction isolation and dielectric isolation technology has diversified, and regarding device technology, high performance of devices by Bi / MOS combination and integration of multi-devices including high-precision analog CMOS Higher functionality is steadily being advanced. In addition, while various circuits are integrated to make it more intelligent, the development of level shift circuit technology that eliminates the potential difference between the low voltage control circuit section and the high voltage output circuit section is also active. In addition, various examples of development of intelligent power devices (hereinafter referred to as IPDs) that combine these elemental technologies have been reported, and their practical use has been accelerated. As shown in FIG. 3, the IPD is a power IC in which elements having greatly different required performances and structures are mounted on one chip. FIG. 3 shows a power IC using pn junction isolation, which includes a p layer 12 on an n ⁺ substrate 11.
N wells 141, 142, 143 are formed inside the
Inside each n-well, power MOSFETs 1, n
A pn bipolar transistor 2 and a MOS capacitor 3 are formed. When making an IPD as shown in Figure 3,
Since many kinds of elements are formed at the same time, it is important to make the processes as common as possible from the viewpoint of product cost.

A MOS in the structure shown in FIG. 3 in FIG.
The sectional view of the capacitor 3 part is shown. In this case, the gate oxide film 172 forming the MOS capacitor 3 is the gate oxide film 171 of the power transistor 1 on the chip or the CMO formed on the other region of the semiconductor substrate 11 (not shown).
The upper electrode 182 of the MOS capacitor 3 is formed simultaneously with the formation of the gate oxide film of another device such as S, and the upper electrode 182 of the MOS capacitor 3 is formed simultaneously with the polysilicon layer to be the gate electrode 181 of the power MOSFET 1. Further, the n ⁺ region of the lower electrode 139 is formed at the same time as the formation of the deep n ⁺ region 138 serving as the extraction region of the n ⁺ buried layer 132 for reducing the collector resistance of the npn bipolar transistor 2. However, the pn junction isolation technique shown in FIG. 3 has a problem that there is a risk of latch-up due to the parasitic pnpn element and an increase in isolation region due to an increase in isolation withstand voltage. Further, the insulating isolation technique using a buried oxide film or the like has a drawback that the U-groove formation, the formation of an oxide film in the U-groove, and the flattening process such as etch back are required, which increases the number of processes.

FIG. 5 shows another example of a conventional IPD. In the case of FIG. 5, unlike the case of FIG. 3, the wafer isolation structure is self-isolated, and no special element isolation region type is required. That is, the p body 151 of the power MOSFET 1 and the n channel M are formed on the n layer 31 formed on the n ⁺ substrate 11 which becomes the drain region of the power MOSFET 1.
Although the p-well 153 of the OSFET 4 and the p-region 154 serving as the lower electrode of the MOS capacitor are formed,
It is not necessary to form a diffusion region for element isolation or a buried insulating film, and is characterized by a simple structure and easy manufacture.

[0005]

However, although the structure of the IPD shown in FIG. 5 is characterized in that the element isolation region is unnecessary, n-type diffusion is performed on the lower electrode 154 of the MOS capacitor 3 as in the example of FIG. Since the layer cannot be used, the p-type diffusion layer 154 must be used. p-type diffusion layer 154
This is because it is inconvenient to use an n-type diffusion layer instead of the above because it becomes common with the n ⁺ drain region 11 of the power MOSFET 1 which is an output transistor.

When this p-type diffusion layer 154 is to be formed simultaneously with the formation of another diffusion layer, for example, the p-well 153 for forming the n-channel MOSFET 4 may be used. However, since the impurity density is relatively low, when about -1 V is applied to the upper electrode, an inversion layer is formed on the surface of the lower electrode, which causes a problem that the capacitance changes. In addition, power MOSF
The diffusion of the p body 151 of ET1 cannot be used as a common process because it is formed after patterning the polysilicon gate. Therefore, this structure requires a separate step of forming the p-type diffusion layer 154 dedicated to the lower electrode of the MOS capacitor, which increases the number of manufacturing steps.

In view of the above problems, an object of the present invention is to easily form a MOS on the same semiconductor substrate without adding any special process even in the self-separation type IPD as shown in FIG.
It is an object of the present invention to provide a semiconductor device capable of forming a capacitor.

[0008]

In order to achieve the above object, a semiconductor device according to a first aspect of the present invention has a first conductivity type semiconductor substrate 31 and a semiconductor substrate 3 as shown in FIG.
First main electrode region 11 of the first conductivity type formed under 1
A second conductivity type body region 151 formed in a part of the upper portion of the semiconductor substrate 31, and a first conductivity type second main electrode region 16 formed on an upper surface of the second conductivity type body region 151.
1. A self-separation type power I that is composed of a power MOSFET 1 including at least 1 and a MOS capacitor 3 formed on another part of the upper portion of the semiconductor substrate 31.
C, the MOS capacitor 3 is a power MOSFE
Simultaneously with the formation of the second conductivity type body region 151 of T1, two second conductivity type diffusion regions 15 formed adjacent to each other are formed.
5 is to use the overlapping region of the lateral diffusion as the lower electrode.

Here, the first conductivity type is, for example, n-type, and the second conductivity type is a conductivity type different from the first conductivity type, that is, p-type, but p and n may be reversed. Of course. The structure shown in FIG. 1 is an example in which a p-type body region (p body region) 151 and a p-type diffusion region 155 are formed on an n-type semiconductor substrate 31. Further, in FIG. 1, the first main electrode region 11 of the power MOSFET means the drain region and the second main electrode region 161 means the source region, but the drain region and the source region may be reversed.
The semiconductor substrate 31 is formed by the CZ method or the FZ method and has a specific resistance of about 50 Ω-cm to 1000 Ω-cm and a thickness of 150.
A semiconductor wafer (silicon wafer) having a thickness of up to 600 μm, a specific resistance of about 50 Ω-cm to about 1000 Ω-cm,
An epitaxial substrate having a thickness of about 30 to 150 μm may be used.

The second feature of the present invention is that the power MOSFET 1 and the MOS capacitor 3 are integrated on the first conductivity type semiconductor substrate 31 in a small amount as shown in FIG.
C, the power MOSFET 1 has a semiconductor substrate 31
Of the first conductivity type semiconductor region 11 formed in the lower part of the first main electrode region and two second conductivity type body regions 151 formed in a part of the upper part of the semiconductor substrate 31, and the body region 151. The second of the first conductivity type formed on the upper surface
Main electrode region 161, a first gate oxide film 171 formed on the semiconductor substrate 31 between the two body regions 151, and a first gate oxide film 171 formed on the first gate oxide film 171. And a polysilicon gate electrode 181 of the power MOS.
Simultaneously with the formation of the body region 151 of the FET 1, an overlapping region of lateral diffusion of two second conductivity type diffusion regions 155 formed adjacent to each other is used as a lower electrode, and is formed on the lower electrode and the upper part of the lower electrode. Second gate oxide film 1
72 and at least a second polysilicon gate electrode 182 above the second gate oxide film 172, and a power M
The body region 151 of the OSFET 1 and the second conductivity type diffusion region 155 of the MOS capacitor are formed by the openings of the first and second polysilicon gate electrodes 181 and 182.
That is, the semiconductor device is a region formed in a self-aligned manner. Similar to the first feature described above, the semiconductor substrate 3
1 may be a CZ or FZ substrate or an epitaxial substrate.

As shown in FIG. 2, the third feature of the present invention is that the power IC according to the above-mentioned second feature is further formed into a first second conductivity type well region 153 formed on the semiconductor substrate 31. , The MOS transistor 4 sharing a small amount of the source region 163 and the drain region 164 formed inside the well region 153, and the second conductivity type diffusion region 155 of the MOS capacitor 3 is the first conductivity type diffusion region 155 of the MOS transistor 4. That is, it is formed inside the second second-conductivity-type well region 156 formed at the same time as the formation of the second-conductivity-type well region 153. If the first conductivity type is n-type, the second conductivity type well regions 153 and 156 are p-type well regions (p-well regions), and the MOS transistor 4 is an n-channel MOSFET. The n-type may be reversed.

A fourth feature of the present invention is that, as shown in FIGS. 1 and 2, a lower electrode formed of one conductivity type diffusion region 155,
The insulating film 172 on the diffusion region 155 and the insulating film 17
2 is a power IC having a capacitor section 3 including an upper electrode 182 made of a polysilicon film containing a small amount of impurities of the same conductivity type as the diffusion area 155 above, and a region serving as a lower electrode of the capacitor section 3 is Silicon film 18
2 is used as a mask and is an overlapping region of the lateral diffusion regions of two diffusion regions 155 formed in a self-aligned manner from both sides of the polysilicon film 182 and adjacent to each other. In FIG. 1 and FIG. 2, the one conductivity type diffusion region 15 is provided.
Reference numeral 5 is a p-type diffusion region 155.
Reference numeral 55 denotes another circuit element forming the power IC, for example, when the p body region 151 of the power MOSFET 1 is formed in a self-aligned manner using the polysilicon film 181 as a mask,
At the same time, the polysilicon film 182 can be formed as a mask in a self-aligned manner. That is, p-type doping of the polysilicon film 182 of the upper electrode of the capacitor,
The p-type doping of the lower electrode 155 can be performed at the same time without increasing the number of steps of the power MOSFET. It is sufficient that the polysilicon film 182 contains a small amount of p-type impurities, so that the n ⁺ -type doped polysilicon film 182 as a whole can be formed by doping a higher concentration of n-type impurities in the subsequent process. Alternatively, it may be a polysilicon doped with n ⁺ from the beginning and doped with a p-type impurity at a concentration lower than that. Further, finally, p ⁺ doping may be further performed. That is, the final polysilicon film 1
The conductivity type of 82 may be n or p, and whether it is n or p may be determined by the design of the entire power IC.

The fifth feature of the present invention is as shown in FIG.
A diffusion region 155 serving as a lower electrode of the capacitor unit 3 is formed in a well region 156 of the same conductivity type as the one conductivity type formed on the surface of the semiconductor region 31 of the conductivity type opposite to the one conductivity type diffusion region 155. It is that you are. That is, according to the fifth feature of the present invention, another circuit element constituting the power IC, for example, the n-channel MOSFE in FIG.
Since the p-well 156 of the capacitor section 3 can be formed at the same time when the p-well 153 of T4 is formed, even a self-separation type power IC does not involve any additional steps.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of a self-separation type IPD according to a first embodiment of the present invention. First of the present invention
In the IPD according to the embodiment of the present invention, the impurity density 10 ¹³ to 10 ¹³ is formed by epitaxial growth on an n ⁺ substrate which is a FZ or CZ substrate having a specific resistance of 0.01 to 0.02 Ω-cm to be the drain region of the power MOSFET 1. ¹⁶ c
m ⁻³ , the n of the power MOSFET 1 is provided inside the p body 151 formed on the n layer 31 having a thickness of 30 to 150 μm.
^{A +} source region 161 is formed, and two p bodies 151 are formed.
A gate oxide film 171 is formed on the surface of the n layer (epitaxial substrate) 31 between them, and a gate electrode 181 of the power MOSFET 1 made of polysilicon is formed thereon. As described above, the specific resistance is 50 to 1000Ω.
A CZ or FZ wafer having a thickness of -cm and a thickness of 30 to 150 μm is used as the n layer 31, and an n ⁺ region having an impurity density of 1 × 10 ¹⁸ to 1 × 10 ²⁰ cm ⁻³ is formed on the back surface of the CZ or FZ wafer by diffusion or epitaxial growth. 11 may be formed. Further, a p well 153 is formed on a part of the surface of the n layer.
Is formed, and an n ⁺ source region 163 and an n ⁺ drain region 164 are formed therein, and an n-channel MOSFE is formed.
It constitutes T4. A gate oxide film 173 and a polysilicon gate electrode 183 are formed on the surface of the p well 153 between the n ⁺ source region 163 and the n ⁺ drain region 164. Further, as shown on the left side of FIG. 1, the MOS capacitor 3 is formed on the surface of the n layer 31 where the power MOSFET 1 and the n channel MOSFET 4 are not formed.

In the MOS capacitor 3 constituting the IPD of the first embodiment of the present invention, the surface of the portion where the lateral diffusions of the two p bodies 155 formed adjacent to the surface of the n layer 31 overlap each other. A gate oxide film 172 and a polysilicon gate electrode 182 are formed on the substrate. That is, the polysilicon gate electrode 182 serves as the upper electrode of the MOS capacitor, and the p body 155 serves as the lower electrode.
The conventional technique shown in FIG. 5 requires an independent process for forming the p-type diffusion layer 154, which complicates the process.
Since the OS capacitor is formed and the impurity density on the surface is low, there is a problem that when a voltage is applied to the upper electrode, an inversion layer is formed on the surface of the p body 154 and the capacitance changes. According to the first embodiment of the present invention, since the lateral diffusions of the two p bodies (p type diffusion layers) overlap each other, the surface impurity density is lower than that of the single p type diffusion layer 154. It becomes high, and it becomes difficult to form the inversion layer. Moreover, the p body 15 of the power MOSFET 1
Since the p body 155 of the MOS capacitor 3 may be formed at the same time when 1 is diffused, the number of steps does not increase. That is, even after the patterning of the polysilicon gate 181 of the power MOSFET 1, the p-body 155 serving as the lower electrode region can be formed in a self-aligned manner by using the pattern of the polysilicon electrode 182 patterned simultaneously with the polysilicon gate 181 as a mask. . For example, using the pattern of the polysilicon electrode 182 as a mask, ¹¹ B ^{+ is used} for the acceleration voltage V _ac = 45-100 keV and the dose amount Φ = 1 × 10.
Ions may be implanted at ¹³ to 1 × 10 ¹⁴ . The width of the polysilicon gate electrode 182 has a predetermined dimension, for example, such that the two p bodies 155 overlap each other in the lateral diffusion that naturally occurs when the p body 151 of the power MOSFET 1 is vertically diffused to a predetermined depth. It may be selected in the range of 2 to 5 μm. The width of the gate of the power MOSFET 1 may be, for example, 4 to 10 μm. Then p
After the body 155 is formed, SiO ₂ or PSG which will be the interlayer insulating film 19 of the power MOSFET 1 is CVD-formed, and then the p body 15 is formed with an alignment margin of, for example, about 1 μm.
Open a contact hole in 5, and power MOSFET 1
The upper electrode 262 of the MOS capacitor 3 may be formed at the same time as the source electrode 211 metallization step.

FIG. 2 is a sectional view of a self-separating IPD according to the second embodiment of the present invention. In the IPD according to the second embodiment of the present invention, n of the power MOSFET 1 is formed inside a p body 151 formed on an n layer 31 formed by epitaxial growth on an n ⁺ substrate which is a drain region of the power MOSFET 1. ^{A +} source region 161 is formed, a gate oxide film 171 is formed on the surface of the n layer 31 between the two p bodies 151, and a gate electrode 181 of the power MOSFET 1 made of polysilicon is formed thereon. The n layer 31 may be a CZ substrate or an FZ substrate, and the n ⁺ region 11 may be formed by diffusion or epitaxial growth. Whether to use the CZ or FZ substrate or the epitaxial substrate may be designed according to the breakdown voltage of the power IC, the switching speed, the ON voltage, and the like. Further, a p well 153 is formed on a part of the surface of the n layer, and an n ⁺ source region 163 and an n ⁺ drain region 164 are formed inside the p well 153.
Are formed to form the n-channel MOSFET 4. A gate oxide film 173 and a polysilicon gate electrode 183 are formed on the surface of the p well 153 between the n ⁺ source region 163 and the n ⁺ drain region 164. Further, as shown on the left side of FIG. 2, the power MOSFET 1 and the n-channel MOSFET 4 are provided on the surface of the n-layer 31.
P-well 156 is formed in a portion where
The MOS capacitor 3 is formed on the surface thereof. That is, M that constitutes the IPD of the second embodiment of the present invention
In the OS capacitor 3, the gate oxide film 172 and the polysilicon gate electrode 182 are formed on the surface of the portion where the lateral diffusions of the two p bodies 155 formed adjacent to the surface of the p well 156 overlap. Then, like the first embodiment of the present invention, the polysilicon gate electrode 1
82 is the upper electrode of the MOS capacitor, and p body 1
55 is the lower electrode. When a MOS capacitor is formed on a single p body 154, the impurity density on the surface is low, so that when a voltage is applied to the upper electrode,
As described above, there is a problem that the inversion layer is formed on the surface of the p body 154 and the capacitance changes, but according to the second embodiment of the present invention, two p bodies are formed. Of the p-well 156, the surface impurity density is higher than that of a single p-body, and the inversion layer is less likely to be formed. Moreover, n-channel MOSFET
Since the p well 156 of the MOS capacitor 3 is formed when the p well 153 of No. 4 is formed and the p body 155 of the MOS capacitor 3 is also formed at the same time when the p body 151 of the power MOSFET 1 is diffused, the number of steps does not increase.

It is needless to say that the present invention may be applied to a pn junction separation type power IC and an insulation separation type power IC other than the self-separation type power IC. Also, it goes without saying that p and n may be reversed in the above description.

[0018]

According to the present invention, the self-separation type power I
Even in the case of C, a p-type diffusion layer used as a lower electrode region of a MOS capacitor is simultaneously formed in another region on the same semiconductor chip to form a power MOSFET or an n-channel MO.
It becomes possible to form the SFET simultaneously with the diffusion step in the process, and it is not necessary to add the number of steps, which is a problem of the conventional technology. Therefore, the manufacturing cost is reduced,
The manufacturing yield can also be improved.

In particular, since the present invention can be applied to a self-separation type power IC, the structure of the IC is simplified, the manufacturing process is simplified, and the manufacturing cost is reduced and the yield is greatly improved.

[Brief description of drawings]

FIG. 1 is a schematic view of a cross section of an IPD according to a first embodiment of the present invention.

FIG. 2 is a schematic view of a cross section of an IPD according to a second embodiment of the present invention.

FIG. 3 is a sectional view of an IPD using a conventional junction separation technique.

FIG. 4 is an enlarged cross-sectional view of a MOS capacitor unit used in the IPD shown in FIG.

FIG. 5 is a sectional view showing a structure of an IPD using a conventional self-separation technique.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 power MOSFET 2 npn bipolar transistor 3 MOS capacitor 4 n channel MOSFET 11 n ⁺ region 12 p layer 17 field oxide film (thermal oxide film) 19 interlayer insulating film 31 n layer (semiconductor substrate) 131, 132, 133 n ⁺ buried layer 138, 139 deep n ⁺ region 141, 142, 143 n well 151, 155 p body 152 p base 153, 156 p well region 154 p type diffusion layer 161, 163 n ⁺ source region 162 n ⁺ emitter region 164 n ⁺ drain region 171,173 MOSFET gate oxide film 172 MOS capacitor gate oxide film 181,182,183 Polysilicon gate electrodes 211,212 Source electrode 213 Drain electrode 221 Emitter electrode 231 Base electrode 241 Collector electrode 251 , 261,262 MOS capacitor metal electrodes

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 29/78 H01L 27/04 H01L 27/06 H01L 21/822 H01L 21/8234

Claims (5)

(57) [Claims] 1. A semiconductor substrate of a first conductivity type, and a first main electrode region of a first conductivity type formed under the semiconductor substrate,
A power having at least a second conductivity type body region formed on a part of an upper portion of the semiconductor substrate and a first conductivity type second main electrode region formed on an upper surface of the second conductivity type body region. A power IC comprising a small amount of a MOSFET and a MOS capacitor formed on another part of the upper part of the semiconductor substrate, wherein the MOS capacitor is formed when the second conductivity type body region of the power MOSFET is formed. At the same time, the semiconductor device is characterized in that an overlapping region of lateral diffusion of two second conductivity type diffusion regions formed adjacent to each other is used as a lower electrode. 2. A power IC in which a power MOSFET and a MOS capacitor are co-integrated in a small amount on a first conductivity type semiconductor substrate, the power MOSFET being a first conductivity type formed under the semiconductor substrate. Using the semiconductor region as a first main electrode region, two second conductivity type body regions formed in a part of the upper portion of the semiconductor substrate and a first conductivity type first region formed on the upper surface of the body region. Second main electrode region, a first gate oxide film formed on the semiconductor substrate between the two body regions, and a first polysilicon film formed on the first gate oxide film. At least a gate electrode, the MOS capacitor is formed at the same time as the formation of the body region,
An overlapping region of lateral diffusion of two second conductivity type diffusion regions formed adjacent to each other is used as a lower electrode, the lower electrode, a second gate oxide film formed on the lower electrode, and At least a second polysilicon gate electrode on the second gate oxide film is provided, and the body region and the second conductivity type diffusion region are formed by the openings of the first and second polysilicon gate electrodes. A semiconductor device, which is a region formed in a self-aligned manner. 3. The power IC further comprises a first second conductivity type well region formed on the semiconductor substrate, and a first conductivity type source region and drain region formed inside the well region. And a second common conductivity type diffusion region formed inside the second second conductivity type well region formed at the same time as the formation of the first second conductivity type well region. 3. The method according to claim 2, wherein
The semiconductor device described. 4. A lower electrode composed of one conductivity type diffusion region,
What is claimed is: 1. A power IC comprising: a capacitor portion having an insulating film above the diffusion region and an upper electrode made of a polysilicon film containing a small amount of impurities of the same conductivity type as the diffusion region above the insulating film; The semiconductor device is characterized in that the region to be the lower electrode is a region where two diffusion regions formed adjacent to each other in a self-aligned manner with the polysilicon film as a mask overlap each other in the lateral diffusion region. Characterized in that wherein said one conductivity type diffusion region is formed on the opposite conductivity type formed on the surface of the semiconductor region, in the well region of the one conductivity type and the same conductivity type as the diffusion region The semiconductor device according to claim 4 .