JPS61139057A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain a desired current amplification factor in a bipolar transistor, by forming a second pattern without removing first resist patterns, and using these resist patterns as blocking masks in ion implantation when an outer base region is formed. CONSTITUTION:First resist patterns 511-514 are selectively formed on a polycrystalline silicon layer 28. With said patterns as masks, the polycrystalline silicon layer 28 is patterned. Thus, gate electrodes 31 and 32 of a CMOS, an emitter taking out electrode 33 of a bipolar transistor and a collector taking out electrode 34 are formed. Then, a second resist pattern 52 having an opening is formed on a PMOSFET part and an active base region 23 of the bipolar transistor, without removing the first resist patterns 511-514. Thereafter, with the second resist pattern 52, the first resist patterns and the exposed part of a field oxide film as blocking masks, boron ions are implanted.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention combines a polycrystalline silicon gate complementary MoS transistor with excellent high-speed characteristics and a low power consumption bipolar transistor with a high cut-off frequency on the same chip. The present invention relates to an improvement in a method for manufacturing a semiconductor integrated circuit device that coexists within a semiconductor integrated circuit device.

[Technical background of the invention]

A semiconductor integrated circuit in which a bipolar transistor and a complementary MOS transistor (hereinafter referred to as 0MO8) coexist on the same semiconductor substrate is generally referred to as 8i-0MO8, and is capable of both analog and digital functions within the same chip. This is a relatively new semiconductor integrated circuit device (IC) that has appeared in response to the demand for coexistence.

Incidentally, the process for manufacturing bipolar semiconductor devices and the process for manufacturing OMO8 have been developed independently, and both are manufactured using unique processes suitable for their respective structures. Therefore, bipolar process and CMO
When manufacturing the above B knee CMO8 by combining the S process, it is difficult to satisfy the characteristics of both bipolar transistors and 0MO8, and in particular, it is difficult to satisfy the characteristics of both bipolar transistors and 0MO8. Achieving this will be extremely difficult. Therefore, in order to meet such demands, the applicant has proposed, for example, a B i-
A method for manufacturing 0MO8 was previously proposed in Japanese Patent Application No. 108069/1983.

As will be described later, the basic idea of the above-mentioned method proposed by the applicant is included in the present invention as it is, and its main points will be explained below along the structure of FIG.

The first point is that the P type substrate 11, the N+ type buried region 121
122 and N-type well regions 141 and 142 to separate the element regions of the OMO3 and bipolar transistors. That is, the N" type buried region 121.
By adopting the N-type well regions 141 and 142 that are in contact with the N-well region 122, the heat treatment time for forming the N-well can be shortened, and impurities from the N+-type buried region can be diffused upward to form impurities in the N-well region. Fluctuations in concentration can be prevented.

Therefore, the characteristics of the NPN transistor formed using the N well 141 as a collector region can be improved, and the threshold voltage of the P channel MOS transistor formed in the N well region 142 can be stabilized.

The second point is the formation of the N1 type emitter region 36 of the NPN transistor and the N++ source and drain regions 38 and 38' of the N channel MOS transistor in 0MO8.
Moreover, the N++ emitter region 36 is formed by thermal diffusion using the extraction electrode 33 made of a polycrystalline silicon layer as a diffusion source. This makes the junction of the N++ emitter region 36 shallow and provides the NPN transistor with high cut-off frequency characteristics and low power consumption characteristics.At the same time, the source and drain regions 38 and 38' of the N-channel MOS transistor are formed through electrode penetration when forming the aluminum electrode. It becomes possible to form the film with a sufficient diffusion depth to prevent this.

[Problems in the Background Art] However, the above-mentioned conventional method for manufacturing 3i-0MO8 proposed by the applicant includes the steps shown in FIGS. 3(A) and (B), and the following A problem like this was occurring.

FIG. 3A shows a stage in which an N+ type emitter region 36 of an NPN transistor is formed using an extraction electrode 33 made of arsenic-doped polycrystalline silicon as a diffusion source. From this state, the N-channel MOS transistor portion of 0MO8 is covered with a resist pattern 26, as shown in FIG. 3(B). Next, using the resist pattern 26, field oxide 1I20, gate electrode 31, emitter extraction electrode 33, and collector extraction electrode 34 as a blocking mask, ions are implanted over the entire surface to form the P+ type source region and drain region 39 of the P channel MOS transistor.
．． 39' and the P" type external base region 4o of the NPN transistor are formed in a self-aligned manner. Note that the gate electrode 3
1. The extraction electrodes 33 and 34 are both formed of a polycrystalline silicon layer, and an oxide film 37 is formed on the surface thereof.

However, the oxide film 37 covering each electrode is formed by thermally oxidizing the surface of these polycrystalline silicon patterns, and cannot be made that thick due to the need to keep the ρS of these electrodes small. Boron is also injected into the electrode 33. The boron thus implanted into the emitter extraction electrode 33 is diffused into the N2 type emitter region 36 by subsequent heat treatment, resulting in the problem that the desired current amplification factor cannot be obtained in the NPN transistor.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and improves the conventional manufacturing method of B i -0MO8 proposed by the applicant in the previous application, provides its basic characteristics as is, and also provides the method shown in FIG. 3 (A ) The present invention provides a method for manufacturing a semiconductor device that can solve the problems described in (B) and obtain a desired current amplification factor in a bipolar transistor.

[Summary of the invention]

A method for manufacturing a semiconductor device according to the present invention includes selectively forming a plurality of second conductivity type high concentration buried regions in a surface layer of a first conductivity type semiconductor substrate, and then forming a first conductivity type high concentration buried region covering a main surface of the semiconductor substrate. a second conductivity type that reaches each of the plurality of second conductivity type high tide buried regions by selectively diffusing second conductivity type impurities from the surface of the epitaxial semiconductor layer; A step of forming a well region and selectively forming a field oxide film on the surface of the epitaxial semiconductor layer form a first conductivity type element region and a second conductivity type element region surrounded by the field oxide film. a step of covering the surfaces of all of these device regions with a thin insulating film serving as a gate insulating film; and a step of selectively doping a first conductivity type impurity into a portion of the second conductivity type device region to form a bipolar transistor. the first of
forming a conductive type active base region; forming an emitter diffusion window in the thin insulating film covering the active base region; and forming a polycrystalline silicon layer heavily doped with a second conductive type impurity into a device selectively forming a first resist pattern on the polycrystalline silicon layer, and selectively etching the polycrystalline silicon layer using the first resist pattern as a mask. A gate electrode of an insulated gate field effect transistor is formed via the thin oxide film on the second conductivity type element region and the first conductivity type element region where the active base region is not formed, and the gate electrode is formed on the active base region. A step of forming an emitter lead-out electrode in contact with the active base region through the emitter diffusion window on the second conductivity type element region where the resist pattern is formed, and a step of forming an emitter lead-out electrode on the active base region without removing the first resist pattern. forming a second conductive type device region where the active base region is not formed and a second resist pattern having an opening on the active base region; and using a blocking mask for the first and second resist patterns. By ion-implanting impurities of the first conductivity type, a high concentration external base region of the same conductivity type is formed in the active base region in a self-aligned manner, and at the same time, a second conductivity type element in which the active base region is not formed is formed. After forming self-aligned first conductivity type source and drain regions on both sides of the gate electrode, and removing the first and second resist patterns, the emitter extraction electrode is formed as a diffusion source. forming an emitter region of a second conductivity type in the active base region of the first conductivity type by thermally diffusing impurities; The method is characterized by comprising a step of forming self-aligned second conductivity type source and drain regions on both sides of the gate electrode by doping type impurities.

In the manufacturing method according to the present invention, the second resist pattern is formed without removing the first resist pattern, and the third resist pattern is used as a blocking mask for ion implantation when forming the external base region. This solves the problem explained in Figure <A>(B). The other configurations are basically the same as the conventional manufacturing method proposed by the applicant, and have the same effects as the prior invention.

[Embodiments of the invention]

Hereinafter, with reference to FIGS. 1(A) to (I), 3 according to the present invention
An example of a method for manufacturing i-0MO8 will be described.

(1) First, as shown in Figure 1(A), the substrate concentration is 1.
After forming an insulating film for diffusion, for example, a thermal oxide film, on the P-type silicon substrate 11 of about 0.014 to 101 Tor' and patterning the necessary parts, antimony (Sb) or arsenic (As) is applied using this as a diffusion mask. selectively diffuses 1018-102/CI! A high concentration N+ type buried head region 1a12t122 having an impurity concentration of 1a12t122 is formed. Next, after removing the above insulating film, P-type epitaxial film is applied to the entire surface of the wafer! ! 13 is deposited and formed. The thickness of the P-type epitaxial layer 113 is 1 to 5-1, and the specific resistance is 0.
The resistance should be 5 to 10 Ω·cm. However, this is a fixed standard and is a value that should naturally be changed depending on the specific conditions of the element. Next, the bipolar transistor formation region F
t1. and PMO8FET formation region, respectively.
The well regions 114t and 142 are formed as follows.

First, the surface of the wafer is thermally oxidized to a film thickness of 50.
A thermal oxide film 15 of 0 to 1,000 layers is formed, and thermal diffusion is performed on the phosphorus ion implanted to form a diffusion source. For example, dose [l 2×1QL2, acceleration voltage 150 keV
Phosphorus ion implantation is carried out under the following conditions, and in the subsequent thermal process 1 to 3
If diffused to a depth of approximately JJIIL, an N-well region with a surface impurity concentration of 8 to 10 x 10" cts-3 will be formed. This thermal diffusion may be performed using a high temperature thermal process of 1000° C. or higher. , N+ type buried region 12112
Since upward diffusion of impurities using 2 as a diffusion source also occurs at the same time, the diffusion length (
In other words, the diffusion time) is shortened, and an N-well can be easily formed.

(Secondly, the device region is defined as shown in FIG. 1(B). First, the surface of the P-type epitaxial layer 13 is thermally oxidized to form a thermal oxide film 16 with a thickness of 300 to 2,000. Further, an oxidation-resistant insulating film 17 of, for example, 5 iaN+ is deposited to a thickness of about 1000 by CVD method.Then, this laminated layer 11116.17 is patterned to leave the laminated film only in the area where the element is to be formed. Thereafter, if necessary, boron or phosphorus ions are implanted using the laminated films 16 and 17 as a mask to form channel cuts 18 and 19.

(3) Next, selective oxidation is performed using the oxidation-resistant insulator 117 as a mask, and as shown in FIG.
1.2 JJIIL field oxide Il*2O is formed, and the P-type element region and N
A mold element region is formed separately. Subsequently, the above-mentioned laminated film 16
．． After removing 17 to expose the surface of the element region, the surface of the element region is thermally oxidized again to form a thermal oxide film 21 having a thickness of 200 to 1000 nm, which will become the gate oxide film of the MOS transistor.

Note that the reason why a thick insulating isolation film 20' is formed also in the element region (N-well region 121) for the bipolar transistor is to form a bipolar transistor having a walled base structure.

(Next, boron ions are selectively implanted into the bipolar transistor element region to form a P-type active base region (internal base region of draft base structure) 23 as shown in FIG. 1 (D). This ion implantation masks unnecessary parts with a resist pattern, and also masks the field oxide film 20 and insulating isolation film 20 in the bipolar transistor part.
′ as a blocking mask. Ion implantation followed by annealing or optionally 1000-110
Diffusion slumbing was performed at a temperature of 0°C, and the sheet resistance ρs
= active base area of about 500 to 1000Ω/mouth [2
Get 3. Thereafter, channel ion implantation 24 and 25 is performed to control the threshold voltages of the PMO8FET and the NMO8FET, if necessary.

(5) Next, as shown in FIG. 1(E), an N'' type collector contact region [27] is formed and a polycrystalline silicon layer 28 is deposited as an electrode material.This is done as follows.

First, the emitter diffusion window 291 and collector diffusion window 292 of the bipolar transistor are opened in the thermal oxide film 21 covering the surface of each element region. Subsequently, an undoubted polycrystalline silicon layer 28 having a thickness of 2,000 to 6,000 wafers is formed by depositing an undoubted polycrystalline silicon layer 28 by a CVD method. Furthermore, after forming a CVD-8i02 film 30 with a film thickness of about 5000, the collector diffusion window 2 of the bipolar transistor is formed.
92. Selectively remove the CVD-8i02 film 30 covering the PMO3FET and NMO8FET parts.

Next, using the remaining CVD-8i02 film 30 as a mask, high concentration phosphorus is selectively diffused into the polycrystalline silicon 1128 using POCl3 or the like as a diffusion source, thereby increasing its sheet resistance (ρS) to ρ8-20Ω/ Reduce it to about B. At this time, since the diffusion coefficient in the polycrystalline silicon layer is large, the highly concentrated phosphorous penetrates through the polycrystalline silicon layer 28 and is diffused into the epitaxial layer via the collector diffusion window 292. As a result, Nwell 14! Inside is N+
An N++ collector contact region 27 is formed that reaches the type buried region 121. Incidentally, the above-mentioned concentration setting and thermal process of P○C+3 are performed so as to sufficiently reach the N+ type region collector contact region 27N" type buried region 121.

Next, after removing the CVD-8i02 film 30 that had masked the bipolar transistor portion by the above-mentioned phosphorus diffusion, arsenic is doped only into the masked portion or into the entire polycrystalline silicon layer 28. When doping arsenic, ions are implanted under the conditions of, for example, a dose of 5 to 20×10 1 SCIR4 and an acceleration voltage of 150 keV, and then annealing is performed to make the arsenic concentration in the polycrystalline silicon layer uniform. As a result, the pibora transistor portion is doped only with arsenic, and the other portions are formed with a polycrystalline silicon layer 28 doped with only phosphorus or with phosphorus and arsenic. Alternatively, after depositing an arsenic-doped polycrystalline silicon layer 28 over the entire surface, the bipolar transistor portion may be masked and phosphorous may be diffused at a high concentration (1) in the same manner as described above.

(61 Next, first resist patterns 511 to 511 are selectively formed on the polycrystalline silicon 1!28 formed as described above.
514 and patterning the polycrystalline silicon layer 28 using the first resist pattern as a mask, the 0MO3 gate snow layer 31. shown in FIG. 4(F) is formed.
32, emitter extraction electrode 3 of bipolar transistor
3 and a collector extraction electrode 34 are formed.

(7) Next, as shown in FIG. 1(G), without removing the first resist patterns 511 to 514, open holes are formed on the PMO8FET portion and the active paste region [23] of the bipolar transistor. A second resist pattern 52 having a portion is formed. Subsequently, boron ions are implanted using the second resist pattern 52, the first resist pattern, and the exposed portions of the field oxide film as blocking masks, thereby forming PMO8F.
P+ type source and drain regions 39 are provided in the ET portion.
．． 39' is formed by self-alignment, and at the same time, a P+ type external base region 40 is formed in the bipolar transistor portion by self-alignment.

Note that by curing the first resist patterns 511 to 514 in advance by irradiating ultraviolet rays or the like, the blocking effect against boron ion implantation can be further improved.

(8) Next, first and second resist patterns 5
After removing 11~514.52, this time PMO8FE
The T portion and the bipolar transistor portion are protected with a resist pattern, and phosphorus ions are selectively implanted into the NMO3FET portion. As a result, N1 type source and drain regions are formed in a self-aligned manner using the gate electrode 32 and field oxide film 20 as a blocking mask.
Forming 38°38'. Subsequently, the resist pattern is removed and heat treatment is performed to diffuse arsenic using the emitter electrode 33 as a diffusion source, forming an N+ type emitter region T436 with a shallow junction to ensure a high current amplification factor of the bipolar transistor. Thereafter, the surfaces of the various polycrystalline silicon electrodes 31 to 34 are thermally oxidized to form an oxide film 37 (as shown in FIG. 1 (1-1)).

(9) After that, as shown in FIG. 1 (1), passivation 11W41,4 of PSG film (phosphorus-doped silicate glass film) or BPSG film (boron and phosphorus-doped silicate glass film), etc.
After adding 2, open the contact part of each element,
By performing vapor deposition and patterning of electrode metal to form various electrodes 43, a semiconductor integrated circuit device in which bipolar transistors and OMO3 coexist is completed.

According to the manufacturing method of the above embodiment, high-speed performance of 0MO8 and high cut-off frequency (fr=3 to 6GH) can be achieved through a relatively simple process.
z) can coexist with low power consumption and low noise bipolar transistors. In the bipolar transistor portion, since diffusion of arsenic from polycrystalline silicon is used to form the emitter region 36, a high current amplification factor can be ensured with a shallow junction. In addition, the presence of the N++ collector contact region 27 diffused from a polycrystalline silicon layer containing a high concentration of phosphorus reduces the collector resistance of the bipolar transistor and lowers its on-resistance. It still has the features of the conventional manufacturing method proposed by the applicant, such as being able to keep the saturation voltage low.

However, as is clear from the description of FIGS. 1(F) and 1(G), the manufacturing method of the above embodiment prevents boron from being introduced into the emitter region 36 when forming the external base region 40. be done.

Therefore, the desired current amplification factor can be ensured in the bipolar transistor formed in the same substrate as OMO8.

〔Effect of the invention〕

As detailed above, the method for manufacturing a semiconductor device according to the present invention, similar to the conventional manufacturing method proposed earlier by the applicant, uses a relatively high-speed operation characteristic of 0MO3 and a bipolar transistor with a high cut-off frequency. They can be manufactured together in a simple process, and the problems in conventional manufacturing methods can be solved and a stable desired current amplification factor can be obtained in the bipolar transistor, resulting in remarkable effects.

[Brief explanation of the drawing]

FIGS. 1(A) to (1) show B i which is an embodiment of the present invention.
- Cross-sectional views showing the manufacturing method of a CMO8 semiconductor integrated circuit device in the order of steps, FIGS. 2 and 3 (A) (8) are the conventional manufacturing method of a semiconductor integrated circuit device proposed by the present applicant and its problems. FIG. 2 is a sectional view for explaining. 11...P-type silicon substrate, 121.122...N
+ type buried region 13...P type epitaxial layer, 14
1.142... N well region, 20... Field oxide film, 21... Gate oxide film, 23... P type active base region, 27... N4'' type collector contact region, 28...・Polycrystalline silicon layer, 291-293...
・Diffusion window, 31. 32... Gate electrode, 33... Emitter electrode, 34... Collector extraction electrode, 36...
・N++ emitter extraction 1! Kashiwa, 38.38'...
N++ source and drain regions, 39.39'...
P+ type source and drain region, 40... P+ type external base region, 41.42... Passivation film, 4
3...Metal electrode, 26,511-512.52...
・Resist pattern. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 111 Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] After selectively forming a plurality of second conductivity type high concentration buried regions in the surface layer of the first conductivity type semiconductor substrate, growing an epitaxial semiconductor layer of the first conductivity type covering the main surface of the semiconductor substrate; forming a second conductivity type well region reaching each of the plurality of second conductivity type high concentration buried regions by selectively diffusing a second conductivity type impurity from the surface of the epitaxial semiconductor layer; A step of forming a first conductivity type element region and a second conductivity type element region surrounded by the field oxide film by selectively forming a field oxide film on the surface of the semiconductor layer; A first conductivity type active base region of the bipolar transistor is formed by covering with a thin insulating film that becomes a gate insulating film and selectively doping a first conductivity type impurity into a part of the second conductivity type element region. forming an emitter diffusion window in the thin insulating film covering the active base region; and forming a polycrystalline silicon layer heavily doped with second conductivity type impurities over the device region. , the active base region is formed by selectively forming a first resist pattern on the polycrystalline silicon layer, and selectively etching the polycrystalline silicon layer using the first resist pattern as a mask. a gate electrode of an insulated gate field effect transistor is formed via the thin oxide film on the second conductivity type element region and the first conductivity type element region where the active base region is not formed; forming an emitter extraction electrode in contact with the active base region through the emitter diffusion window on the mold element region; and forming the active base region thereon without removing the first resist pattern. forming a second resist pattern having an opening on the active base region and the second conductivity type element region where the active base region is not exposed; By ion implantation, a highly doped external base region of the same conductivity type is formed in the active base region in a self-aligned manner, and at the same time,
forming self-aligned first conductivity type source and drain regions on both sides of the gate electrode in the second conductivity type device region where the active base region is not formed; After removing the pattern,
forming a second conductivity type emitter region in the first conductivity type active base region by thermally diffusing impurities using the emitter extraction electrode as a diffusion source; forming self-aligned second conductivity type source and drain regions on both sides of the gate electrode by doping with second conductivity type impurities using as a blocking mask. Method of manufacturing the device.