KR0147651B1 - Bicmos device and its manufacture - Google Patents

Abstract

A bi CMOS device and a manufacturing method thereof are described.

It is connected to the emitter region of a bipolar transistor on a semiconductor substrate, and is formed of an emitter electrode composed of polycrystalline silicon implanted with N-type impurities having high destruction of a natural oxide film, and a source / drain region of an N-type MOS transistor on a semiconductor substrate. In addition, the same impurity as the emitter electrode is implanted, and a source / drain electrode composed of a polysilicon film having a thickness thinner than that of the emitter electrode.

Thus, the low contact resistance of the source / drain electrodes and the emitter region can be realized by a shallow junction without additional process.

Description

BiCMOS device and its manufacturing method

1A to 1D are cross-sectional views illustrating a conventional general bi CMOS device and a method of manufacturing the same.

2 is a cross-sectional view showing a bi CMOS device according to an embodiment of the present invention.

3A to 3D are cross-sectional views illustrating a method of manufacturing a bi CMOS device according to a first embodiment of the present invention.

4A to 4C are cross-sectional views illustrating a method of manufacturing a bi CMOS device according to a second exemplary embodiment of the present invention.

5A and 5B are graphs for comparing the diffusion distance of phosphorus (P) diffused to a silicon substrate according to the thickness of the polycrystalline silicon film.

* Explanation of symbols for main parts of the drawings

10: semiconductor substrate 12, 14: N-type and P-type buried layer

16,18: P-type and N-type wells 20: field oxide film

22: gate insulating film 24: gate electrode

25: Spacer 26, 28: source / drain

30: base area 32: collector area

34, 38, 56: interlayer insulating layer 36: resistance

40, 52: source / drain electrodes 44, 53, 54: emitter electrodes

62: wiring

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a BiCMOS device capable of implementing a shallow junction and low contact resistance, and a method for manufacturing the same.

An important aspect in the design of large scale integrated circuits is how to speed up the operation of the circuit and how to reduce the amount of heat emitted from the entire circuit within a certain range even if the number of elements included in the circuit increases.

In general, in a bipolar circuit, a delay time of a gate can be reduced, but a large amount of heat is emitted, thereby limiting the number of transistors that can be integrated in a single chip, and a CMOS circuit (hereinafter referred to as CMOS) circuit. In this case, the amount of heat generated in the circuit can be minimized, which is very advantageous in terms of power consumption. However, in order to charge and discharge the capacitive load, the CMOS transistor's own current driving capability is small, which limits the operation speed.

Recently, Bi-CMOS (hereinafter referred to as BiCMOS) technology, which manufactures bipolar devices and CMOS devices simultaneously, has been developed on a single chip, and has been applied to various communication integrated circuits, video tape recorders (VTRs), and integrated circuits used in cameras. It is also applied to gate arrays and memory devices. Such devices use high-speed and high-density devices by using CMOS for high-density parts and bipolar devices for high-speed parts.

In a semiconductor integrated circuit device, in order to increase the operation speed of devices, a CMOS transistor shortens a channel length, and a bipolar transistor reduces the width of a base region located between an emitter region and a collector region. Higher speeds are achieved by shortening, and impurity concentrations in the emitter region are increased in order to obtain high current gain characteristics.

As an effective manufacturing method for achieving the above object, a polycrystalline silicon layer is laminated in an opening of an insulating layer formed on a silicon substrate, and impurities are injected into the polycrystalline silicon to inject impurities into the polysilicon by a subsequent thermal process. It is possible to shorten the width of the base region by allowing the diffusion of the silicon substrate to shallowly adjust the junction depth of the emitter region. As impurities to be injected therein, a method of shortening the diffusion distance spreading when the thermal process is performed by injecting impurities having a small thermal diffusion coefficient such as an asic (As) or antimony (Sb) to obtain a shallow junction. use. However, in order to simplify the process, when the source / drain electrodes connected to the source / drain regions of the CMOS transistors are formed using the same polysilicon layer, the natural oxide film destruction effect of the asnic (As) or antimony (Sb) is small. Since the contact resistance of the contact window is increased to deteriorate the operating speed of the device, the contact resistance is lowered by injecting phosphorus (P) having a high natural oxide destruction effect. However, since phosphorus (P) has a large thermal diffusion coefficient, a shallow junction cannot be formed, and thus, phosphorus (P) cannot be used in the emitter region of a bipolar transistor. Therefore, in order to fabricate the bi-MOS device while satisfying the electrical characteristics of the emitter region and the source / drain electrodes of the bipolar transistor, the polysilicon layer connected to the emitter region of the bipolar transistor has an ascetic (As) or antimony ( Phosphorus (P) is injected into Sb) into the polysilicon layer connected to the source / drain regions. However, such a method injects different impurities, and thus has a problem of further increasing the photographic process.

1A to 1D are cross-sectional views illustrating a method of manufacturing a conventional general BiCMOS device.

Referring to FIG. 1A, a process of forming N-type and P-type buried patches 12 and 14 on a semiconductor substrate 10, a process of forming an epitaxial layer on the buried layer, and the epitaxial layer Forming p-type and n-type wells 16 and 18 in the shir layer, forming a field oxide film 20 for device isolation in an inactive region of the semiconductor substrate, and forming a thin gate oxide film 22 on the entire surface of the resultant Forming a gate electrode 24 on the gate oxide film, forming a spacer 25 on the sidewalls of the gate electrode, and forming N-type and P-type semiconductor substrates using the gate electrode and the field oxide film as masks. Ion implantation of each type impurity proceeds to a process of forming the source / drain 26 and 28, the base region 30 and the collector region 32 of the bipolar transistor.

Referring to FIG. 1B, a process of forming a first insulating layer 34 by depositing an insulating material on the entire surface of the resultant, and depositing and patterning polycrystalline silicon on the first insulating layer to form a resistor 36. Proceeds to.

Referring to FIG. 1C, a process of forming a second insulating layer 38 by depositing an insulating material on the entire surface of the resultant, forming a contact window by partially etching the first and second insulating layers, and forming a contact window on the entire surface of the resultant After the polysilicon has been deposited, photolithography is performed to form the electrode 40 and the emitter electrode 44 of the bipolar transistor connected to the source / drain regions, and to perform the photolithography process to mask the source / drain electrodes. Forming a photoresist pattern 46 and ion implanting an asce or an antimony Sb into the emitter electrode using the photoresist pattern as a mask.

Referring to FIG. 1D, a photolithography process is performed to form a photoresist pattern 48 for masking an emitter electrode, and a photoresist pattern is used as a mask to form a polysilicon layer 40 for source / drain electrodes. Proceeds to the step of ion implantation of P).

As described above, according to the conventional method of manufacturing a BiCMOS device, in order to manufacture a BiCMOS device while satisfying the electrical characteristics of the emitter region and the source / drain electrodes of the bipolar transistor, the polysilicon in contact with the emitter region of the bipolar transistor. Since the layer is injected with an asce (As) or antimony (Sb), and the polysilicon layer of the source / drain electrodes is injected with phosphorus (P), the process is complicated because the photo process is performed in duplicate, resulting in an increase in manufacturing cost. do.

Accordingly, it is an object of the present invention to provide a BiCMOS device capable of keeping the emitter region in a shallow junction without lowering the process and at the same time lowering the contact resistance of the source / drain electrodes.

Another object of the present invention is to provide a suitable manufacturing method for manufacturing the BiCMOS device.

A BiCMOS device for achieving the object of the present invention is an integrated circuit device comprising a MOS transistor and a bipolar transistor on the same semiconductor substrate,

An emitter electrode connected to the emitter region of the bipolar transistor on the semiconductor substrate and composed of polycrystalline silicon implanted with an N-type impurity having high destruction of a natural oxide film; And

A source / drain electrode connected to a source / drain region of an N-type MOS transistor on the semiconductor substrate and implanted with the same impurities as the emitter electrode, and formed of a polysilicon film having a thickness thinner than that of the emitter electrode. It characterized by having a.

According to a preferred embodiment of the present invention, it is preferable that the N-type impurity having a high natural oxide film destruction effect is phosphorus (P).

According to a preferred embodiment of the present invention, it is preferable that a high melting point silicide film is formed on the surface of the emitter electrode and the source / drain electrodes.

Method for manufacturing a BiCMOS device for achieving another object of the present invention,

Forming a first polysilicon layer on the semiconductor substrate;

Forming a emitter electrode of a bipolar transistor by etching the first polycrystalline silicon layer;

A third step of forming a second polysilicon layer on the resultant product on which the emitter electrode is formed;

Etching the second polysilicon layer to form a source electrode and a drain electrode connected to a source / drain region of a MOS transistor having a structure in which first and second polysilicon layers are stacked, and a second polycrystalline silicon layer 4th process;

A fifth step of ion implanting an N-type impurity having a high natural oxide film destruction effect into the second polycrystalline silicon layer; and

And a sixth step of heat-treating the semiconductor substrate.

In a preferred embodiment of the present invention, it is preferable to further include a step of forming a high melting point metal film or silicide of a high melting point metal on the second polycrystalline silicon layer after the third step.

It is preferable that the N-type impurity having high destruction effect of the natural oxide film is phosphorus (P).

According to another embodiment of the present invention, there is provided a method of manufacturing a bi CMOS device,

Forming a polysilicon layer on the semiconductor substrate;

Partially etching the polysilicon layer to form an emitter electrode of a bipolar transistor and a source / drain electrode of a MOS transistor;

A third process of partially etching the polysilicon layer of the source / drain electrode to reduce the thickness thereof;

And a fourth step of ion implanting an N-type impurity having high natural oxide film destruction effect into the polycrystalline silicon layer of the emitter electrode and the source / drain electrode; and a fifth step of heat treating the semiconductor substrate.

In a preferred embodiment of the present invention, it is preferable to further include a step of forming a high melting point metal film or silicide of a high melting point metal on the polycrystalline silicon layer after the first step.

It is preferable that the N-type impurity having high destruction effect of the natural oxide film is phosphorus (P).

According to the present invention, the contact resistance of the source / drain electrodes can be reduced, and the emitter region can be formed by a shallow junction.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings. 2 is a cross-sectional view of a BiCMOS device according to the present invention, FIGS. 3A to 4C are cross-sectional views for explaining a method of manufacturing a BiCMOS device according to an embodiment of the present invention, and FIGS. 5 and 6 are thicknesses of a polysilicon film. Is a graph for comparing the diffusion distance of phosphorus (P) to the silicon substrate. In the figures introduced subsequently, the same reference numerals as in FIGS. 1A-1D denote the same parts.

[rescue]

2 is a cross-sectional view showing a BiCMOS device according to the present invention, wherein reference numeral 10 is a semiconductor substrate, 12 and 14 are N-type and P-type buried layers, 16 and 18 are P-type and N-type wells, and Silver is the field oxide film, 22 is the gate insulating film, 24 is the gate electrode, 25 is the spacer, 26 and 28 the source and drain regions, 30 is the base region of the bipolar transistor, 32 is the collector region, 34,38 And 56 are insulating layers, 36 are resistors, 44 and 54 are emitter electrodes, 58 are emitter regions, 60 are impurity regions for lowering the contact resistance of the source / drain, and 62 are metal wirings, respectively. .

Referring to FIG. 2, the BiCMOS device of the present invention is connected to an emitter region of a bipolar transistor on a semiconductor substrate, and is composed of an emitter electrode 54 made of polycrystalline silicon implanted with N-type impurities having high destruction effect of a natural oxide film. And a source connected to a source / drain region of an NMOS transistor on the semiconductor substrate, the same impurities being injected into the emitter electrode, and composed of two types of polysilicon thinner than the polycrystalline silicon of the emitter electrode. / Drain electrode 52 is provided. Phosphorus (P) is preferable as an N-type impurity having a high destruction effect of the natural oxide film, and a silicide film of high melting point metal is preferably formed on the surface of the emitter electrode and the source / drain electrode.

According to the above structure, a shallow junction can be formed by increasing the thickness of the emitter electrode, so that the width of the base region can be shortened to achieve high speed, and high concentration impurities in the source / drain region connected to the source / drain electrode. Since the layer is formed, BiCMOS devices with low contact resistance can be realized.

[Manufacturing method]

3A to 4B, a method of manufacturing a BiCMOS device according to the present invention will be described with reference to a preferred embodiment.

Example 1

3A to 3D are cross-sectional views illustrating a method of manufacturing a BiCMOS device according to a first embodiment of the present invention.

The fabrication method according to the first embodiment of the present invention includes: (1) forming a device isolation film and a transistor, (2) forming a first conductive layer for an emitter electrode, (3) forming a second conductive layer for a source / drain electrode and an emitter electrode, and (4) N type impurity implantation into a conductive layer and (5) heat processing process are performed.

3A is a cross sectional view showing a step of forming a field oxide film 12 and a transistor on a semiconductor substrate.

Specifically, the first step of forming the N-type and P-type buried impurity layers 12 and 14 by injecting impurity ions into the semiconductor substrate 10 and then performing heat treatment, and a conventional epitaxial process is performed on the buried impurity layer. A second process of forming an epitaxial layer by using a third process of forming P-type and N-type wells 16 and 18 in the epitaxial layer, and for separating an element in an inactive region of the semiconductor substrate. A fourth step of forming the field oxide film 20, a fifth step of forming the thin gate oxide film 22 on the entire surface of the resultant, and conventional photolithography after depositing polysilicon doped with impurities, for example, on the gate oxide film A sixth step of patterning a process to form a gate electrode 24, a seventh step of depositing an insulating material on the resultant and then etching back to form a spacer 25 on the sidewall of the gate electrode, the gate electrode and the spacer And mask field oxide As a result, the process proceeds to the eighth step of forming the source / drain regions 26 and 28, the base region 30 and the collector region 32 of the bipolar transistor by ion implantation of N-type and P-type impurities into the semiconductor substrate, respectively. .

3B is a cross-sectional view showing the step of forming the resistor 36 and the first conductive layer 44 for the emitter electrode.

Specifically, in the first process of depositing an insulating material such as an oxide to form the first insulating layer 34 on the resultant formed gate electrode and the spacer, the first insulation of the region where the emitter electrode of the transistor is to be formed. A second process of etching the layer 34 to form a contact window for contact with the emitter region, and depositing and patterning, for example, polysilicon on the resultant to form the first conductive layer for the resistor 36 and the emitter electrode Proceeds to a third step of forming (44).

3C is a cross-sectional view illustrating the steps of forming the source / drain electrode 52 and the second conductive layer 54 for the emitter electrode and implanting the impurity ions.

Specifically, the first step of forming a second insulating layer 38 by depositing an insulating material, such as an oxide, on the resultant of FIG. 3B, and the second part of the portion where the source / drain electrode and the emitter electrode are to be formed. A second process of etching the insulating layer to form a contact window, a third process of depositing polysilicon on the resultant, and etching the polysilicon layer except for a portion where the source / drain electrode and the emitter electrode are to be formed. 4th process of forming the electrode 52 and the second conductive layer 54 for emitter electrodes to be connected to the drain, and the polysilicon layer having high destruction effect of the natural oxide film such as phosphorus (P), for example. It proceeds to the 5th process of ion implanting the impurity of a type | mold.

After the third process, the contact resistance may be further lowered by forming a silicide of a high melting point metal or a high melting point metal such as tungsten (W) on the polycrystalline silicon layer.

3d is a cross-sectional view showing the step of completing the BiCMOS device according to the present invention.

Specifically, the first step of forming the third insulating layer 56 by depositing an insulating material on the resultant of FIG. 3c, and performing a heat treatment process on the semiconductor substrate to emitter region 58 and high concentration impurity region ( The second process of forming 60 and the third process of forming metal wirings 62 to 70.

By the heat treatment process, impurities are diffused from the polysilicon layer for emitter electrode to form the emitter region 58, and impurities are diffused from the polysilicon layer 52 connected to the source / drain regions of the N-type transistor. A high concentration of impurity region 60 with low contact resistance is formed.

According to the first embodiment of the present invention, the emitter electrode is formed of a polysilicon layer thinner than the polysilicon layer of the source / drain electrode, so that the same impurities, the impurities implanted in the same process by the difference in the thickness of the polysilicon film, For example, in the subsequent heat treatment process, the impurity implanted into the thicker side by the thickness difference is less diffused into the silicon substrate to form a shallow impurity layer. In addition, by implanting phosphorus (P) having a high destruction effect of the natural oxide film, the contact resistance of the source / drain electrodes can be reduced.

Example 2

4A to 4C are cross-sectional views illustrating a method of manufacturing a BiCMOS device according to a second exemplary embodiment of the present invention, in which a polysilicon layer for source / drain electrodes is partially etched to reduce its thickness.

The manufacturing method according to the second embodiment of the present invention comprises the steps of: (1) forming a device isolation film and a transistor, (2) forming a conductive layer for source / drain electrodes and emitter electrodes, (3) etching part of the conductive layer for source / drain electrodes, and (④) N-type impurity implantation into the layer, and (5) heat treatment process.

4A is a cross-sectional view showing the step of forming the resistor 36. The first insulating layer 34 is formed in the same manner as in the first embodiment, and then the contact window is not formed. After depositing polysilicon on the insulating layer 34, it is patterned to form only the resistor 36.

4B is a cross-sectional view showing the steps of forming the polysilicon layers 52 and 53 for the source / drain and emitter electrodes.

Specifically, a process of forming a second insulating layer 38 by applying an insulating material on the resultant on which the resistor 36 is formed, and for connecting to the source region by etching the first and second insulating layers on the source region. Forming a contact window, applying polysilicon to the entire surface of the resultant, and then forming a photoresist pattern for masking the emitter electrode region by a general photolithography process; its thickness compared with the emitter electrode 53 Partially etching the polysilicon 52 of the source / drain electrode such that the thickness of the source / drain electrode is reduced, and impurities having a high destruction effect of the natural oxide film on the polycrystalline silicon layer for the emitter electrode 53 and the source / drain electrode 52, for example, The process of ion implanting phosphorus (P) and patterning the emitter electrode 53 and the source / drain electrode 52 by a normal photolithography process.

4C is a cross-sectional view of a state in which a BiCMOS is completed according to a second embodiment of the present invention. The process is subsequently performed in the same manner as in the first embodiment, and the interlayer insulating film 56 for planarization and the emi diffused by the thermal process The region 58 and the impurity region 60 and the metal wiring 62 are formed to diffuse from the source / drain electrodes of the N-type MOS transistor to lower the contact resistance.

In the second embodiment of the present invention, the low contact resistance of the source / drain electrode 52 in contact with the silicon substrate and the emitter region 58 of the bipolar transistor can be realized by a shallow junction.

5A and 5B are graphs for comparing the diffusion distance of phosphorus (P) diffused to the silicon substrate according to the thickness of the polysilicon film, and the same energy and the same impurities according to the thickness of the polysilicon film formed on the silicon substrate When ion implanted impurities (indicated by dashed lines) are diffused to silicon substrates by thermal processes (indicated by solid lines), the diffusion distances are different.

According to the BiCMOS device and the method of manufacturing the same according to the present invention, the contact resistance of the source / drain electrodes can be lowered by ion implantation of phosphorus (P) having a high destruction effect of the natural oxide film, and the polycrystal for emitter electrode of a bipolar transistor Emitters are diffused by heat treatment by forming a silicon layer thicker than that of the source / drain electrode polycrystalline silicon layer of the MOS transistor and simultaneously implanting phosphorus (P) having a high destruction effect of the natural oxide film. By shortening the diffusion distance of the impurities diffused from the polysilicon layer for electrodes, the junction of the emitter region can be formed shallow.

The present invention is not limited to the above embodiments, and many modifications are possible by those skilled in the art within the technical idea of the present invention.

Claims (8)

An emitter electrode connected to the emitter region of the bipolar transistor on the semiconductor substrate and composed of polysilicon implanted with N type impurities having high destruction of the natural oxide film; And a source / drain connected to a source / drain region of an N-type MOS transistor on the semiconductor substrate and having the same impurity as the emitter electrode, and having a thickness of the polysilicon film thinner than the polysilicon film of the emitter electrode. A bi CMOS device, comprising an electrode. The bi CMOS device according to claim 1, wherein the N-type impurity having a high natural oxide film destruction effect is phosphorus (P). The bi-MOS device according to claim 1, wherein a high melting point metal film or a silicide film of the high melting point metal is formed on surfaces of the emitter electrode and the source / drain electrodes. Forming a first polysilicon layer on the semiconductor substrate; Forming a emitter electrode of a bipolar transistor by etching the first polycrystalline silicon layer; A third step of forming a second polysilicon layer on the resultant product on which the emitter electrode is formed; Etching the second polysilicon layer to form a source electrode and a drain electrode connected to a source / drain region of a MOS transistor composed of an emitter electrode having a structure in which first and second polysilicon layers are stacked and a second polycrystalline silicon layer 4th process; A fifth step of ion implanting an N-type impurity having a high natural oxide film destruction effect into the second polysilicon layer; And And a sixth step of heat-treating the semiconductor substrate. The method of claim 4, further comprising, after the third step, forming a high melting point metal film or silicide of a high melting point metal on the second polycrystalline silicon layer. Forming a polysilicon layer on the semiconductor substrate; Partially etching the polysilicon layer to form an emitter electrode of a bipolar transistor and a source / drain electrode of a MOS transistor; A third process of partially etching the polysilicon layer of the source / drain electrode to reduce the thickness thereof; A fourth step of ion-implanting an N-type impurity having a high destruction effect of the natural oxide film on the polysilicon layer of the emitter electrode and the source / drain electrode; And a fifth step of heat-treating the semiconductor substrate. The method of claim 6, further comprising, after the first step, forming a high melting point metal film or silicide of a high melting point metal on the polycrystalline silicon layer. The method of manufacturing a bi-MOS device according to claim 4 or 6, wherein the N-type impurity having high destruction effect of the natural oxide film is phosphorus (P).