KR0151011B1 - A bipolar transistor and method of manufacturing the same - Google Patents

Abstract

Bipolar transistors and methods of manufacturing the same are described. A bipolar transistor according to the present invention includes a well of a first conductivity type, an emitter impurity layer formed at the center of the well, a base impurity layer formed to completely surround the emitter impurity layer, and a donut shape along an edge of the well. And a high concentration collector impurity layer of a first conductivity type formed at a predetermined interval from the base impurity layer. A first conductive layer formed in parallel with the high concentration collector impurity layer is connected to the high concentration collector impurity layer through a contact window, and the first conductive layer is connected to the collector electrode through another contact window. The simple manufacturing process reduces process time and cost, and improves reliability by eliminating parasitic bipolar transistor generation and increasing collector resistance.

Description

Bipolar Transistors and Manufacturing Method Thereof

1 is a cross-sectional view showing a BiCMOS manufactured by a conventional method.

2 is a cross-sectional view showing a bipolar transistor manufactured by another conventional method.

3a to 3c are schematic layouts according to embodiments of the present invention.

4A to 4C are cross-sectional views taken along line AA of FIG. 3A, line BB of FIG. 3B, and line CC of FIG. 3C, respectively.

5A to 5I are cross-sectional views illustrating a method of manufacturing a bipolar transistor according to a first embodiment of the present invention, and the AA line of FIG. 3A is cut out.

6A and 6B are cross-sectional views illustrating a method of manufacturing a bipolar transistor according to a second embodiment of the present invention, and the BB line of FIG. 3B is cut out.

7A and 7B are cross-sectional views illustrating a method of manufacturing a bipolar transistor according to a third embodiment of the present invention, and the CC line of FIG. 3C is cut out.

The present invention relates to a bi-MOSMOS and a method for manufacturing the same, and more particularly, to a bipolar transistor and a method for manufacturing the same, which solves a problem of deterioration in reliability due to the omission of a high concentration of buried and epitaxial layers.

By using bipolar transistors and MOS transistors in a single chip to complement and improve the advantages and disadvantages of each device, bi-MOS technology has been widely applied in the field of semiconductor memory.

For bisMOS manufacturing technology that optimizes the function of MOS transistors of bipolar transistors, various methods of manufacturing bipolar transistors have been proposed, including SIC (Selectively Ion Implanted Collector) and BEST (Base Electrode Surround Emitter Transistor) structures. Is a representative example. In particular, the process of forming a high concentration of buried layer and the epitaxial process is an essential process for a high performance bipolar transistor.

FIG. 1 is a cross-sectional view showing a BiCMOS manufactured by a conventional method, and performing an epitaxial process to form a bipolar transistor and a MOS transistor, and for reducing the sheet resistance of the collector and efficient isolation between the elements. This is the case where a high concentration of buried layer is formed under the field.

In FIG. 1, the left side of the figure shows a peripheral circuit region composed of a bipolar transistor, a PMOS transistor, and the like, and the right side of the figure shows a cell region of an SRAM composed of an NMOS, a high resistance polycrystalline silicon layer, and the like.

N-type and P-type high concentration buried layers (3 and 5 degrees) are selectively formed in the vicinity of the surface of the semiconductor substrate 1, and an epitaxial layer (epi.) Is formed thereon. The N-type well 7 is formed in an epitaxial layer located above the N-type heavily buried layer, and the P-type well 9 is formed in an epitaxial layer located above the P-type heavily buried layer. Bipolar transistors and PMOS transistors are formed insulated from each other in the N-type well, and NMOS transistors are formed in the P-type well. The bipolar transistor is formed of a collector impurity layer consisting of an N-type well 7 and a high concentration collector impurity layer 11, a base impurity layer 13, and an emitter impurity layer 15, wherein the high concentration collector impurity layer 11 is formed. ) Is connected to the N-type high concentration buried layer (3). The PMOS transistor is formed of a P-type source / drain region 17 and a gate electrode 25, and the NMOS transistor is formed of an N-type source / drain region 19 and a gate electrode 25. The high resistance polysilicon layer 29 of the SRAM is connected to either the source region or the drain region 19 of the NMOS transistor. The other of the emitter impurity layer 15 and the source and drain regions 19 of the NMOS transistor is connected to the electrodes 35 and 43, respectively, via the pad layers 23 and 31, respectively. The collector electrode 33 of the bipolar transistor is connected to the high concentration collector impurity layer 11, the base electrode 37 is connected to the base impurity layer 13, and the emitter electrode 35 is an emitter impurity layer ( 15 and the pad layer 23 are connected to each other. The source / drain electrodes 39 of the PMOS transistors are connected to the source / drain regions 17, respectively. At this time, reference numeral 21, which is not described, denotes a field oxide film, and 27 and 45 denote insulating layers.

By Sea Moss produced by the conventional method described above is a step of selectively forming a high concentration buried layer (3 and 5) on the surface of the semiconductor substrate for the production, the thickness of about 1㎛-2㎛ on the front surface A process of growing an epitaxial layer of (epi.), A process of forming an N-type or a P-type well in the epitaxial layer, and a process of forming bipolar transistors and MOS transistors in the wells.

After forming an N-type or P-well on a semiconductor substrate, a bi-MOS transistor is manufactured by comparing the CMOS manufacturing process with the bi-MOS manufacturing process described above. The process should further add a high concentration buried layer forming process and an epitaxial process as compared with a conventional CMOS manufacturing process. The high buried layer formation process and the epitaxial process are representative parts of the complicated process of making Bi CMOS manufacturing process. In the case of the epitaxial process, since the technology requires high precision, it also takes much time and cost.

Therefore, as a way to reduce the complexity of the process, and to reduce the process time and cost, the technique for manufacturing the bi-MOS by removing the high buried layer forming process and epitaxial process that was essential to the by- CMOS manufacturing technology Research has been conducted, which is a method of forming a bipolar transistor and a MOS transistor in a well formed directly on a semiconductor substrate.

FIG. 2 is a cross-sectional view showing a bipolar transistor manufactured by another conventional method, after forming an epitaxial layer on a semiconductor substrate, forming a well in the epitaxial layer, and forming elements in the well Unlike the conventional manufacturing method of the conventional method, a well is formed directly on a semiconductor substrate, and then a bipolar transistor is formed in the well.

FIG. 2 shows only bipolar transistors in bi-MOS, since the performance degradation in bipolar transistors is most severe when no high buried and epitaxial layers are formed. Although not shown, it can be assumed that MOS transistors are formed around the bipolar transistor.

After the impurity ions are selectively implanted into the P-type semiconductor substrate 50 to form the N-type and P-type wells 52 and 54, a field oxide film 62 is formed on the surface of the substrate by a selective thermal oxidation process. Subsequently, a high concentration collector impurity layer is formed by injecting N-type impurities at a high concentration into a region where the high concentration collector impurity layer 56 is to be formed, and then a P-type impurity layer 64 and a base impurity layer are selectively injected. Form 58. Subsequently, the impurity doped layer 60 is formed by diffusing impurities of the pad layer 70 in which the doped polycrystalline silicon and the silicide are laminated to the substrate, and the electrodes 72, 74, 76, and 78 are usually Form in the way.

According to the bipolar transistor manufacturing method according to another conventional method, compared with the conventional method, a high concentration buried layer forming process and an epitaxial process are omitted, so that the overall manufacturing process is simplified, and the effect of time and cost reduction can be expected. .

But. As a result, characteristic deterioration of the bipolar transistor becomes remarkable. Representative characteristic deterioration is listed as follows.

First, the effect of parasitic bipolar transistors becomes significant, which affects the operation of the bi-CMOS logic gate.

As shown in FIG. 2, the base impurity layer 58, the N-type well (which constitutes the collector impurity layer), and the P-type impurity layer 64 formed in the P-type well 54 (circuit configuration) of the bipolar transistor And any P-type impurity layer formed as necessary) form a PNP parasitic bipolar transistor.

Second, the collector resistance is increased, which slows down the operation speed of the device. The current passing through the emitter impurity layer 60 and the base impurity layer 58 is changed only in one direction, that is, from the base impurity layer 58 to the high concentration collector impurity layer 56 by the voltage applied to the collector electrode 72. As it flows, the resistance of the path through which the current flows is relatively high. In the case of the cross-sectional view shown in FIG. 1, the high concentration buried layer 3 could effectively form a low collector resistance.

Therefore, while the manufacturing process is simpler than the conventional method, there is a need for a bipolar transistor that does not cause problems such as an increase in collector resistance and generation of parasitic bipolar transistors.

An object of the present invention is to provide a bipolar transistor with a simple manufacturing process.

Another object of the present invention is to provide a bipolar transistor having a low collector resistance and capable of suppressing the operation of parasitic bipolar transistors.

It is still another object of the present invention to provide a suitable method for producing the bipolar transistor described above.

A bipolar transistor according to the present invention for achieving the above and other objects,

Well of a first conductivity type: Emitter impurity layer formed in the center of the well: Base impurity layer formed to completely surround the emitter impurity layer: And formed in a donut shape along the edge of the well, the base impurity layer Is characterized in that it comprises a high concentration collector impurity layer of the first conductivity type maintaining a constant interval.

In a preferred embodiment of the present invention, first contact windows connecting the high concentration collector impurity layer and the first conductive layer are formed on the high concentration collector impurity layer, wherein the first conductive layer is the high concentration collector. It is preferable to arrange | position in parallel with an impurity layer, and to form in the donut shape.

Preferably, the first conductive layer is formed of any one of polycrystalline silicon, polyside in which polycrystalline silicon and silicide are laminated, and a metal material.

In addition, the first conductive layer is connected to the second conductive layer through a second connection window, wherein the first conductive layer is formed of any one of polysilicon and polysilicon laminated with polycrystalline silicon and silicide, The second conductive layer is preferably formed of a metal material.

In another preferred embodiment of the present invention, the first conductive layer is disposed so as to partially parallel with the high concentration collector impurity layer, wherein the first conductive layer is preferably arranged in the form of c or =. .

In addition, a third contact window is formed on the high concentration collector impurity layer to be thermally connected with a third conductive layer, wherein the first conductive layer and the third conductive layer are partially connected to each other. The layer and the third conductive layer are preferably connected to each other by a fourth conductive layer formed on the third conductive layer.

In addition, when a third contact window is formed on the high concentration impurity collector layer and the third conductive layer is thermally formed, it is preferable that contact windows are also formed on the first conductive layer. .

Preferably, the third conductive layer is formed above the first conductive layer.

Preferably, the first conductive layer and the third conductive layer are formed of any one of polycrystalline silicon, a silicide in which polycrystalline silicon and silicide are overlapped, and a metal material. In this case, the first conductive layer is polycrystalline silicon, polycrystalline silicon, and silicide. Is preferably formed of any one of overlapping silicides, and the third conductive layer is formed of a metal material.

The bipolar transistor is preferably included in the bi-MOS.

In accordance with another aspect of the present invention, there is provided a method of manufacturing a bipolar transistor, including: forming a well of a first conductivity type in a semiconductor substrate: implanting a second conductivity type impurity into the center of the well; A second step of forming an impurity layer: a third step of forming a donut-shaped high concentration collector impurity layer surrounding the base impurity layer by injecting an impurity of a first conductivity type along the edge of the well; and in the base impurity layer And a fourth step of partially doping the first conductive type impurity to form an emitter impurity layer.

The well is partially implanted with phosphorus ions into the semiconductor substrate with an energy of about 100 keV, about 3.0 × 10 ¹³ ions / cm ² , and a heat treatment for about 12 hours at a temperature of about 1,150 ° C. in a nitrogen atmosphere. It is preferably formed.

The base impurity layer is preferably formed by implanting boron ions with an energy of about 30 keV and about 3.0 × 10 ¹³ ions / cm ² intentional wood.

The high concentration collector impurity layer is preferably formed by implanting phosphorus ions with an energy of about 100 keV and about 5.0 × 10 ¹⁵ ions / cm ² intentional wood.

The fourth step includes forming an insulating layer on a semiconductor substrate, forming a contact window for partially exposing the insulating layer to expose a region on which an emitter impurity layer is to be formed, and forming polysilicon on the resultant. It is preferable to proceed to the step of depositing, the step of injecting impurity ions into the polysilicon, the step of depositing silicide on the resultant, and the step of patterning the polysilicon and silicide.

At this time, the step of implanting the impurity ions, it is preferable to proceed to inject the acenic ions with energy of about 100keV, about 7.0 x 10 ¹⁵ ions / cm ² intended wood.

In the step of forming a contact window, the pad layer and the high concentration that are connected to the emitter impurity layer are formed by the step of forming a contact window, in which the high concentration collector impurity layer is partially exposed, and patterning polysilicon and silicide. It is preferable to further include simultaneously forming the first conductive layer to be connected to the collector impurity layer.

In a preferred embodiment of the present invention, after the step of forming the pad layer and the first conductive layer, the step of forming a second insulating layer on the resultant, by partially etching the second and first insulating layer Forming a contact window that partially exposes the base impurity layer, the pad layer, and the first conductive layer, depositing a second conductive material on the resultant, and patterning the second conductive material to connect with the base impurity layer It is preferable that the method further includes a step of forming a base electrode, an emitter electrode connected to the pad, and a collector electrode connected to the first conductive layer.

Preferably, the contact window partially exposing the high concentration collector impurity layer is one or more, and the first conductive layer is patterned to be parallel to the high concentration collector impurity layer to form a donut shape.

In addition, the first conductive material may be any one of polycrystalline silicon and polyside in which polycrystalline silicon and silicide are laminated, and the second conductive material layer is preferably a metal material.

In another preferred embodiment of the present invention, after the step of forming the pad layer and the first conductive layer, the step of forming a second insulating layer on the resultant, by partially etching the second and first insulating layer Forming a contact window that partially exposes the base impurity layer, the pad layer, and the high concentration collector impurity layer, depositing a third conductive material on the resultant, and patterning the third conductive material to connect with the base impurity layer It is preferable to further include the step of forming a base electrode, an emitter electrode connected to the pad layer, and a collector electrode connected to the high concentration collector impurity layer.

In this case, the first conductive layer may be formed to be partially disposed in parallel with the high concentration collector impurity layer, and the collector electrode may be formed to partially overlap the high concentration collector impurity layer.

In addition, the first conductive layer and the collector electrode are preferably formed to be connected to each other, wherein the first conductive layer and the collector electrode are preferably connected to each other by a third conductive layer formed above the collector electrode. .

The first conductive material may be any one of polycrystalline silicon and polyside in which polycrystalline silicon and silicide are laminated, and the second conductive material may be a metal material.

In another preferred embodiment of the present invention, after the step of forming the pad layer and the first conductive layer, the step of forming a second insulating layer on the resultant, partially etching the second and first insulating layer Forming a contact window that partially exposes the base impurity layer, the pad layer, the first conductive layer and the high concentration collector impurity layer, depositing a third conductive material on the resultant, and patterning the third conductive material. It is preferable to further include the step of forming the base electrode connected with the said base impurity layer, the emitter electrode connected with the pad layer, and the collector electrode connected with the said 1st conductive layer and the high concentration collector impurity layer.

In this case, the first conductive layer is preferably disposed in parallel with the high concentration collector impurity layer.

Therefore, according to the bipolar transistor and the manufacturing method thereof according to the present invention, in forming a bipolar transistor in a well formed directly on a semiconductor substrate, a high concentration collector impurity layer is formed so as to surround the base impurity layer in a donut shape, firstly, a high concentration By eliminating the buried layer forming process and the epitaxial process, time and cost were reduced due to the simplicity of the process. Second, by forming a high concentration collector buried layer around the base impurity layer, the problem of generation of parasitic bipolar transistor and increase of collector resistance was avoided. In order to solve this problem, a bi-MOS CMOS device, in which logic gate operation is normal but the operation speed of the device does not decrease, can be manufactured in a simple process similar to that of a CMOS process.

Hereinafter, with reference to the accompanying drawings will be described in more detail the present invention.

3A to 3C are schematic layout diagrams according to embodiments of the present invention.

3A to 3C, the region defined by the dotted line and the square shape is the base impurity layer region R1, and the region defined by the dotted line and the hollow square shape is the high concentration collector impurity layer region R2, The rectangular region defined by the solid line and hatched therein is a contact window region R3 for connecting the high concentration collector impurity layer to the first conductive layer, and the rectangular region defined by the dashed line and overlapping the R1 region is an emi. And a pad layer region R4 connected to the impurity layer, and defined by a single-dot chain line and overlapping the R2 region, are a first conductive layer region R5 connected to a high concentration collector impurity layer, and defined by a solid line. Two diagonally intersecting rectangular regions located within the region and intersecting therewith are contact window regions R6 for connecting the base electrode to the base impurity layer. And a rectangular area intersected with diagonal lines in the right side of the R6 region is a contact window region R7 for connecting the pad layer and the emitter electrode, and intersected in the rightmost region of the drawing. The rectangular area in which the diagonal line is drawn is a contact window area R8 for connecting the first conductive layer and the collector electrode, and the rectangular area including the R6 area therein is a base electrode area R9 defined by the double-dot chain line. , The rectangular region defined by the double-dotted line and including the R7 region therein is an emitter electrode region R10, and the rectangular region defined by the double-dotted line and including the R8 region therein is the collector electrode region R11. to be.

According to the layout of FIG. 3A, it can be seen that the concentration collector impurity layer and the first conductive layer surround the base impurity layer in a donut shape, and at least one contact for connecting the first conductive layer and the high concentration collector impurity layer. It can be seen that windows are formed throughout the high concentration collector impurity layer. In addition, the collector electrode may be connected to the high concentration collector impurity layer through the first conductive layer, and the collector electrode may be connected to the first conductive layer by contact windows formed on the first conductive layer. In addition, it can be seen that the collector electrode may be arranged in a predetermined shape in consideration of the arrangement of the base electrode and the emitter electrode or the arrangement of other peripheral electrodes.

According to the layout of FIG. 3b, the high concentration collector impurity layer surrounds the base impurity layer in a donut shape, and the first conductive layer partially surrounds the base impurity layer in the shape of c, unlike in FIG. 3a. It can be seen. One or more contact windows for connecting the first conductive layer and the high concentration collector impurity layer may be partially formed on the high concentration collector impurity layer, and the collector electrode may be formed to partially overlap the first conductive layer. have. In this case, it can be seen that the collector electrode is connected to the first conductive layer by a contact window formed on the first conductive layer and is also connected to the high concentration collector impurity layer by a contact window formed on the high concentration collector impurity layer. .

According to the layout diagram of FIG. 3C, the first conductive layer is formed in parallel with the high concentration collector impurity layer, and the collector electrode is perpendicular to the traveling direction of the first conductive layer at the edge of the first conductive layer. It can be seen that it is arranged.

Although not shown in the layout diagrams of FIGS. 3A to 3C, the R8 region disposed on the R5 region may be removed so that the first conductive layer and the collector electrode are not connected to each other. In this case, the first conductive layer and the collector electrode may be connected to each other through other contact windows (not shown).

According to the above-described layout diagrams, the current flowing from the emitter impurity layer to the collector impurity layer through the base impurity layer is different from the bipolar transistor shown in FIG. 2 as long as it is a region in which a high concentration collector impurity layer is formed. It can be seen that the resistance of the collector can be significantly lowered because it can flow in any direction.

4A to 4C are cross-sectional views taken along line AA of FIG. 3A, line BB of FIG. 3B, and line CC of FIG. 3C, respectively.

N-type wells 82 and P-type wells 84 are formed in the semiconductor substrate 80, and bipolar transistors are formed in the N-type wells. The high concentration collector impurity layer 102 is formed on both sides of the base impurity layer 106, and the emitter impurity layer 123 is formed in the base impurity layer. In this case, the high concentration collector impurity layer 102 is not shown in FIGS. 4A to 4C, but referring to FIGS. 3A to 3C, the base impurity layer 106 has a donut shape. It can be seen that it surrounds.

Referring to FIG. 4A, a first conductive layer 120 is formed on the entire surface of the high concentration collector impurity layer 102, and the first conductive layer 120 is formed through contact windows formed on the first conductive layer. ) And the collector electrode 136 are partially connected.

Referring to FIG. 4B, the first conductive layer 124 is formed on, for example, a c shape on one surface of the high concentration collector impurity layer 102, and the collector electrode 136 has the first conductive layer and the high concentration collector. The first conductive layer 124 and the high concentration collector impurity layer 102 are connected to each other through a contact window formed on the impurity layer 102 (see regions R5, R8, and R11 in FIG. 3B).

Referring to FIG. 4C, a first conductive layer (not shown) is formed on one surface of the high concentration collector impurity layer 102, for example, in a shape, and the collector electrode 136 has a high concentration of the first conductive layer. The first conductive layer and the highly concentrated collector impurity layer are connected to each other through a contact window formed on the collector impurity layer (see areas R5, R8, and R11 in FIG. 3C).

In this case, the first conductive layer and the collector electrode may be connected to each other through a contact window formed on the first conductive layer (see regions R8 of FIGS. 3B and 3C) and may be formed on the first conductive layer and the collector electrode. It may be connected to each other by different conductive layer materials.

The current of the bipolar transistor flows from the emitter impurity layer 123 to the high concentration collector impurity layer 102 through the base impurity layer 106 and through the base impurity layer. In this case, since the high concentration collector impurity layer 102 surrounds the base impurity layer 106 in a donut shape, current passing through the base impurity layer is scattered in all directions, and then collected in the high concentration collector impurity layer.

Therefore, according to the bipolar transistor according to the present invention, it is possible to solve the conventional problem in which the current flows in only one direction, thereby lowering the collector resistance.

Example 1

5A through 5I are cross-sectional views illustrating a method of manufacturing a bipolar transistor according to an exemplary embodiment of the present invention, and the AA lines of FIG. 3A are cut out.

The figures are depicted around a bipolar transistor applied to an SRAM device, in which the left portion of the figure shows the peripheral circuit region and the right portion of the figure shows the cell region (see FIG. 1).

First, FIG. 5A illustrates a first process of forming an N type well 82 and a P type well 84 using a conventional selective oxidation (LOCOS) process on a semiconductor substrate 80 and again a conventional selective oxidation process. As a result, the process proceeds to the second process of partially forming a field oxide film for device isolation on the surface of the semiconductor substrate.

In this case, the N-type wells 82 and P-type wells 84 have phosphorus ions of 100 keV of energy, 3.0 × 10 ¹³ ions / cm ^2, intentional wood and boron ions of 80 keV of energy, 2.0 × 10 ¹³ ions / cm ^2. After the injection into the intended wood, it is formed by heat treatment for about 12 hours in a nitrogen atmosphere, about 1,150 ℃ to diffuse into the semiconductor substrate.

In the figure, an N-type well on the left is a region where a PMOS transistor is to be formed, an intermediate N-type well is a region where an NPN bipolar transistor is to be formed, and a P-type well on the right is an region where an NMOS transistor is to be formed. At this time, the PMOS and bipolar transistors are the elements constituting the peripheral circuit region, and the NMOS transistors are the elements constituting the cell region.

FIG. 5B illustrates a process of forming gate electrodes of NMOS and PMOS transistors, which is a first process of implanting ions to adjust the threshold voltage of the transistor on the entire surface of the product on which the field oxide film 86 is formed. A second process of forming a gate oxide film in the second process, a third process of forming a gate electrode material by laminating polycrystalline silicon and tungsten silicide on the gate oxide film, and a process of forming the gate electrode 88 by patterning the stacked materials Proceed to 4 steps.

In this case, the gate electrode 88 is formed not only in the region where the gate electrodes of the PMOS and NMOS transistors are to be formed, but also in the region in which the bipolar transistor is to be formed. For example, the sidewall spacer formation process of a gate electrode, the ion implantation process of a MOS transistor, etc.). It is left to protect the surface of the semiconductor substrate.

FIG. 5C shows a process for forming low concentration sources / drains of NMOS and PMOS transistors, in which N-type impurity ions such as phosphorus (P) ions, for example, energy of 40 keV, 3.0 × 10 ¹³ ions / The first step of forming a low concentration source / drain 94 of the NMOS transistor by injecting into an intentional cm ² and a P-type impurity ion such as, for example, boron difluoride (BF 2) ion, is applied only to the region where the PMOS transistor is to be formed. Is injected into the intended energy of 4.4 × 10 ¹³ ions / cm ² to proceed to the second step of forming a low concentration source / drain 92 of the PMOS transistor.

At this time, it is seen that the source / drain of the lightly doped drain (LDD) structure is formed of a fully-concentrated impurity layer formed on the gate electrode and a highly-concentrated impurity layer formed on the spacer formed on the sidewall of the gate electrode. Those skilled in the art will clearly know.

5d illustrates a process of forming the spacers 96 on the sidewalls of the gate electrode 88, which is a first process of forming an insulating film, such as silicon dioxide, on the entire surface of the resultant source having the low concentration source / drain, and The insulating layer is anisotropically etched to form a spacer 96 on the sidewall of the gate electrode 88.

FIG. 5E illustrates a process of forming the low concentration base impurity layer 90, which is formed by applying and patterning a material such as a photoresist onto the entire surface of the spacer 96 on which the bipolar transistor is formed. The first process of forming the pattern 100 exposing only the region to the surface, the second process of removing the gate electrode material formed on the region where the bipolar transistor is to be formed and the entire surface of the resultant, for example, boron difluoride (BF ₂ ) The P-type impurity is injected into a 30keV energy, 3.0 × 10 ¹³ ions / cm ² intentional wood, and the third process is performed to form a low concentration base impurity layer 90.

5F shows a process of forming a high concentration collector impurity layer 102, a base impurity layer 106, a source / drain 98 of an LDMOS NMOS transistor and a source / drain 104 of an LDD PMOS transistor. As a result, this is because after removing the pattern 100, the N-type impurity ions such as phosphorus ions are transferred to a 100 keV energy, 5.0 × 10 ¹⁵ ions / cm ² intentional area in the region where the high concentration collector impurity layer 102 is to be formed. Implanting to form the high concentration collector impurity layer 102, and in the region where the PMOS transistor is to be formed and a portion of the base impurity layer, a P-type impurity ion such as boron difluoride (BF2) ion is energy of 30 keV, 5.0 x 1015. P-type impurity ions such as boron difluoride (BF ₂ ) ions are implanted into the high concentration collector impurity layer 102 by implanting into a dose of ions / cm 2, and in a region where the PMOS transistor is to be formed and a part of the base impurity layer. 30keV energy . Implanted with a dose of 5.0 × 10 ¹⁵ ions / cm ² to form the base impurity layer 106 and the PMOS source / drain 104 of the LDD structure, and an N-type impurity such as anacean in the region where the NMOS transistor is to be formed. The ions are implanted with an energy of 40 keV and 5.0 x 10 ¹⁵ ions / cm ² intentional wood to form an NMOS source / drain 98 having an LDD structure.

In this case, the high concentration collector impurity layer 102 is formed so as to surround the low concentration base impurity layer 90 in a donut shape as described in the layout diagrams (region R2) shown in FIGS. 3A and 3B. .

In the region where the high concentration collector impurity layer 102 is to be formed, P-type impurity ions are implanted at a predetermined concentration by the process described in FIG. 5E, but the concentration is ion implantation for forming the high concentration collector impurity layer. Since the amount is smaller than the concentration of the impurity ions used at the time, there is no problem in forming the high concentration collector impurity layer 102.

5g illustrates a process of forming the high-resistance polysilicon layer 110, which is a first step of removing the fifth ion implantation prevention layer, and an insulating layer such as silicon dioxide is deposited on the entire surface of the resultant, for example. A second process of forming 108, a third process of depositing a material such as polysilicon or amorphous silicon to a thickness of about 500 GPa on the entire surface of the resultant, and a first photo for forming a high-resistance polysilicon layer The method proceeds to a fourth process of forming the polysilicon layer 110 of the fixed term by feathering the material by a photolithography process using the resist pattern 112.

In this case, the polysilicon layer 110 of the fixed term is included in the SRAM cell, and is shown to show a process of simultaneously forming the peripheral circuit region and the cell region.

FIG. 5h illustrates a process of forming the emitter impurity layer 123, the first conductive layer 120, the first pad layer 122, and the second pad layer 118, which is the first photoresist pattern. First step of removing the second step of forming a first insulating layer 114 (shown in combination with the insulating layer 108 formed in FIG. 5g) by coating an insulating material such as silicon dioxide on the entire surface of the resultant A third process of partially removing the first insulating layer on the source or drain 98 of the high concentration collector impurity layer 102, the base impurity layer 106 and the NMOS to form a contact window, for example on the entire surface of the resultant After depositing a material such as silicon to a thickness of about 1,000 Å, for example, the fourth step of injecting N-type impurity ions such as acenic ions into an energy of 100 keV, 7.0 × 10 ¹⁵ ions / cm ² intentional wood, On the polysilicon implanted, for example tungsten silicide A fifth step of laminating silver silicide, and a first pad layer 120 connected to the high concentration collector impurity layer 102 by patterning the stacked polysilicon and tungsten silicide and a second pad layer connected to the source or drain of the NMOS. Proceeding to the sixth step of forming 118.

In this case, the first conductive layer 120 is disposed in parallel with the high concentration collector impurity layer 102 surrounding the base impurity layer 106 in a donut shape (see R5 region in FIG. 3A), and the first conductive layer. One or more contact windows for connecting the high concentration collector impurity layer are formed on the entire high concentration collector impurity layer 102, as in the region R3 shown in FIG. 3A.

In addition, the emitter impurity layer 123 is formed by diffusion of impurity ions injected into the polysilicon layer into the semiconductor substrate, and the first pad layer 122 is included in the first conductive layer 120 (third a). (Refer to region R4 in FIG.).

When the first conductive layer 120 is formed at the same time as the step of forming the first pad layer 122, as described above, polysilicon having a form in which polycrystalline silicon and silicide are laminated or (in the case of the present invention) ) It is composed of polycrystalline silicon, but when formed separately from the first pad layer forming process, it can be formed of a metal material such as aluminum, of course.

As a material constituting the first conductive layer 120, when the polycrystalline silicon doped with impurities is used, the high concentration collector impurity layer 102 diffuses impurities doped in the polycrystalline silicon, thereby increasing its concentration. .

FIG. 5i illustrates a process of forming electrodes, which is a first process of forming a second insulating layer 126 by applying an insulating material such as silicon dioxide on the entire surface of the resultant, a first process on a region where an electrode is to be formed. And a second process of forming a contact window by partially removing the second insulating layer, and depositing a metal material such as aluminum, for example, on the entire surface of the resultant, and then patterning the source / drain electrode 128 of the PMOS, and the NMOS. The third process is to form the source or drain electrode 138, the base electrode 132, the emitter electrode 134, and the collector electrode 136.

In this case, the base electrode 132, the emitter electrode 134, and the collector electrode 136 are disposed to correspond to the regions R9, R10, and R11 shown in the layout diagram of FIG. 3A.

On the other hand, the collector electrode 136 is connected to the high concentration collector impurity layer 102 through a contact window formed on the first conductive layer, wherein the first conductive layer is random depending on the arrangement of the base electrode and the emitter electrode. It may be arranged in the shape of. In the case of FIG. 3A, the rods were arranged in the shape of long rods parallel to the emitter electrode and the base electrode.

Example 2

6A and 6B are cross-sectional views illustrating a method of manufacturing a bipolar transistor according to another exemplary embodiment of the present invention, and the BB line of FIG. 3B is cut out.

FIG. 6A illustrates a process of forming the first conductive layer 124, which proceeds to the second process of FIG. 5h, and then the high concentration collector impurity layer 102, the region where the emitter impurity layer is to be formed, and the NMOS. A first step of forming a contact window by partially removing the first insulating layer on the source or drain, and performing the fourth and fifth steps of FIG. 5h on the entire surface of the resultant, and then patterning the stacked polyside The first conductive layer 124 connected to the high concentration collector impurity layer on one side of the high concentration collector impurity layer 102, the first pad layer 122 connected to the emitter impurity layer 123, and the source or drain of the NMOS. It proceeds to the 2nd process of forming the 2nd pad layer 118 connected with 98.

In this case, unlike the first conductive layer 120 of FIG. 5h, the first conductive layer 124 is disposed in parallel with the high concentration collector impurity layer, that is, in a c-shape (R5 region of FIG. 3b). Reference). Therefore, a contact window for connecting the high concentration collector impurity layer 102 and the first conductive layer 124 is formed only on one surface of the high concentration collector impurity layer (see R3 region in FIG. 3b).

The first conductive layer 124 is preferably composed of one of polysides and polycrystalline silicon, and may be formed of a metal material when the first conductive layer forming process is not parallel to the first pad layer 122 forming process. have.

FIG. 6B illustrates a process of forming electrodes, which proceeds to the first process of FIG. 5I, and then partially etches the first and second insulating layers to form a source / drain 1040 (first conductive layer) of the PMOS. 124, a first process of forming a contact window on the first pad layer 122, the high concentration collector impurity layer 102, and the source or drain 98 of the NMOS, and a metal such as, for example, aluminum on the entire surface of the resultant. Depositing and patterning the material to form a source / drain electrode 128, a base electrode 132, an emitter electrode 134, a collector electrode 136, and a source or drain electrode 138 of the NMOS; The process proceeds.

In this case, the collector electrode 136 is connected to the first conductive layer 124 through a contact window (not shown) formed on the first conductive layer (region 3 in FIG. 3b R8) and formed on the high concentration collector impurity layer. It is also connected to the high concentration collector impurity layer 102 through a contact window (region R8 in FIG. 38).

The collector electrode may be formed without being connected to the first conductive layer. In this case, it is not necessary to form a contact window for connecting the collector electrode and the first conductive layer to each other.

In addition, in the above-described case in which the collector electrode and the first conductive layer are not connected, they may be connected to each other through another contact window, for example, a contact window formed on each of the first conductive layer and the collector electrode.

Example 3

7A and 7B are cross-sectional views illustrating a method of manufacturing a bipolar transistor according to a third embodiment of the present invention, and the CC line of FIG. 3C is cut out.

In the case of the third embodiment, when the first conductive layer (not shown) is formed in the shape of =, all the processes except the process of patterning the first conductive layer are the same as those of the second embodiment.

Therefore, according to the bipolar transistor and the manufacturing method thereof according to the present invention, first, by forming the well directly on the semiconductor substrate, it is possible to simplify the manufacturing process than the conventional method by removing the high concentration buried layer forming process and epitaxial process ( Process is very similar to CMOS manufacturing process). Process time and cost savings can be expected. Second, by forming the high concentration collector impurity layer so as to surround the base impurity layer in a donut shape, it is possible to solve the problem of generation of parasitic bipolar transistor and increase of collector resistance.

In the present specification, a bipolar transistor and a method of manufacturing the same are described in the manufacture of bi-MOS transistors, but the technology of the present invention can be widely applied to the case of forming the bipolar transistor alone or in other cases.

Claims (34)

Well of a first conductivity type: Emitter impurity layer formed in the center of the well: Base impurity layer formed to completely enclose the emitter impurity layer: And formed in a donut shape along the edge of the well, the base impurity layer And a high concentration collector impurity layer of a first conductivity type which maintains a constant interval therebetween. The bipolar transistor of claim 1, further comprising a plurality of first contact windows formed on the high concentration collector impurity layer. The bipolar transistor of claim 2, further comprising a first conductive layer electrically connected to the high concentration collector impurity layer through the first contact windows and disposed in a donut shape to be parallel to the high concentration collector impurity layer. . The bipolar transistor of claim 3, wherein the first conductive layer is formed of any one of polycrystalline silicon, polyside in which polycrystalline silicon and silicide are stacked, and a metal material. The bipolar transistor of claim 3, further comprising a second conductive layer electrically connected to the first conductive layer through a second connection window formed on the first conductive layer. 6. The bipolar transistor according to claim 5, wherein the first conductive layer is formed of any one of polycrystalline silicon and polyside in which polycrystalline silicon and silicide are laminated, and the second conductive layer is formed of a metal material. 3. The bipolar of claim 2, further comprising a first conductive layer electrically connected to the high concentration collector impurity layer through the first contact windows, the first conductive layer being disposed only in parallel with the high concentration collector impurity layer. transistor. 8. The bipolar transistor according to claim 7, wherein the first conductive layer is arranged in any one of = and c. The bipolar transistor according to claim 7, further comprising a third conductive layer electrically connected to the high concentration collector impurity layer through a third contact window formed on the high concentration collector impurity layer. The bipolar transistor according to claim 9, wherein the first conductive layer and the third conductive layer are partially connected. The bipolar transistor of claim 10, further comprising a fourth conductive layer electrically connecting the first conductive layer and the third conductive layer formed on the third conductive layer. The bipolar transistor of claim 10, further comprising contact windows formed on the first conductive layer and electrically connecting the first conductive layer and the third conductive layer. The bipolar transistor according to claim 9, wherein the third conductive layer is formed above the first conductive layer. 10. The bipolar transistor of claim 9, wherein the first conductive layer and the third conductive layer are formed of any one of polycrystalline silicon, a polyside overlapping polysilicon and silicide, and a metal material. The method according to any one of claims 9 to 13, wherein the first conductive layer is formed of any one of polycrystalline silicon and polyside in which polycrystalline silicon and silicide are overlapped, and the third conductive layer is formed of a metal material. A bipolar transistor, characterized in that. The bipolar transistor of claim 1, wherein the bipolar transistor is included in a bi-MOS. A first step of forming a well of a first conductivity type on a semiconductor substrate. A second step of forming a base impurity layer by injecting a second conductivity type impurity into a center portion of the well. A third step of forming a donut-shaped high concentration collector impurity layer surrounding the base impurity layer and surrounding the base impurity layer by implanting impurities; and partially doping a first conductive type impurity to the base impurity layer And a fourth step of forming an emitter impurity layer. 18. The method of claim 17, wherein the well is partially implanted with phosphorus ions into the semiconductor substrate with an energy of about 100 keV, about 3.0 x 10 ¹³ ions / cm ² , and a nitrogen atmosphere at a temperature of about 1,150 ° C for 12 hours. Transistor manufacturing method characterized in that formed by a step of heat treatment. 18. The method of claim 17, wherein the base impurity layer is formed by implanting boron ions with an energy of about 30 keV and a dose of about 3.0 x 10 ¹³ ions / cm ² . 18. The method of claim 17, wherein the high concentration collector impurity layer is formed by implanting phosphorus ions with a dose of energy of about 100 keV and a dose of about 5.0 x 10 ¹⁵ ions / cm ² . 18. The method of claim 17, wherein the fourth step comprises: forming an insulating layer on the semiconductor substrate; and forming a contact window exposing the surface on which the emitter impurity layer is to be formed to the surface by partially etching the insulating layer. And fabricating polycrystalline silicon on the resultant, injecting impurity ions into the polysilicon, depositing silicide on the resultant, and patterning the polysilicon and silicide. Way. 22. The bipolar transistor fabrication method of claim 21, wherein the implanting of impurity ions proceeds with implanting an ionic ion with an energy of about 100 keV and a dose of about 7.0 x 10 ¹⁵ ions / cm ² . Way. 22. The method according to claim 21, wherein in the step of forming a contact window, the contact window, in which the high concentration collector impurity layer is partially exposed, is also formed, and the polycrystalline silicon and silicide are patterned to connect with the emitter impurity layer. And forming a pad layer and a first conductive layer connected to the high concentration collector impurity layer simultaneously. 24. The method of claim 23, after the step of forming the pad layer and the first conductive layer, the step of forming a second insulating layer on the resultant, the second and first insulating layer by partially etching the base impurity layer Forming a contact window for partially exposing the pad layer and the first conductive electrode, depositing a second conductive material on the resultant, and a base electrode connected to the base impurity layer by patterning the second conductive material; And forming a emitter electrode connected to the pad and a collector electrode connected to the first conductive layer. 24. The method of claim 23, wherein the contact window that partially exposes the high concentration collector impurity layer is one or more. 24. The method of claim 23, wherein the first conductive layer is patterned to be parallel to the high concentration collector impurity layer to form a donut shape. 25. The method of claim 24, wherein the first conductive material is any one of polycrystalline silicon and polyside laminated polysilicon and silicide, and the second conductive material layer is a metal material. 24. The method of claim 23, after the step of forming the pad layer and the first conductive layer, the step of forming a second insulating layer on the result, the second and first insulating layer by partially etching the base impurity layer Forming a contact window for partially exposing the pad layer and the high concentration collector impurity layer, depositing a third conductive material on the resultant, and a base electrode connected to the base impurity layer by patterning the third conductive material; And forming a emitter electrode connected to the pad and a collector electrode connected to the high concentration collector impurity layer. 29. The method of claim 28, wherein the first conductive layer is formed so as to be disposed in parallel with the high concentration collector impurity layer. 29. The method of claim 28, wherein the first conductive layer and the collector electrode are formed to be connected to each other. 31. The method of claim 30, wherein the first conductive layer and the collector electrode are connected to each other by a conductive layer formed above the collector electrode. 29. The method of claim 28, wherein the first conductive material is any one of polysilicon and a polyside in which polycrystalline silicon and silicide are laminated, and the second conductive material is a metal material. 24. The method of claim 23, after the step of forming the pad layer and the first conductive layer, the step of forming a second insulating layer on the resultant, the second and first insulating layer by partially etching the base impurity layer Forming a connection window partially exposing the pad layer, the first conductive layer, and the high concentration collector impurity layer, depositing a third conductive material on the resultant, and patterning the third conductive material to form the third impurity layer; And forming a base electrode to be connected, an emitter electrode to be connected to the pad layer, and a collector electrode to be connected to the first conductive layer and the high concentration collector impurity layer. 34. The method of claim 33, wherein the first conductive layer is formed to be disposed in parallel with the high concentration collector impurity layer.