JP2697631B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device.
Respect law, in particular, a semiconductor comprising Ba Lee Paula transistor
The present invention relates to a device manufacturing method .

[0002]

2. Description of the Related Art In recent years, the speed and performance of bipolar transistors, especially NPN transistors, have been remarkably improved. In measuring instruments and memory testers,
Higher speeds are required in response to higher performance of semiconductor devices. As the speed and performance of NPN transistors increase, there is a growing demand for higher speed and higher performance of PNP transistors used in complementary (complementary) circuits with NPN transistors.

However, at present, the speed of the PNP transistor has not been advanced as much as the NPN transistor. As is well known, a transition frequency (Tr
there is ansition frequency) f _T. The parameters governing f _T are (i) the speed of the minority carrier traveling through the base, and (ii) the base width or depth of the emitter and base junction. First, the minority carrier in the base of the PNP transistor is a hole (hole). Therefore, the number of minority carriers in the base of the PNP transistor is smaller than that of the NPN transistor using electrons as the minority carrier. Second, because the carrier movement speed is physically low, and secondly, the controllability of the base width has not been considered as much as in the case of the NPN transistor.
It is difficult to realize a narrow base width and a shallow junction. These factors are the main reasons why the speed of the PNP transistor cannot be increased. The second of the factors mentioned here is a problem relating to the structure and manufacturing method of the device, and the present invention also deals with this problem.

FIGS. 7 (a) and 7 (b) are schematic cross-sectional views showing a configuration example of a vertical PNP transistor and a vertical NPN transistor according to the prior art, respectively. Hereinafter, in this specification, a transistor is a vertical transistor unless otherwise specified.

In the PNP transistor shown in FIG. 7A, a P-type epitaxial layer 62 is grown on a P-type substrate 61, and an N-type base region 64 is selectively formed. It is manufactured by forming the mold emitter region 65. An insulating film 63 is provided on the surface other than the portion that becomes the contact hole.

On the other hand, the outline of the method of manufacturing the NPN transistor shown in FIG. 7B is as follows. That is, first, N
Growing an N-type epitaxial layer 67 on the mold substrate 66;
A P-type base region 68 is selectively formed, and thereafter, a contact 71 is opened in the insulating film 63. Then, for example, after growing a polysilicon layer 70 doped with arsenic (As), the polysilicon layer 70 is selectively etched except for a portion to be an emitter, and a P-type base region is formed by annealing at a high temperature. An N-type emitter region 69 is formed in 68.

The N manufactured by this series of processes
In the PN transistor, the polysilicon layer 7 described above is used.
The presence of 0 is very important in improving characteristics.
The reason will be described below. First, the presence of the polysilicon layer (or also referred to as due to the influence of the oxide film present at the interface between the silicon substrate) by, for injection efficiency from the emitter to the base is increased, the DC current amplification factor h _FE Is easy to improve. Therefore, when the same h _FE (for example, 80) is to be obtained, annealing can be performed in a shorter time than when no polysilicon layer is provided.
This is because a shallower junction, that is, a narrower base width can be realized. Second, since the emitter opening in the oxide film is covered with the polysilicon layer, an emitter electrode (made of Al and its alloy, Au or the like) to be formed on this opening is separated from the emitter junction. This is because the junction breakdown of the emitter can be prevented. If there is no polysilicon layer in the emitter opening, the shallower the junction, the more likely it is that the emitter will break down. That is, by providing a polysilicon layer doped with an N-type impurity such as As in the emitter opening, an extremely shallow emitter junction can be easily and stably formed, and both improvement in characteristics and improvement in reliability can be achieved.

On the other hand, as shown in FIG.
In the NP transistor, a polysilicon layer containing a P-type impurity does not exist on the P-type emitter region 65. The reason for this is that boron (B) is used as a dopant for the P-type emitter region of the PNP transistor in terms of solid solubility and the like. However, compared to polysilicon not doped with impurities, boron-doped polysilicon is used. The layer has the characteristic that the etching rate is extremely slow. For the formation of the polysilicon layer over the emitter opening in an NPN transistor, in situ doped DOPOS (Dope
d Polysilicon) and ion-implanted polysilicon are adopted, but if these methods are applied to PNP transistors, the polysilicon layer cannot be processed practically. A polysilicon layer cannot be provided in the emitter opening. Therefore, for a reason completely opposite to the case where the As-doped polysilicon layer is provided in the above-described NPN transistor, a shallow junction cannot be formed in the PNP transistor, and therefore, a high speed operation cannot be achieved.

[0009] When an attempt is made to constitute a complementary circuit on an integrated circuit, even can be realized 10~20GHz as for example f _T for the NPN transistor,
On the PNP transistor side, only f _{T of} about 1 to 4 GHz can be realized at most, and only a far from a true complementary circuit can be obtained. In addition, the above-mentioned vertical PNP
In addition to the transistor, there is a lateral PNP transistor (lateral PNP transistor). In the lateral PNP transistor, carriers move in the lateral direction with respect to the substrate surface. Characteristics, which are far inferior to vertical PNP transistors (f _T is about 5 MHz)
Can only be realized. Techniques for improving the problems of the conventional complementary circuit are disclosed in, for example, JP-A-59-113658, JP-A-60-65566, and JP-A-63-18671.

[0010]

However, according to the techniques disclosed in these publications, it is impossible to improve the characteristics of the PNP transistor to be comparable to those of the NPN transistor and to realize a true complementary circuit. First, the technique disclosed in JP-A-59-113658 is to form a lateral NPN transistor and a vertical PNP transistor in P-type epitaxial layer on an n-type substrate, both of the transistors of f _T Although the difference is small, the overall speed cannot be increased. JP 6
In 0-65566 discloses faster technique of the lateral PNP transistor is disclosed, it can actually be realized f _T
It is at most about ten and several MHz. Also, JP-A-63-
In the technique disclosed in Japanese Patent No. 18671, a P-type layer serving as an emitter region of a PNP transistor is formed with N
It is characterized in that it is formed shallower than the P-type layer serving as the base region of the PN transistor. However, as is clear from the above description, reliability problems such as emitter junction destruction and h.
There is naturally a limit in that _FE cannot be improved,
It is difficult to achieve a sufficiently high speed.

An object of the present invention is to realize a PNP transistor which is truly high speed and has high reliability, and realizes a complementary circuit or an integrated circuit using the PNP transistor.

[0012]

Means for Solving the Problems The semiconductor device of the present invention
A first manufacturing method is a semiconductor having a PNP transistor.
In the method of manufacturing the device, the N
Undoped polysilicon layer over the mold region
And forming a P-type impurity over the polysilicon layer.
Forming a film containing a material, a polysilicon layer and a P-type
PNP transistors by selectively removing the film containing impurities
Process into the shape of the emitter electrode of the
The P-type impurity in the film containing the P-type impurity
Diffusion into the N-type region through the recon
Forming a p-type emitter region of the transistor.

[0013]

[0014]

[0015]

According to a second method of manufacturing a semiconductor device of the present invention,
Forming a N-type area to the selected択的the P-type substrate, prior to
A step of growing a polysilicon layer not doped with impurities on the serial N-type region, said covering the polysilicon layer
A step of growing a film containing P-type impurities, by performing heat treatment after row Tsu Na etching the film containing selectively the polysilicon layer and the P-type impurity, the P-type impurity of
P-type impurities in a film containing a substance through the polysilicon layer
Forming a P-type region and to diffuse into the region of the N type
And a process.

According to a third method of manufacturing a semiconductor device of the present invention,
Forming an N-type first region on a P-type substrate,
Type region selectively formed, in the manufacturing method of a semiconductor integrated circuit for selectively forming a second region of the further N-type in the region of the P type selectively formed, N-type second of after the formation of the region, and growing a poly-silicon layer not doped with impurities on the entire surface, and selectively forming a film containing P-type impurities into port <br/> Rishirikon layer, N-type a step of impurity ions implanted into the port Rishirikon layer of selectively removing the polysilicon layer to leave, either with on-implanted polysilicon layer which receives the portion immediately below the film containing P-type impurities Heat treatment, and diffusion from the polysilicon layer in a portion immediately below the film containing the P- type impurity.
Alternatively Te in P-type region and a step of forming a diffusion region of the P-type impurity.

[0018]

According to the present invention, a polysilicon layer not doped with impurities and a film containing boron are laminated, and after patterning is performed in this state, heat treatment is performed to diffuse boron into the patterned polysilicon layer. At the same time, boron is diffused into the N-type region of the semiconductor to form a P-type region. The film containing boron on the polysilicon layer is used as a boron diffusion source. Thus, in the case of a PNP bipolar transistor, since the emitter region is covered with the boron-doped polysilicon layer, h _FE
As a result, a shallow junction can be achieved, and high speed can be achieved, and the reliability of the emitter junction can be improved. In the present invention, the polysilicon layer is patterned at a stage where boron is not doped, and then boron is diffused.
Boron-doped polysilicon solves the problem that processing is difficult.

[0019]

Next, an embodiment of the present invention will be described with reference to the drawings.

Embodiment 1 This embodiment is an example of a single PNP transistor according to the present invention. This PNP
2A and 2B and FIG.
(a) and (b) are shown in order.

First, a P-type substrate 1 having a high impurity concentration is used, a P-type epitaxial layer 2 is grown on one surface of the P-type substrate 1, and an isolation oxide film 3 is selectively formed.
As a result, the cross-sectional shape of P-type epitaxial layer 2 becomes trapezoidal, and first insulating film 4 continuous with isolation oxide film 3 is provided on the top surface. Thereafter, a photoresist 5 is applied, the photoresist 5 is selectively opened at a portion corresponding to the top surface portion of the P-type epitaxial layer 2, and the opening of the photoresist 5 and the first insulating film exposed at the bottom thereof are exposed. N-type impurities (N-type dopant ions) are ion-implanted into the P-type epitaxial layer 2 through the film 4 to form an N-type region 6 serving as a base of the PNP transistor (FIG. 1A). As ions to be implanted, for example, arsenic (As) is used, and implantation conditions are, for example, an acceleration voltage of 50 KeV and an implantation amount of 6 × 10 ¹³ cm ⁻² .

Subsequently, a second insulating film 7 is formed on the entire surface,
Thereafter, an emitter contact 8 and a base contact 9 are opened in the second insulating film 7 and the first insulating film 4. At this time, the N-type region 6 is exposed at the bottom of the emitter contact 8, but the first insulating film 4 is left at the bottom of the base contact 9. Here, the second insulating film 7
Is aimed at the surface passivation effect of the nitride film or the like, and by providing this, it is possible to improve the moisture resistance and the like. However, even if the second insulating film 7 is not provided, the present invention It does not impair the effect. Then, a polysilicon layer 10 to which no impurity is added is grown on the entire surface, and a boron-doped film 11 is further formed (FIG. 1B). Here, the boron-doped film 11 is a film containing boron as a diffusion source.
G (Borosilicate Glass) or PBF (Poly-Boron-Film)
Can be used. The boron concentration in the film is 3-4 ×
It suffices if it is at least 10 ¹⁹ atoms cm ^-3 . Polysilicon layer 10
May be 100 to 400 nm, and the thickness of the boron-doped film 11 may be about 50 to 300 nm. However, the thickness is not limited thereto. It can be determined in consideration of annealing conditions and desired characteristics (breakdown voltage, h _FE , high frequency characteristics). The polysilicon layer 10 may be formed by a normal method, or may be obtained by annealing an amorphous silicon layer to make it polycrystalline.

Next, a photoresist 12 is applied to the entire surface, and the photoresist 12 other than the portion on the emitter contact 8 is selectively removed by a photolithography process. Then, using the remaining photoresist 12 as a mask, the boron doped film 11 and the polysilicon layer 1 are formed.
0 is etched [FIG. 2 (a)]. At this time, since the first insulating film 4 remains at the bottom of the base contact 9, the N-type region 6 is not etched through the base contact 9.

After removing the photoresist 12, 950 is removed.
Annealing at ~ 1000 ° C. to form a boron-doped film 1
From 1, boron is diffused into the polysilicon layer 10 to form a boron-doped polysilicon layer 13. Then, the N-type region 6 is removed from the polysilicon layer 13 doped with boron.
The P-type emitter region 14 is formed by diffusing boron therein. Thereafter, the boron-doped film 11 is removed with hydrofluoric acid or the like, and the first insulating film 4 in the base contact 9 is removed.
A base electrode 15 and an emitter electrode 16 are formed on the base contact 9 and the polysilicon layer 13, respectively. Further, a collector electrode 17 is formed on the back side of the P-type substrate 1 to complete a PNP transistor [FIG. 2 (b)]. Here, each of the electrodes 15 to 17 is made of Al or its alloy, or T
It is configured using a metal such as i / Pt / Au.

Embodiment 2 Next, an embodiment in which a complementary circuit is realized on a semiconductor integrated circuit will be described. FIG.
(a) to (c) and FIGS. 4 (a) to (c) are cross-sectional views sequentially showing the manufacturing process of the semiconductor integrated circuit.

First, an N-type buried layer 22 and an N-type epitaxial layer 23 are formed on a P-type substrate 21 according to a normal process.
Are sequentially formed [FIG. 3 (a)]. Next, a trench 24 for element isolation is formed, and a first insulating film 25 is formed on the entire surface including the inside of the trench 24. The region on the left side of the figure sandwiched between the trenches 24 is a region to be an NPN transistor,
The region on the right side of the drawing is a region to be a PNP transistor. A photoresist 26 is applied on the first insulating film 25, the photoresist 36 is selectively opened, and, for example, boron (B ⁺ ) ions are implanted to form a P-type region 27 in a region to be a PNP transistor. Form [Fig.
(b)]. At this time, if the ion implantation conditions are determined in consideration of the impurity concentration and the thickness of the N-type epitaxial layer 23,
After compensating the mold, the profile of the P-type impurity is obtained such that the concentration gradually increases from the surface to the back. This P-type region 27 becomes a buried region and an epitaxial region, that is, a collector region of the PNP transistor.

Next, an N-type pull-up portion 28 serving as a collector pull-up portion of the NPN transistor and a pull-up portion of the N-type buried layer 22 below the PNP transistor is formed. And
A photoresist 29 is applied and selectively opened, and a P ⁺ base region 30 of the NPN transistor and a collector pull-up 3 of the PNP transistor are formed by ion implantation of B ^+.
A part is formed [FIG. 3 (c)]. The photoresist 29 is removed, a photoresist 32 is applied again, and a selective opening is performed. For example, As ⁺ ions are implanted to form an N-type base region 33 of the PNP transistor [FIG.
(a)]. At this time, the ion species may be P ⁺ (phosphorus ion), but from the viewpoint of the diffusion coefficient and the like, it is desirable to use As ⁺ for forming a shallower base. The conditions for forming the base at this time may be determined in consideration of the annealing conditions, desired characteristics, and the like thereafter.

Thereafter, the base contact 34, the emitter contact 35 and the collector contact 36 of the NPN transistor and the base contact 37 and the emitter contact 38 of the PNP transistor are formed on the first insulating film 25.
Then, an N-type pulling contact 40 for the N-type buried layer 22 and the collector contact 39 are formed. At this time, N
The base contact 34 and the emitter contact 35 of the PN transistor are provided for the P-type base region 30, and the base contact 37 and the emitter contact 38 of the PNP transistor are provided for the N-type base region 33. Then, a polysilicon layer 41 not doped with an impurity is grown on the entire surface.
1 is provided with a boron-doped film 42. As the boron doped film 42, the same one as described in the first embodiment can be used. A photoresist 43 is applied, and the photoresist 39 is selectively left only on the base contact 34 of the NPN transistor, on the emitter contact 38 of the PNP transistor, and only on the collector contact 39 of the PNP transistor. The resist 39 is removed. And the remaining photoresist 4
Using the mask 3 as a mask, the boron doped film 42 is etched, and further, for example, As ⁺ ion implantation is performed on the entire surface [FIG. 4 (b)]. At this time, the thickness of the polysilicon layer 41, the thickness of the boron-doped film 42, the conditions for As ⁺ ion implantation, and the like are determined in the same manner as in the first embodiment.

The photoresist 43 is removed, a photoresist (not shown) is applied again, and the emitter contact 3 of the NPN transistor is formed by a photolithography process.
5, a collector contact 36, a base contact 37 of a PNP transistor, and an N-type pull-up contact 4.
This photoresist is selectively left over 0. Then, the remaining photoresist and boron doped film 42
Is used as a mask, the polysilicon layer 41 is etched. Thus, the polysilicon remains only on each of contacts 34 to 40. Then, high-temperature annealing is performed.

By this annealing, the boron doped film 42
The NPN transistor base contact 35 and the PNP transistor emitter contact 3
8 and polysilicon layer 41 on collector contact 39
Is diffused into the polysilicon layer 44 doped with boron. Further, the diffusion of boron from the polysilicon layer 44 forms a P-type emitter region 47 of the PNP transistor in the N-type base region. Also,
By implanting As ⁺ ions, the emitter contact 35 and the collector contact 36 of the NPN transistor are
The polysilicon layer 41 on the base contact 37 of the PNP transistor and on the N-type pull-up contact 40 has been converted to a polysilicon layer 45 doped with As. For this reason, as a result of annealing, As becomes the P of the NPN transistor.
The N-type emitter region 46 of the NPN transistor.
(c)]. Thereafter, by removing the boron-doped film 42 and attaching and processing a normal metal electrode, a desired semiconductor integrated circuit can be formed.

As described above, the NP is formed on the same semiconductor substrate.
A complementary element having an N transistor and a PNP transistor can be realized. In this case, N
Type and P-type polysilicon resistors can be formed simultaneously. In the case of the present embodiment, since both the P-type emitter region of the PNP transistor and the N-type emitter region of the NPN transistor are formed by diffusion of impurities from the polysilicon layer, characteristics suitable for being called a true complementary circuit. Can be obtained.

Embodiment 3 The present invention can be applied not only to a vertical PNP transistor but also to a horizontal PNP transistor. FIG. 5 shows a vertical NP on the same semiconductor substrate by using the same process as the above-described embodiments.
An example in which an N transistor and a lateral PNP transistor are configured is shown.

An As-doped polysilicon layer 45 is provided on the emitter E ₁ and collector C _{1 of} the NPN transistor and the base B _{2 of} the lateral PNP (L-PNP) transistor, and the base B _{1 of the} NPN transistor and the vertical PN
A polysilicon layer 44 doped with boron is formed on the emitter E ₂ and the collector C _{2 of the} P transistor.
The method of forming these polysilicon layers 44 and 45 is the same as in each of the above-described embodiments. Removing the boron doped film 42,
A desired semiconductor integrated circuit can be realized by attaching and processing a normal metal electrode.

Embodiment 4 The present invention is not limited to bipolar transistors, but can be applied to MOS transistors. FIG. 6 shows an example in which the present invention is applied to a CMOS integrated circuit.

This CMOS integrated circuit uses a P-type substrate 50.
A region where an ET (Nch-MOS) is formed, and a region on the right side of the drawing where a P-channel MOSFET (Pch-MOS) is formed are separated by a separation oxide film 57. An N-type well region 56 is formed in a region where the P-channel MOSFET is formed. An As-doped polysilicon layer 52 is disposed on each of the source S ₁ and drain D ₁ contacts 51 of the N-channel MOSFET, and boron is deposited on each of the source S ₂ and drain D ₂ contacts 53 of the P-channel MOSFET. A doped polysilicon layer 55 is provided. Further, a boron-doped film 54 is provided on the polysilicon layer 55, and the polysilicon layer 55 is doped with boron by diffusion of boron from the boron-doped film 54. The gates G ₁ and G ₂ of each MOSFET are on the gate oxide film 58. According to the present embodiment, since a very shallow source-drain junction can be formed, the short channel effect when the gate length is reduced can be suppressed, which greatly contributes to speeding up the device. As a matter of course, a Bi-CMOS IC can be formed by combining with the bipolar transistors of the above-described embodiments.

[0036]

As described above, according to the present invention, since a boron-doped polysilicon layer can be easily formed on a contact in a patterned state, an extremely shallow junction can be easily formed in a single PNP transistor. since it stably formed, it can be achieved performance (e.g. increase of f _T), since the very close high performance PNP transistor NPN transistor and the high frequency characteristic can be realized on the same substrate, a truly complementary circuit In addition, it can be easily applied to lateral PNP transistors and can form polysilicon resistors. It can also be applied to source and drain contacts of C-MOS integrated circuits and can form shallow junctions. Therefore, the short channel effect due to the miniaturization of the gate is suppressed and the speed is increased, and the Bi-CMOS That it can be applied to the AND circuit, it is possible to obtain a large effect.

[Brief description of the drawings]

FIGS. 1A and 1B are cross-sectional views illustrating a manufacturing process of a PNP transistor of Example 1. FIG.

FIGS. 2A and 2B are cross-sectional views illustrating the steps of manufacturing the PNP transistor according to the first embodiment.

FIGS. 3A to 3C are cross-sectional views illustrating manufacturing steps of the semiconductor integrated circuit according to the second embodiment.

FIGS. 4A to 4C are cross-sectional views illustrating manufacturing steps of the semiconductor integrated circuit according to the second embodiment.

FIG. 5 is a sectional view showing a semiconductor integrated circuit according to a third embodiment.

FIG. 6 is a cross-sectional view illustrating a semiconductor integrated circuit according to a fourth embodiment.

FIGS. 7A and 7B are cross-sectional views illustrating a conventional PNP transistor and an NPN transistor, respectively.

[Explanation of symbols]

1,21,50 P-type substrate 2 P-type epitaxial layer 3,57 Isolation oxide film 4,25 First insulating film 5,12,26,29,32,43 Photoresist 6 N-type region 7 Second insulating film 8, 35, 38 Emitter contact 9, 34, 37 Base contact 10, 13, 41, 44, 45, 52, 55 Polysilicon layer 11, 42, 54 Boron-doped film 14, 47 P-type emitter region 15 Base electrode 16 Emitter electrode 17 Collector electrode 22 N-type buried layer 23 N-type epitaxial layer 24 Trench 27 P-type region 28 N-type pull-up portion 30 P-type base region 31 Collector pull-up portion 33 N-type base region 36,39 Collector contact 40 N-type pull-up contact 46 N-type emitter region 51, 53 Contact 56 N-type well region

Claims (3)

(57) [Claims] 1. A semiconductor device having a PNP transistor.
In the method for manufacturing the semiconductor substrate, an N-type region serving as a base of the semiconductor substrate is provided.
Undoped polysilicon layer
Forming a P-type impurity covering the polysilicon layer.
Forming a film containing a material;
The film containing the P-type impurity is selectively removed to remove the PN.
Step of processing into the shape of emitter electrode of P transistor
And heat treatment to remove P in the film containing the P-type impurity.
Impurity of the N type through the polysilicon layer.
P-type emitter of the PNP transistor
Forming a region.
Device manufacturing method. 2. An N-type region is selectively formed on a P-type substrate.
And do not dope impurities on the N-type region.
Growing a new polysilicon layer;
Growing a film containing the P-type impurity over the layer
And selectively removing the polysilicon layer and the P-type impurity.
After performing etching with the film containing, heat treatment is performed,
The P-type impurity in the film containing the P-type impurity is
Diffusion into the N-type region through a silicon layer to form a P-type
Forming a region.
Device manufacturing method. 3. An N-type first region is formed on a P-type substrate.
Thereafter, a P-type region is selectively formed and selectively formed.
A second N-type region is further added to the formed P-type region.
In a method of manufacturing a semiconductor integrated circuit to be selectively formed,
After the formation of the N-type second region, impurities are doped.
Growing a polysilicon layer over the entire surface and a P-type
Selectively depositing a film containing impurities on the polysilicon layer
Forming and adding N-type impurities to the polysilicon layer.
Step of ion implantation and a film containing the P-type impurity
And leave a portion of the polysilicon layer immediately below
Step of selectively removing implanted polysilicon layer
Heat treatment is performed, and the film containing the P-type impurity is
By diffusion from the polysilicon layer immediately below, the P
The P-type impurity diffusion region is selectively formed in the P-type region.
Manufacturing a semiconductor device, comprising the steps of:
Construction method.