JPH0897226A - Pnp transistor, semiconductor integrated circuit, manufacture of semiconductor device, and manufacture of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE: To realize a real complementary circuit between an NPN transistor and a PNP transistor, by achieving high speed operation of the PNP transistor. CONSTITUTION: A poly silicon layer 13 doped with boron is formed on the emitter contact of a PNP transistor. The poly silicon layer 13 is formed by a method wherein a poly silicon layer 10 which is not doped with impurities and a boron-doped film 11 which is a diffusion source of boron are laminated on the whole surface, the poly silicon layer 10 and the boron-doped film 11 are selectively left only on the emitter contact 8 by using a photoresist 12, and heat treatment is performed. After boron diffusion from the boron-doped film 11 to the poly silicon layer 10, boron is continuously diffused from the poly silicon layer 10 to an N-type region 6, and a P-type emitter region 14 is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a high speed and high frequency bipolar transistor.

[0002]

2. Description of the Related Art In recent years, the speed and performance of bipolar transistors, especially NPN type transistors, have been significantly improved. Also, in measuring instruments and memory testers,
Higher speed is required in response to higher performance of semiconductor devices. With the increase in speed and performance of NPN transistors, there has been a strong demand for speed and performance of PNP transistors used in complementary (complementary) circuits with NPN transistors.

However, at present, the speedup of PNP transistors is not as advanced as that of NPN transistors. As is well known, the transition frequency (Tr
ansition frequency) f _T. The parameters governing f _T are (i) the speed of a minority carrier traveling in the base, and (ii) the base width or depth of the emitter and base junctions. As a factor that impedes the high speed operation of the PNP transistor, firstly, since the minority carrier in the base of the PNP transistor is a hole (hole), it is smaller than the NPN transistor using electrons (electrons) as the minority carrier. The carrier movement speed is physically low, and secondly, the controllability of the base width has not been taken into consideration as much as in the case of the NPN transistor.
The fact that a narrow base width and a shallow junction could not be realized is mentioned, and these factors are the main reason why the speedup of the PNP transistor is not advanced. The second of the factors cited here is a problem related to the structure and manufacturing method of the device, and the present invention handles exactly this problem.

7 (a) and 7 (b) are schematic cross-sectional views showing structural examples of a conventional vertical PNP transistor and vertical NPN transistor, respectively. Hereinafter, in this specification, unless otherwise specified, the transistors are vertical transistors.

In the PNP transistor of FIG. 7A, a P-type epitaxial layer 62 is grown on a P-type substrate 61 to selectively form an N-type base region 64, and then a P-type epitaxial layer 62 is formed in the N-type base region 64. It is manufactured by forming the mold emitter region 65. An insulating film 63 is provided on the surface other than the portion to be the contact hole.

On the other hand, the outline of the manufacturing method of the NPN transistor of FIG. 7B is as follows. That is, first N
Growing an N-type epitaxial layer 67 on the mold substrate 66,
A P-type base region 68 is selectively formed, and then a contact 71 is opened in the insulating film 63. Then, for example, after growing a polysilicon layer 70 doped with arsenic (As), this polysilicon layer 70 is selectively etched leaving a portion to become an emitter, and annealed at a high temperature to form a P-type base region. An N-type emitter region 69 is formed in 68.

N produced by this series of processes
In the PN transistor, the above-mentioned polysilicon layer 7
The presence of 0 is very important for improving the characteristics.
The reason will be described below. First of all, due to the presence of the polysilicon layer (or it is also said to be due to the influence of the oxide film existing at the interface with the silicon substrate), the injection efficiency from the emitter to the base is increased, so that the direct current amplification factor h _FE is increased. Is easy to improve. Therefore, when trying to obtain the same h _FE (for example, 80), the annealing time is shorter than that in the case where the polysilicon layer is not provided.
This is because a shallower junction, that is, a narrower base width can be realized. Second, since the emitter opening in the oxide film is covered with the polysilicon layer, the emitter junction (made of Al and its alloy, or Au) to be formed on this opening is separated from the emitter junction. This is because the junction breakdown of the emitter can be prevented. If there is no polysilicon layer in the emitter opening, the shallower the junction, the easier the junction breakdown of the emitter occurs. That is, by providing a polysilicon layer doped with an N-type impurity such as As in the emitter opening, an extremely shallow emitter junction can be easily and stably formed, and both improvement in characteristics and improvement in reliability can be achieved.

On the other hand, as shown in FIG.
In the NP transistor, there is no polysilicon layer containing P-type impurities on the P-type emitter region 65. The reason is that boron (B) is used as a dopant for the P-type emitter region of the PNP transistor from the viewpoint of solid solubility and the like. However, as compared with polysilicon not doped with impurities, polysilicon doped with boron is used. It can be mentioned that the layer has a characteristic that the etching rate becomes extremely slow. The formation of the polysilicon layer on the emitter opening in the NPN transistor involves the formation of DOPOS (Dope) doped in situ.
d Polysilicon) and ion-implanted polysilicon are adopted, but even if these methods are applied to a PNP transistor, the processing of the polysilicon layer is practically impossible. Therefore, in the end, the PNP transistor contains a P-type impurity. It is not possible to provide a polysilicon layer in the emitter opening. Therefore, for the reason completely opposite to the case where the As-doped polysilicon layer is provided in the above-described NPN transistor, the PNP transistor cannot form a shallow junction, and thus the speedup cannot be achieved.

When a complementary circuit is to be formed on an integrated circuit, even if an NPN transistor of 10 to 20 GHz can be realized as f _T ,
On the side of the PNP transistor, only f _{T of} about 1 to 4 GHz can be realized, and only a far complementary circuit to a true complementary circuit can be obtained. In addition, the vertical PNP described above
In addition to the transistor, there is a lateral PNP transistor (lateral PNP transistor). In this lateral PNP transistor, the carriers move laterally with respect to the substrate surface, so that the base width is limited by lithography and the like. Characteristics, which are far inferior to vertical PNP transistors (f _T is about 5 MHz).
Can only be realized. Techniques for improving the problems of such conventional complementary circuits are disclosed in, for example, JP-A-59-113658, JP-A-60-65566, and JP-A-63-18671.

[0010]

However, with the techniques disclosed in these publications, it is impossible to improve the characteristics of the PNP transistor to a level comparable to that of the NPN transistor and realize a true complementary circuit. First, the technique disclosed in JP-A-59-113658 is to form a lateral NPN transistor and a vertical PNP transistor in P-type epitaxial layer on an n-type substrate, both of the transistors of f _T Although the difference is small, the overall speedup cannot be realized. JP-A-6
In 0-65566 discloses faster technique of the lateral PNP transistor is disclosed, it can actually be realized f _T
The frequency is at most about a dozen MHz. In addition, JP-A-63-
In the technology disclosed in 18671, the P-type layer which becomes the emitter region of the PNP transistor is N
It is characterized in that it is formed shallower than the P-type layer serving as the base region of the PN transistor. However, as is clear from the above description, there is a reliability problem of junction breakdown of the emitter and h.
There is a limit in that _FE cannot be improved,
It is difficult to achieve sufficient speedup.

An object of the present invention is to realize a truly high-speed and highly reliable PNP transistor and a complementary circuit or integrated circuit using this PNP transistor.

[0012]

A PNP transistor according to the present invention is a PNP transistor having an emitter contact, in which a polysilicon layer containing a P-type impurity is selectively formed on the emitter contact.

The semiconductor integrated circuit of the present invention is a semiconductor integrated circuit having a PNP transistor and an NPN transistor on a substrate of one conductivity type, wherein the PNP transistor has an emitter and a collector of the same conductivity type,
A polysilicon layer containing impurities of the same conductivity type is selectively formed on the emitter contact of the P-transistor,
The NPN transistor has an emitter of opposite conductivity type, and a polysilicon layer of opposite conductivity type is formed on an emitter contact of the NPN transistor.

The CMOS integrated circuit of the present invention has a P-channel type MOSFET and an N-channel type MOSFE on the same substrate.
In the CMOS integrated circuit having T and T, a polysilicon layer containing a P-type impurity is selectively formed on the source region and the drain region of the P-channel MOSFET, and the source region and the drain region of the N-channel MOSFET are formed. A polysilicon layer containing an N-type impurity is selectively formed on the above.

The Bi-CMOS integrated circuit of the present invention is the semiconductor integrated circuit of the present invention, wherein a P-channel type MOSFET and an N-channel type MOSFE are provided in the substrate.
T is further formed, a polysilicon layer containing a P-type impurity is selectively formed on the source region and the drain region of the P-channel MOSFET, and T is formed on the source region and the drain region of the N-channel MOSFET. N
A polysilicon layer containing a type impurity is selectively formed.

According to the method of manufacturing a semiconductor device of the present invention, a region of the second conductivity type is selectively formed on a substrate of the first conductivity type, and then a polysilicon layer not doped with impurities and A film containing impurities of the first conductivity type is grown, the polysilicon layer and the film are selectively etched, and heat treatment is performed to form a first conductivity type in the region of the second conductivity type. To form a region.

According to the method of manufacturing a semiconductor integrated circuit of the present invention, a first conductive type region is formed on a first conductive type substrate, and then the first conductive type region is selectively formed. A method of manufacturing a semiconductor integrated circuit, wherein a second region of a second conductivity type is selectively formed in a region of the first conductivity type formed and selectively formed. After forming the first region of the above, a step of growing a polysilicon layer not doped with impurities over the entire surface and a step of selectively forming a film containing impurities of the first conductivity type on the polysilicon layer And a step of ion-implanting impurities of the second conductivity type into the polysilicon layer, and a step of selectively leaving the ion-implanted polysilicon layer while leaving the polysilicon layer immediately below the film. Then, heat treatment is performed to spread from the polysilicon layer. And a step of selectively forming a region and a second region of the second conductivity type of said first conductivity type by.

[0018]

According to the present invention, a polysilicon layer not doped with impurities and a film containing boron are laminated, patterning is performed in this state, and then heat treatment is performed to diffuse boron into the polysilicon layer after patterning. At the same time, boron is diffused into the N-type region of the semiconductor to form a P-type region. The film containing boron on the polysilicon layer is used as a diffusion source of boron. Accordingly, in the case of a PNP bipolar transistor, since the emitter region is covered with the polysilicon layer doped with boron, h _FE
Is improved, a shallow junction is possible, a high speed is achieved, and the reliability of the emitter junction is improved. In the present invention, by patterning the polysilicon layer at the stage where boron is not doped, and then diffusing boron,
Boron-doped polysilicon solves the problem that it is difficult to process.

[0019]

Embodiments of the present invention will now be described with reference to the drawings.

Example 1 This example is an example of a single PNP transistor based on the present invention. This PNP
Transistor manufacturing process is shown in Fig. 1 (a), (b) and Fig. 2
They are shown in order in (a) and (b).

First, a P-type substrate 1 having a high impurity concentration is used, a P-type epitaxial layer 2 is grown on one surface of the P-type substrate 1, and an isolation oxide film 3 is selectively formed.
As a result, the P-type epitaxial layer 2 has a trapezoidal sectional shape, and the top surface thereof is provided with the first insulating film 4 continuous with the isolation oxide film 3. After that, a photoresist 5 is applied, the photoresist 5 is selectively opened at a portion corresponding to the top surface portion of the P-type epitaxial layer 2, and the opening of the photoresist 5 and the first insulating layer exposed at the bottom thereof are exposed. N-type impurities (N-type dopant ions) are ion-implanted into the P-type epitaxial layer 2 through the film 4 to form an N-type region 6 serving as a base of the PNP transistor [FIG. 1 (a)]. Arsenic (As) is used as the ions to be implanted, and the implantation conditions are, for example, an acceleration voltage of 50 KeV and an implantation amount of 6 × 10 ¹³ cm ⁻² .

Subsequently, a second insulating film 7 is formed on the entire surface,
After that, the emitter contact 8 and the base contact 9 are opened in the second insulating film 7 and the first insulating film 4. At this time, the N-type region 6 is exposed at the bottom of the emitter contact 8, but the first insulating film 4 is left at the bottom of the base contact 9. Here, the second insulating film 7
Is intended for the surface passivation effect of a nitride film or the like, and by providing it, it is possible to improve the moisture resistance and the like. In particular, even if the second insulating film 7 is not provided, It does not hinder the effect. Then, the polysilicon layer 10 to which no impurities are added is grown on the entire surface, and further a boron-doped film 11 is formed [FIG. 1 (b)]. Here, the boron-doped film 11 is a film containing boron as a diffusion source, for example, BS.
G (Borosilicate Glass) and PBF (Poly-Boron-Film)
Can be used. Boron concentration in the film is 3-4x
It should be 10 ¹⁹ atoms cm ⁻³ or more. Polysilicon layer 10
Is about 100 to 400 nm, and the thickness of the boron-doped film 11 is about 50 to 300 nm. However, the present invention is not limited to this, and the arsenic implantation conditions in the N-type region 6 to be the base and the subsequent It can be determined in consideration of annealing conditions and desired characteristics (breakdown voltage, h _FE , high frequency characteristics). Further, the polysilicon layer 10 may be formed by a usual method or may be formed by annealing an amorphous silicon layer to polycrystallize it.

Next, a photoresist 12 is applied on the entire surface, and the photoresist 12 other than the portion on the emitter contact 8 is selectively removed by a photolithography process. Then, using the remaining photoresist 12 as a mask, the boron-doped film 11 and the polysilicon layer 1
0 is etched [FIG. 2 (a)]. At this time, since the first insulating film 4 remains on the bottom of the base contact 9, the N-type region 6 is not etched through the base contact 9.

After removing the photoresist 12, 950
Boron-doped film 1 by annealing at ~ 1000 ° C
Boron is diffused into the polysilicon layer 10 from 1 to form a boron-doped polysilicon layer 13. Then, from the boron-doped polysilicon layer 13 to the N-type region 6
Boron is diffused therein to form the P-type emitter region 14. Then, the boron-doped film 11 is removed with hydrofluoric acid or the like, the first insulating film 4 in the base contact 9 is removed,
A base electrode 15 and an emitter electrode 16 are formed on the base contact 9 and the polysilicon layer 13, respectively. Further, the collector electrode 17 is formed on the back surface side of the P-type substrate 1 to complete the PNP transistor [FIG. 2 (b)]. Here, each of the electrodes 15 to 17 is made of Al, an alloy thereof, or T.
It is configured by using a metal such as i / Pt / Au.

<Embodiment 2> Next, an embodiment in which a complementary circuit is realized on a semiconductor integrated circuit will be described. Figure 3
4A to 4C are cross-sectional views sequentially showing manufacturing steps of this semiconductor integrated circuit.

First, according to a normal process, an N type buried layer 22 and an N type epitaxial layer 23 are formed on a P type substrate 21.
Are sequentially formed [FIG. 3 (a)]. Next, a trench 24 for element isolation is formed, and a first insulating film 25 is formed on the entire surface including the inside of the trench 24. The region on the left side of the drawing sandwiched by the trenches 24 is a region to be an NPN transistor,
The region on the right side of the drawing is a region that should be a PNP transistor. A photoresist 26 is applied on the first insulating film 25, the photoresist 36 is selectively opened, and, for example, boron (B ⁺ ) ions are implanted to form a P-type region 27 in a region to be a PNP transistor. Form [Fig. 3
(b)]. At this time, if the ion implantation conditions are determined in consideration of the impurity concentration and the thickness of the N-type epitaxial layer 23, N
After compensating for the mold, a profile of the P-type impurity is obtained such that the concentration gradually increases from the surface toward the back. This P-type region 27 becomes a buried region and an epitaxial region, that is, a collector region of the PNP transistor.

Next, an N-type pull-up portion 28 is formed which serves as a collector pull-up portion of the NPN transistor and a pull-up portion of the N-type buried layer 22 below the PNP transistor. And
A photoresist 29 is coated and selectively opened, and the P + type base region 30 of the NPN transistor and the collector pull-up of the PNP transistor 3 by the B ⁺ ion implantation method.
Form a part [FIG. 3 (c)]. The photoresist 29 is removed, a photoresist 32 is applied again and selectively opened, and, for example, As ⁺ ions are implanted to form an N-type base region 33 of the PNP transistor [FIG.
(a)]. The ion species at this time may be P ⁺ (phosphorus ion), but it is desirable to use As ⁺ for forming a shallower base from the viewpoint of the diffusion coefficient and the like. The base forming conditions at this time may also be determined in consideration of the subsequent annealing conditions and desired characteristics.

Then, on the first insulating film 25, the base contact 34, the emitter contact 35 and the collector contact 36 of the NPN transistor, the base contact 37 and the emitter contact 38 of the PNP transistor are formed.
Also, a collector contact 39 and an N-type pulling contact 40 for the N-type buried layer 22 are formed. At this time, N
The PN transistor base contact 34 and the emitter contact 35 are provided for the P-type base region 30, and the PNP transistor base contact 37 and the emitter contact 38 are provided for the N-type base region 33. Then, a polysilicon layer 41 not doped with impurities is grown on the entire surface, and the polysilicon layer 4 is further grown.
A boron-doped film 42 is provided on the first layer 1. As the boron-doped film 42, the same film as that described in the first embodiment can be used. Photoresist 43 is applied so that the photoresist 39 selectively remains only on the base contact 34 of the NPN transistor, the emitter contact 38 of the PNP transistor, and the collector contact 39 of the PNP transistor. The resist 39 is removed. And the remaining photoresist 4
Using the mask 3 as a mask, the boron-doped film 42 is etched, and, for example, As ⁺ ion implantation is performed on the entire surface [FIG. 4 (b)]. At this time, the thickness of the polysilicon layer 41, the thickness of the boron-doped film 42, the conditions of As ⁺ ion implantation, etc. are determined in the same manner as in the case of the above-described first embodiment.

The photoresist 43 is removed, a photoresist (not shown) is applied again, and the emitter contact 3 of the NPN transistor is formed by a photolithography process.
5 and collector contact 36, PNP transistor base contact 37, and N-type pulling contact 4
This photoresist is selectively left above the 0. Then, the remaining photoresist and boron-doped film 42
Using the as a mask, the polysilicon layer 41 is etched. As a result, the polysilicon remains only on the contacts 34-40. Then, high temperature annealing is performed.

By this annealing, the boron-doped film 42 is formed.
The presence of the NPN transistor base contact 35 and the PNP transistor emitter contact 3
8 and the polysilicon layer 41 on the collector contact 39
Boron is diffused into the polysilicon to form a polysilicon layer 44 doped with boron. Further, diffusion of boron from the polysilicon layer 44 forms a P-type emitter region 47 of the PNP transistor in the N-type base region. Also,
By implanting As ⁺ ions, on the emitter contact 35 and collector contact 36 of the NPN transistor,
The polysilicon layer 41 on the base contact 37 of the PNP transistor and on the N-type pulling contact 40 is converted into a polysilicon layer 45 doped with As. Therefore, as a result of annealing, As is P of the NPN transistor.
Diffuses into the mold base region 30, thereby forming the N-type emitter region 46 of the NPN transistor [FIG.
(c)]. After that, the boron-doped film 42 is removed and a normal metal electrode is deposited and processed, whereby a desired semiconductor integrated circuit can be formed.

In this way, NPs are formed on the same semiconductor substrate.
It is possible to realize a complementary element having an N transistor and a PNP transistor. In this case, N on the insulating film
And P-type polysilicon resistors can be formed at the same time. In the case of the present embodiment, both the P-type emitter region of the PNP transistor and the N-type emitter region of the NPN transistor are formed by the diffusion of impurities from the polysilicon layer, so that they are suitable as a true complementary circuit. Can be obtained.

<Third Embodiment> The present invention can be applied not only to vertical PNP transistors but also to horizontal PNP transistors. FIG. 5 shows a vertical NP formed on the same semiconductor substrate by using the same process as each of the above-described embodiments.
An example in which an N transistor and a lateral PNP transistor are configured is shown.

An As-doped polysilicon layer 45 is provided on the emitter E ₁ and collector C _{1 of} the NPN transistor and the base B _{2 of} the lateral PNP (L-PNP) transistor. The base B _{1 of the} NPN transistor and the vertical PN are provided.
A boron-doped polysilicon layer 44 is formed on the emitter E ₂ and collector C _{2 of the} P-transistor.
The method of forming these polysilicon layers 44 and 45 is the same as that of the above-mentioned respective embodiments. The boron-doped film 42 is removed,
A desired semiconductor integrated circuit can be realized by depositing and processing a normal metal electrode.

<Embodiment 4> The present invention is not limited to a bipolar transistor, but can be applied to a MOS transistor. FIG. 6 shows an example in which the present invention is applied to a CMOS integrated circuit.

This CMOS integrated circuit uses a P-type substrate 50, and the left side of the figure is an N-channel MOSF.
The region where ET (Nch-MOS) is formed, the right side in the figure is the region where P-channel MOSFET (Pch-MOS) is formed, and these are separated by an isolation oxide film 57. An N-type well region 56 is formed in the region where the P-channel MOSFET is formed. An As-doped polysilicon layer 52 is arranged on each contact 51 of the source S ₁ and drain D ₁ of the N-channel MOSFET, and boron is formed on each contact 53 of the source S ₂ and drain D ₂ of the P-channel MOSFET. A doped polysilicon layer 55 is arranged. Further, a boron-doped film 54 is provided on the polysilicon layer 55, and the polysilicon layer 55 is doped with boron by the diffusion of boron from the boron-doped film 54. The gates G ₁ and G ₂ of each MOSFET are on the gate oxide film 58. According to the present embodiment, since a very shallow source-drain junction can be formed, it is possible to suppress the short channel effect when the gate length is miniaturized, which greatly contributes to the speedup of the device. As a matter of course, it is possible to form a Bi-CMOS IC by combining with the bipolar transistor of each of the above embodiments.

[0036]

As described above, according to the present invention, a polysilicon layer doped with boron can be easily formed on a contact in a patterned state, so that an extremely shallow junction can be easily formed in a single PNP transistor. Since it can be stably formed, high performance (for example, improvement of f _T ) can be realized, and a high-performance PNP transistor whose high-frequency characteristics are very close to those of the NPN transistor can be realized on the same substrate, thus realizing a true complementary circuit. In addition, it can be easily applied to a lateral PNP transistor and can form a polysilicon resistance. Furthermore, it can be applied to a source contact and a drain contact of a C-MOS integrated circuit, and a shallow junction can be formed. Therefore, the short channel effect due to the miniaturization of the gate is suppressed, which contributes to the speedup. That it can be applied to the AND circuit, it is possible to obtain a large effect.

[Brief description of drawings]

1A and 1B are cross-sectional views showing a manufacturing process of a PNP transistor according to a first embodiment.

2A and 2B are cross-sectional views showing a manufacturing process of the PNP transistor of the first embodiment.

3A to 3C are cross-sectional views showing the manufacturing process of the semiconductor integrated circuit of the second embodiment.

4A to 4C are cross-sectional views showing the manufacturing process of the semiconductor integrated circuit of the second embodiment.

FIG. 5 is a sectional view showing a semiconductor integrated circuit of Example 3;

FIG. 6 is a sectional view showing a semiconductor integrated circuit of Example 4;

7A and 7B are cross-sectional views illustrating a conventional PNP transistor and NPN transistor, respectively.

[Explanation of symbols]

1,21,50 P-type substrate 2 P-type epitaxial layer 3,57 Isolation oxide film 4,25 First insulating film 5,12,26,29,32,43 Photoresist 6 N-type region 7 Second insulating film 8,35,38 Emitter contact 9,34,37 Base contact 10,13,41,44,45,52,55 Polysilicon layer 11,42,54 Boron-doped film 14,47 P-type emitter region 15 Base electrode 16 Emitter electrode Reference Signs List 17 collector electrode 22 N-type buried layer 23 N-type epitaxial layer 24 trench 27 P-type region 28 N-type pulling portion 30 P-type base region 31 collector pulling portion 33 N-type base region 36,39 collector contact 40 N-type pulling contact 46 N-type emitter region 51,53 Contact 56 N-type well region

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 21/8249 27/06

Claims (11)

[Claims] 1. A PNP having an emitter contact formed therein.
In the transistor, on the emitter contact,
A PNP transistor characterized in that a polysilicon layer containing a P-type impurity is selectively formed. 2. The PNP transistor according to claim 1, wherein an emitter region of the PNP transistor is formed by diffusing the P-type impurity from the polysilicon layer. 3. A semiconductor integrated circuit having a PNP transistor and an NPN transistor on a substrate of one conductivity type, wherein the PNP transistor has an emitter and a collector of the same conductivity type, and the same conductivity is provided on an emitter contact of the PNP transistor. -Type impurity-containing polysilicon layer is selectively formed, the NPN transistor has an opposite conductivity type emitter, and the opposite conductivity type polysilicon layer is formed on the emitter contact of the NPN transistor. And a semiconductor integrated circuit. 4. A polysilicon layer containing impurities of the same conductivity type is selectively formed also on the collector contact of the PNP transistor, and a polysilicon layer of the opposite conductivity type is also formed on the collector contact of the NPN transistor. The semiconductor integrated circuit according to claim 3, which is formed. 5. The semiconductor integrated circuit according to claim 3, wherein the PNP transistor is a vertical bipolar transistor. 6. The semiconductor integrated circuit according to claim 3, wherein the PNP transistor is a lateral bipolar transistor. 7. A P-channel MOSFET on the same substrate
And a N-channel MOSFET, wherein a polysilicon layer containing a P-type impurity is selectively formed on the source region and the drain region of the P-channel MOSFET, and the source of the N-channel MOSFET is formed. A CMOS integrated circuit, wherein a polysilicon layer containing an N-type impurity is selectively formed on the region and the drain region. 8. The method according to claim 3, further comprising a P-type polysilicon resistor and an N-type polysilicon resistor formed on the insulating film at the same time when the polysilicon layer of the PNP transistor and the polysilicon layer of the NPN transistor are formed. 4. The semiconductor integrated circuit according to 4. 9. The semiconductor integrated circuit according to claim 3, wherein a P-channel MOSFET is provided in the substrate.
And an N channel type MOSFET are further formed, and a polysilicon layer containing a P type impurity is selectively formed on the source region and the drain region of the P channel type MOSFET, and the source region and the drain of the N channel type MOSFET are formed. A Bi-CMOS integrated circuit in which a polysilicon layer containing N-type impurities is selectively formed on a region. 10. A second conductivity type region is selectively formed on a first conductivity type substrate, and then a polysilicon layer not doped with impurities and the first conductivity type impurity are formed. A semiconductor device in which a first conductive type region is formed in the second conductive type region by growing a film containing the same, selectively etching the polysilicon layer and the film, and performing heat treatment. Production method. 11. A first-conductivity-type substrate is formed by forming a second-conductivity-type first region on a first-conductivity-type substrate and then selectively forming the first-conductivity-type region. In a method of manufacturing a semiconductor integrated circuit, wherein a second region of a second conductivity type is further selectively formed in a region of the first conductivity type, wherein after forming the first region of the second conductivity type, A step of growing a polysilicon layer not doped with impurities over the entire surface, a step of selectively forming a film containing impurities of the first conductivity type on the polysilicon layer, and a step of impurities of the second conductivity type Is ion-implanted into the polysilicon layer, a step of selectively leaving the ion-implanted polysilicon layer while leaving the polysilicon layer directly below the film, and performing a heat treatment, The first conductivity type region is diffused by diffusion from the layer. And the second of said second conductivity type
The method for manufacturing a semiconductor integrated circuit, further comprising: