JPH02112270A - Bipolar cmos semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To assure a high gain band width and high withstand voltage by forming a longitudinal PNP transistor including a low resistance p type collector in an epitaxial layer such as a shallow grown at least two times. CONSTITUTION:After an oxide film 2 is formed on a p<-> type single crystal silicon substrate 1, it is subjected to selective etching, and then thermal diffusion by Sb is performed to form an n<+> buried layer 3 in longitudinal NPN and PNP transistor regions, a transversal PNP transistor region, and a P-MOS transistor region, respectively. Then, first epitaxial growth is performed to form a first epitaxial layer 4. Further, a high concentration p<+> buried layer 5 and a low concentration p<+> buried layer 6 for interelement isolation are formed by boron implantation. Successively, second epitaxial growth is performed to form a second epitaxial layer 7. Further, an n type collector electrode section 8, a p type well diffusion layer 9, and an n type well diffusion layer 10 are formed by ion implantation. Moreover, the collector buried layers 5, 6 and the well diffusion layers 9, 10 are extended into contact thereamong by heat treatment to provide a longitudinal PNP transistor in which sheet resistance of the collector buried layer is reduced.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention provides a bipolar CMOS semiconductor device in which a vertical NPN I-transistor, an S-type PNP transistor, a lateral PNP transistor, and a complementary MOS transistor are formed on the same substrate. and its manufacturing method.

[Conventional technology]

Conventionally, sensors and analog circuits were composed of individual parts5
Regarding semiconductor devices in which electronic circuits such as digital circuits and actuator drive circuits are configured on the same monolithic substrate, for example, Japanese Patent Laid-Open No. 52-2292 and Japanese Patent Laid-Open No. 54
A bipolar CMOS semiconductor device for digital circuits, in which a 0MOS transistor and a bipolar NPN transistor are integrally formed, has been proposed in Japanese Patent Application Laid-open No. 51-106278 and Japanese Patent Application Laid-open No. 51-106278. No., Japanese Patent Publication No. 6072255
No. 62-219555 discloses a bipolar CMO8 semiconductor device for analog circuits that includes a vertical PNP transistor that can be formed simultaneously without increasing the number of masks. Furthermore, Japanese Patent Laid-Open No. 62-247558 and other publications propose means for realizing as many elements as possible using bipolar CMOS elements. However, these conventionally proposed semiconductor devices are constructed using only two types of n-type and n-type buried layers and a diffusion layer from the epitaxial surface using epitaxial layers grown on the same substrate. Therefore, it is almost impossible to simultaneously satisfy the breakdown voltage, current amplification factor, and high frequency characteristics of all elements.

On the other hand, in the field of compound semiconductors such as semiconductor lasers, HEMTs, and MODFETs, multiple epitaxial technology to obtain a heterostructure is a well-known technology. As a means to lower the resistance, a method of performing epitaxial growth twice is disclosed, for example, in Japanese Patent Application Laid-Open No. 49-362.
No. 91 JP-A-49-52987, JP-A-57-157
567, etc., and the idea of using multiple epitaxial technology to integrate elements with different breakdown voltages is disclosed in, for example, JP-A-53-54983 and JP-A-51-474.
No. 93, Japanese Unexamined Patent Publication No. 57-197640, etc. However, these semiconductor devices using multiple epitaxial techniques are only devices that integrate individual or two devices in a limited range.

In semiconductor devices, digital circuits require low power consumption and high-speed CMOS circuits, and analog circuits require relatively high breakdown voltage of 10 V or more, wide gain bandwidth of IGHz or more, and complementary High-performance vertical NPN and vertical PNP transistor circuits with excellent characteristics are required, but bipolar/CMOS# conductor devices that achieve at least the high performance of these four basic devices are not yet known. Furthermore, at present, no bipolar CMOS manufacturing technology using multiple epitaxial technology is known.

[Problem to be solved by the invention]

As mentioned above, the conventional technology is a high-speed static R
A combination of a vertical NPN bipolar transistor with a high gain bandwidth developed for AM and a short channel 0MOS transistor, or a vertical NPN bipolar transistor with a relatively low gain bandwidth for operational amplifiers and analog circuits. This is an integrated version of PNP and NPN transistors and 0MOS transistors.

By the way, peripheral circuits for sensors that operate at high speeds, such as high-speed cameras, require performance that can process input signals of any level at high speed in order to fully utilize their high-speed performance. For this purpose, bipolar CMOS semiconductor devices including vertical PNP transistors and conventional high-speed vertical NPN transistors, which have a gain bandwidth exceeding 1 GHz, a relatively high breakdown voltage exceeding IOV, and a high knee current, are indispensable. ing.

However, conventional semiconductor devices including vertical PNP transistors have a problem in that they cannot have characteristics compatible with peripheral circuits of such high-speed sensors.

In order to form a bipolar CMOS semiconductor device including a vertical PNP transistor with a high gain bandwidth on the same substrate as described above, the following techniques are used: (1) High gain in a shallow epitaxial region concentration p
Technique for forming one buried layer (2) Forming a shallow P N double diffusion transistor,
Similarly, a technique is required to simultaneously form the NP double diffusion of a shallow NPN transistor and the source/drain junction of a CMOS transistor with high precision.

The present invention was made in order to solve the above-mentioned problems in conventional bipolar CMOS semiconductor devices. High-speed vertical type P with high stickiness and high knee current
An object of the present invention is to provide a bipolar CMOS semiconductor device including an NP transistor.

[Means and effects for solving the problem] In order to solve the above problems, the present invention provides a seta-epitaxially grown layer that is grown in at least two steps with a low doping level, and is different from the epitaxially grown layer. A semiconductor device comprising a plurality of circuit components on a single monolithic semiconductor substrate with a low doping level of the type, comprising a separated vertical PNP transistor with a buried p-type collector layer with at least a high doping level; , vertical NPN transistor, horizontal PNP transistor, horizontal N-MOS transistor, horizontal P-MO
The S transistor is integrally formed on the substrate.

Further, the method for manufacturing a bipolar CMOS semiconductor device of the present invention includes a step of doping Sb between the substrate and the first epitaxial layer to form a highly concentrated diffusion layer, and a step of doping boron between the first and second epitaxial layers. Steps of forming a collector buried layer and N-M from the top of the second epitaxial layer.
The process includes doping the same boron as the well diffusion layer of the OS transistor to form a well diffusion layer, and by heat treatment, the collector buried layer and the well diffusion layer are simultaneously stretched from above and below to make contact, and the collector low A vertical PNP with a concentration layer of 1 to 2 x 1016 cm-', a collector-emitter breakdown voltage of 12 V or more, and a collector-buried layer sheet resistance of 100 to 50,007 mm.
Bipolar CM so that transistors can be obtained
It manufactures OS semiconductor devices.

As a result, a vertical PNP transistor with a low-resistance p-type collector is formed in the shallow epitaxial layer grown at least twice, resulting in a high CE breakdown voltage (a vertical PNP transistor with a large gain bandwidth). Therefore, high-speed, high-performance vertical NPN transistors and vertical PNP transistors, and horizontal PNP transistors having complementary characteristics suitable for analog circuits are obtained.
It is possible to provide a bipolar CMOS semiconductor device integrally configured with a CMOS transistor suitable for a digital circuit, and a method for manufacturing the same.

〔Example〕

Examples will be described below. FIG. 1 is a sectional view showing an embodiment of a bipolar CMOS semiconductor device according to the present invention, and FIGS. 2 to 7 are process diagrams showing a method for manufacturing the same. Next, the manufacturing process of the embodiment of the present invention will be explained based on FIGS. 2 to 7. First, as shown in Figure 2, a thick oxide film 2 of about 1 μm is formed on a p-type single crystal silicon substrate 1 doped with boron and having a resistivity of 2 to 20 Ω, and then selected using normal photolithography technology. The oxide film 2 is etched, and then thermal diffusion is performed using Sb to form a vertical NPN buried layer 3 with ρs = 10 to 20Ω.
Transistor and PNP transistor area, horizontal PN
They are formed in the P transistor region and the P-MOS transistor region. Note that the substrate orientation is not specified.

Next, epitaxial growth is performed, and this epitaxial region is an important device constant that determines the CE breakdown voltage and transition frequency f of the vertical NPN transistor. CB breakdown voltage is 15V or more, f is 1GHz
In order to ensure the above and to guarantee a sufficiently low collector resistance with a fine emitter size, the epitaxial layer thickness is 2.5 to 5.
．． 5, and vertical P is formed in this epitaxial layer.
It is necessary to form the p-buried layer of the NP transistor with a low sheet resistance of 500Ω/□ or less. In order to form a low resistance p3 buried layer of a vertical PNP transistor in this shallow epitaxial layer, the epitaxial region must be formed using a two-layer technique.

The reason for this is that the diffusion constant of the p1 impurity (boron) in the high concentration n diffusion layer is approximately one order of magnitude lower than that in the low concentration Si (
R, B Fair Concentration P
rofilesof Diffused Dopant
s in 5ilicon'' in F, F, Y.

Wang + Ed, + Impurity Do
Ping Processes 1nSt! 1co
n, North-11o11and, New
York + 1981 Chapter 7) phenomenon, the n゛ diffusion layer 3 doped with Sb or 8S
This is because it is impossible to form a p-buried layer by double diffusion with.

First, as shown in FIG. 3, a first epitaxial growth is performed to form a first epitaxial layer 4.

Then, using ordinary photolithography technology and ion plantation technology, a high concentration p9 buried layer 5 (20
0 to IKΩ/□) and low concentration p+ buried layer 6 for isolation between elements
(500 to 5 Ω/[l) is formed by boron ion implantation. These two buried layers may be used together, and in order to improve the launch amplifier resistance, N-MOS
It is better to create it also in the well part of the transistor.

The first epitaxial layer 4 contains Pl;tSb as a dopant, and has a thickness of 0.5x l in order to increase the bunch-through voltage of the vertical NPN transistor to 20V or higher.
Q I 6-3 ×1016. , at a high concentration of -3, 1
．． It is formed within the range of 0 to 2.0 μm. This thickness is determined so that the p-buried layer 6 is connected to the p-type impurity region of the substrate l in the completed state, and that the high concentration p-buried layer 5 and the n-buried layer 3 are connected to the p-type impurity region of the substrate l.
It is necessary to optimize to avoid contact at a high concentration of QII+, -1 or higher.

Next, after a heat treatment is performed for the purpose of recovering the damaged layer caused by the ion implantation, a second epitaxial growth is performed to form a second epitaxial layer N7, as shown in FIG. This second epitaxial layer 7 is composed of 2~], 0
The second epitaxial layer 7 is formed to have a thickness of 1.5 to 3.5 μm with a concentration of
1GH by reducing collector resistance of NP transistor
This is an essential technology to ensure high-speed performance exceeding z and to suppress parasitic thyristor operation, and the thickness and concentration of this epitaxial layer 7 must be carefully set to optimize the performance of the five components. There is.

FIG. 8 shows CE, breakdown voltage, (T″ax, and vertical PN
It shows the change in the punch-through breakdown voltage of the B-N terminal of the P transistor. As you can see from this figure, if you increase the thickness, C
E, breakdown voltage increases, but f, ``'', BN breakdown voltage decreases. The optimal value of the thickness of the second epitaxial layer 7 is 2.5~
3.0 μm, and the variable range is 1°5 to 3.5 μm.

The first layer of the two-layer stack described above. The second epitaxial layer 4.7 includes a p layer buried under the p well of the M2S portion and a P-MOS.
This is an important technique that prevents the n-buried layer placed under the n-well of the transistor from coming into contact with a high concentration. That is, since the surfaces on which the n' buried layer and the p' buried layer are formed are not the same with the first epitaxial layer 4 in between, it is possible to avoid contact of the peak high concentration layers with each other. As a result, the total amount of charge in the p' buried layer is QF '': i 5 X IQ'' ~ l
Even when the concentration is increased to 1914 cm −2 , the interwell breakdown voltage can be maintained at IOV or higher. This makes it possible to theoretically increase the launch amplifier resistance by one order of magnitude compared to the conventional one.

After forming the second epitaxial layer 7, the n-type collector electrode portion 8, 1) type well diffusion layer 9. An n-type well diffusion layer 10 is formed by ion implantation. The n-type well diffusion layer 10 is used for an n-well region of a P-MOSI transistor, for a field channel stopper of a vertical NPN transistor, for a field channel stopper of an isolation part of a vertical PNP transistor, and for a field channel stopper of a vertical PNP transistor.
Used as the base region of NP transistor. In the vertical NPN transistor, the Vth of the field MOS must be secured to 15V or more, and the CB must be sufficiently high.
In order to ensure a high breakdown voltage, it is formed at a distance of 2 to 5 μm from the base region and with a width of 2 to 4 μm. In addition, in vertical PNP transistors, the base width is 2 to 5 μm in order to ensure a breakdown voltage of 15 V or more between -3UB and 2 to 4 μm in width.
μm and ensure a CE breakdown voltage of 1.5V or more, and 50V
In order to secure the above early voltage, the n-type well diffusion layer 10 is required.

Further, the n-type well diffusion layer 9 is used in the collector low concentration region of the vertical PNP transistor as well as the n-well region of the N-MOS transistor.

Said n-type collector electrode section 8. The conditions for ion implantation into the n-type well diffusion layer 9 and the n-type well diffusion layer 10, together with the following stretching process, must satisfy the following requirements from the device side. That is, ■ the diffusion distance Xj of the n-type well diffusion layer 10 and the n-type well diffusion layer 9 is 1/2 of the thickness of the second epitaxial layer 7, and ■ the diffusion depth Xj of the n-type collector electrode section 8. is greater than or equal to the thickness of the second epitaxial layer; ■The surface concentration of the n-type well diffusion layer 10 and the n-type well diffusion layer 9 is 3 to 7×1016c.
It is necessary that m-'. This value is for vertical PN
P transistor breakdown voltage, knee current, N-MOS and P-
Source/drain breakdown voltage of MOS transistor, vertical NP
This is an important parameter that satisfies all the requirements of the isolation breakdown voltage of N transistors and vertical PNP transistors, and the CE breakdown voltage of horizontal PNP transistors.

For example, the surface concentration of the n-type well diffusion layer 9 forming the n-well region of an N-MOS transistor is set to 3 to 7×10
16CI11-3, and x4 of the moontsuko diffusion layer is 1.0.
The second epitaxial layer 7 is set to a range of ~1.5 μm.
By setting the thickness of p to 1.5 to 3.5 μm, p
゛Buried layers 5 and 6 and 5XIO"~2x10"cm-"
The vertical PNP
The CE breakdown voltage of the transistor is 12V or more, [1 is IGII]
z or more is possible.

Next, as shown in FIG. 5, sufficient heat treatment is performed to stretch and diffuse the well region. Next, boron ions are implanted into the isolation region to form the channel stopper layer 11.
form. Note that this channel stopper layer 11 covers the base-n" raised portion of the vertical PNPI transistor and the N
- Also used to prevent channel leakage of MOS transistors.

Next, as shown in FIG. 6, selective oxidation is performed using a conventional Si3Nm film as a mask, leaving the active layer and the electrode lead-out portions. Next, the n-type diffusion layer 12 is formed into a vertical type N
The base region of the PN transistor and the collector region of the lateral PNr' transistor are formed by ion implantation. Next, an n-type diffusion layer 13 is formed in the base region of the vertical PNP transistor by ion implantation. These two types of diffusion layers 12 and 13 are designed to facilitate control of the current amplification factor hFE of the bipolar transistor and to improve performance.
They are formed by separate and independent ion implantation with different energy doses.

Next, as shown in FIG. 7, a thin gate oxide film 14 of 200 to 300 layers is formed on the entire surface, and then immediately subjected to low pressure CVD.
Polycrystalline silicon is laminated by a method. Next, P or As is diffused into the polycrystalline silicon, and a gate electrode 15 is formed using normal photolithography. The thickness of the polysilicon gate electrode is 400 to 500n111, and ρ
, is preferably 30 to 50Ω/□ or less.

Next, in order to reduce the number of masks and the number of steps, vertical PN
P transistor emitter 16 and collector raising electrode 17. External base of vertical NPN transistor 18.
Emitter 19 and external collector 20.21 of the lateral pNP transistor. A shallow P diffusion layer is provided which also serves as the source/drain part 22 of the P-MOS transistor and the lower electrode of the substrate, and a vertical NP diffusion layer is provided.
N transistor emitter 23 and collector raising electrode 24. External base 25 and N of vertical PNP transistor
Terminal lifting electrode 26. External base electrode 27 of lateral PNP transistor. Also, a shallow n' diffusion layer is provided which also serves as the source/drain part 28 of the N-MOS transistor.

The shallow p1 diffusion layer is made using BFz”, 30~5
QkeV, 3-1 (IXIO"cm-' ion implantation, shallow n' diffusion layer is formed using As', 100-180keV, 3-10XIO"cm)
-" is formed by ion implantation. Next, a heat treatment is performed to remove defects and activate it, and an oxide film (usually using BPSG or PSC) is formed by CVD method, and a contact hole is opened by normal photolithography. .

Next, the electrode material A1 or AI containing Si.

The bipolar CMOS according to the present invention as shown in FIG.
A semiconductor device is obtained.

As described above, although the manufacturing method according to the present invention can produce a high-performance plate with an extremely wide variety of components, each individual process is an extremely simple and conventional method that mainly uses photolithography and ion plantation. This is extremely effective in reducing costs.

In the vertical NPN transistor manufactured by the above manufacturing method, as a condition for forming an emitter base diffusion layer, a polysilicon emitter, which has various problems at the interface, is not used, and in order to compensate for this, the energy during emitter ion implantation is The electrode is made large to 180 ke■, and the emitter Xj is ensured to be 0.2 μm or more to improve the electrode heat resistance. Also, the energy used in ion implantation to form the base is different from that of ordinary shallow NPN transistors, and a relatively high energy of 40 to 7 Gke V is used.

In addition, in vertical PNP transistors, as conditions for forming an emitter base diffusion layer, boron is formed in the form of B F 2 at 30 to 50 ke V to make the emitter shallow, achieving x7-0.3 μm. .

In addition, the ion implantation conditions for base formation are consistent with these, and in order to make the base shallower, phosphorus is added at 120 to 180 ke.
Ions are implanted with high energy of V.

In addition, in lateral PNP transistors, in order to increase the injection effect into the emitter, a p diffusion layer, which forms the source and drain layers of a P-MOS transistor, is used to form a layer with as high a concentration as possible, and in the collector region. In order to increase carrier capture efficiency, a p-type diffusion layer is used to form the base region of the vertical NPN transistor.

Further, the isolation is composed of a three-layer stack of a low concentration p1 buried layer 6, a p well diffusion layer 9, and a channel stopper layer 11, and a high concentration p1 buried layer is used for the substrate pulling part.

FIG. 9 shows an impurity profile showing the impurity concentration distribution in the depth direction of each component configured as described above. 8 is a vertical PNP transistor, ■) is a vertical NPN
In the transistor, (C1 is a lateral N-MOS transistor, fD) is an impurity profile of a lateral P-MOS transistor, and the symbols indicate the concentrations in the portions indicated by the same symbols in FIG.

Next, the device performance achieved in each component of the bipolar CMO8 semiconductor device obtained as described above will be shown below.

(1) Vertical PNP transistors have unprecedented high speed, high gain, and high knee current.
A device complementary to the transistor was obtained. That is, gain bandwidth: maximum 1.0 to 1.5 GHz (especially at low current 0.1 mA, 0.8 Gllz or more) current gain: 50
~100 Knee current: 5mA or more (emitter size 4μm x 1
(0 μm) CE-to-CE breakdown voltage = 12 V or more (2) In the N-type NPN transistor, a device with a sufficient gain bandwidth necessary for analog circuits including a video band and a small element size was obtained.

Gain bandwidth: max. 3.0-5.0 GHz (especially at low current 0.1 mA], 5 CIlz or more) Current gain: 10
0~200 Knee current: 5mA or more (emitter size 2μm
5 μm) CE breakdown voltage: 12 V or more In a lateral PNP transistor, a device with a low gain bandwidth due to holes accumulated in the epitaxial region can be obtained. This allows the circuit to be used for special purposes such as delay circuits.

Also, by simply changing the base width layout, C
The withstand voltage between E can be increased.

Gain Bandwidth: 20-50 Mllz Current Gain = 2
Breakdown voltage between 0 and 50 CE: 20■ or more +41 In the N-MOS transistor, characteristics suitable for an interface circuit with a microprocessor were obtained.

Mutual conductance at saturation: 50 to 65 s/mSD withstand voltage: 12■ or more (in the 51P-MOS transistor, the above NMO
Sufficient characteristics were obtained to form a complementary circuit with the S transistor.

Saturation phase pressure conductance: 20 to 35 s/m SD withstand voltage = 12 V or more, characteristics of each component are bipolar CMOS that performs analog data processing centered on video signal processing.
It is the most suitable for the circuit. Particularly high gain bandwidth, current gain, and knee current can be obtained with vertical PNP transistors, making them ideal for differential amplifiers and PCs using PNP transistors.
I-circuits and complementary circuit configurations that combine unprecedented high speed and high accuracy are possible.

In the embodiment shown in Fig. 1 above, in order to increase the element breakdown voltage and reduce the parasitic capacitance of the element, the highly concentrated diffusion layer was not brought into contact with the other. For this purpose, it is also possible to make the n-buried layer 3 and the p-buried layer 6 in contact with each other. In this case, due to problems with alignment accuracy, the element size is reduced by about 2 to 4 μm. Further, in this case, it is more effective to arrange the n-well diffusion layer 10 in the vertical NPN transistor over the entire active layer. However, CB withstand voltage, cB withstand voltage, CS surface 1
Both pressures decreased to 1/2, and etc., CTS decreased to 2
~5 times increase.

Furthermore, although the embodiment shown in FIG. 1 shows an example in which only active elements are formed as constituent elements, the bipolar CMOS semiconductor device according to the present invention has a resistor, a MOS capacitor, and a diffusion capacitor integrated at the same time. It is also possible to form In the case of resistors, six types of resistors are available: n-type diffused resistor, n-type diffused resistor, polysilicon resistor, n-type pinch resistor, and p-type pinch resistor, and another diffusion layer is added to form the resistor. You can also do that.

FIG. 10 shows an n-type diffused resistance. The diffusion layer 12 determines the resistance value, and is the same as the diffusion layer for forming the base of the vertical NPN transistor. The resistance value due to this diffusion layer is 1.5 to 2.5 Ω/□. If a lower sheet resistance is required or more precise control is required, a separate diffused resistor can be created using conventional photolithography and a diffused layer. Note that the electrode portion of the diffused resistor shown in FIG. 10 utilizes a high concentration p diffusion layer 18 in order to reduce contact resistance.

FIG. 11 similarly shows a pinch high resistance using the base region of a vertical NPN transistor, and 31 is an n diffusion layer. FIG. 12 shows an n-type diffused resistor using an n-diffused layer 13 forming the base region of a vertical PNP transistor. FIG. 13 shows a polysilicon resistor using polysilicon 33 formed on a selective oxide film 32-1, and FIG. 14 shows a polysilicon resistor using polysilicon for a gate electrode, which is automatically formed when creating a MOS transistor. 34 is shown. Furthermore, in the semiconductor device shown in FIG. 1, the heavily doped p-buried layer 5 can be used to form a p-type resistor through which a high current can flow.

Further, in the embodiment shown in FIG. 1, in order to reduce the number of masks during manufacturing, the emitter diffusion layer of the bipolar transistor is formed of the same diffusion layer as the source and drain of the MOS transistor. However, in order to control the current amplification factor hFE of the bipolar transistor and to make the base region shallower, it is necessary to form the bipolar transistor with a diffusion layer separate from that of the MOS transistor, or with a passivation CvD film (usually BPSG or PSG) in the emitter region. )
A method of forming an opening first and then forming an n'' diffusion layer in the emitter section in a self-aligned manner, or using polysilicon as an electrode and obtaining a shallow junction by in-phase diffusion from within the polysilicon. etc. are also applicable.

Regarding the electrode structure, simple AI or A containing Si
Although the one using one electrode is shown, in consideration of improving the heat resistance of the electrode and especially reducing the emitter resistance, PtSi or Ti is used.
Silicidation with high melting point metals such as Si, and TiN,
It is also possible to use a barrier metal made of a high melting point metal such as TiW or W or an alloy.

As shown below, according to the present invention, the gain bandwidth IG 1
Since a bipolar CMOS semiconductor device is constructed by combining high-performance vertical PNP transistors that are 17 or more and are complementary to vertical NPN transistors, for example, 1
) IN diode, AP diode, and even one-dimensional,
When you want to process the signal of a two-dimensional photo array sensor, the output signal may be low and close to the GND level, but since it can be differentially amplified using a vertical PNP transistor, it can be processed at high speed with a single power supply. High gain allows for highly accurate control. Therefore, the semiconductor device according to the present invention can be applied to ICs that process signals using conventional vertical transistors, whether for consumer use or industrial use.
When integrating sensor interfaces, microprocessor interfaces, etc., not only can great capabilities be brought out, but it is also possible to create high-speed, high-precision ICs that have never existed before.

[Technology of invention]

As described above based on the embodiments, according to the present invention, a high-speed, high-performance vertical PNP transistor with a high CB breakdown voltage and a large gain bandwidth can be obtained. It is possible to provide a bipolar CMOS semiconductor device in which a usable vertical PNP transistor, a horizontal PNP transistor, and a CMOS transistor are integrated. Further, according to the manufacturing method of the present invention, it is possible to provide a method for manufacturing a bipolar CMO8# and conductor device that can easily improve the performance of each component.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing an embodiment of a bipolar CMOS semiconductor device according to the present invention, and FIGS. 2 to 7 are views showing the manufacturing process of the semiconductor device shown in FIG. 1, and FIG. is the vertical NPN with respect to the thickness of the second epitaxial layer.
CE o of transistors and vertical PNP transistors
A diagram showing the relationship between the breakdown voltage and the punch-through breakdown voltage of the B-N terminal of a vertical PNP transistor, Figure 9-(0) shows the impurity profile of each component of the semiconductor device shown in Figure 1. Figure 10 shows an n-type diffused resistor, Figure 11 shows a pinch n-type diffused resistor, and Figure 12 shows a
FIG. 13 is a diagram showing an n-type diffused resistance, FIG. 13 is a diagram showing a polysilicon resistance, and FIG. 14 is a diagram showing a MOS capacitance. In the figure, 1 is a substrate, 2 is an oxide film, 3 is an n-type buried layer,
4 is a first epitaxial layer, 5 is a high concentration p-type buried layer, 6 is a first epitaxial layer;
is a low concentration p-type buried layer, 7 is a second epitaxial layer, 8 is an n-type collector electrode section, 9 is a p-type well layer, 10 is an n-type well layer, 11 is a p-type channel stopper layer, and 12 is a p-type Diffusion layer, 13: n-type diffusion layer, 14: gate oxide film, 15: electrode to gate 1, 16: emitter of vertical PNP transistor, 17: collector pull-up electrode, 18: vertical NPN
external base of the transistor, 19 is the emitter of the lateral PNP transistor, 20.21 is its collector, 22 is the P
-The source/drain part of the MOS transistor, 23 is the emitter of the vertical NPN transistor, 24 is the collector pull-out electrode, 25 is the external base of the vertical PNP transistor, 26 is the N terminal pulling electrode, 27 is the horizontal PNP
The external base of the transistor, 28 indicates the source/drain portion of the N-MOS + transistor. Patent applicant: Olympus Optical Industry Co., Ltd.

Claims (1)

Claims: 1. A plurality of epitaxially grown layers on a single monolithic semiconductor substrate having a low doping level of a different type than the epitaxially grown layers grown in at least two separate stages with a low doping level. A semiconductor device configured as a circuit component comprising at least a separated vertical PNP transistor with a buried p-type collector layer having a high doping level, a vertical NPN transistor, a lateral PNP transistor, and a lateral N-M transistor.
A bipolar CMOS semiconductor device comprising an OS transistor and a lateral P-MOS transistor. 2. The low doping level semiconductor substrate is boron-doped p^ with a resistivity of 2-20 Ωcm.
- It is composed of a single crystal silicon wafer, and the epitaxial growth layer is 0.5 to 3 x 10^1^6 cm^
-^3 P or Sb doped thickness 1.0~2.0μ
m n-type first epitaxial layer, and 2 to 10×10^1
^5cm^-^3 P or Sb doped thickness 1.5
The collector buried layer of the vertical PNP transistor is formed by doping boron at a high concentration between the first epitaxial layer and the second epitaxial layer. 2. The element isolation region and the well lead-out electrode portion of the N-MOS transistor are formed by doping boron at the same concentration or at a low concentration as the collector buried layer. bipolar CMOS semiconductor device. 3. The vertical type is formed by the Sb-doped n-type buried layer formed between the substrate and the first epitaxial layer and the n-type diffusion layer formed by diffusing phosphorus from the first epitaxial layer and the second epitaxial layer. A vertical PNP transistor portion is provided in which a PNP transistor is surrounded by a PN junction, a collector region and a substrate region of the vertical PNP transistor are electrically separated, and an electrode extraction portion for setting the potential of the n-type buried layer is formed. 3. The bipolar CMOS semiconductor device according to claim 1, further comprising a bipolar CMOS semiconductor device. 4. The Sb-doped n-type buried layer formed between the substrate and the first epitaxial layer is used as a collector region, and the n-type diffusion region diffused from the second epitaxial layer is used for punch-through and channel leakage between the base and the substrate. 4. The bipolar CMOS semiconductor device according to claim 1, further comprising a vertical NPN transistor serving as a prevention layer. 5. The first epitaxial layer and the second epitaxial layer are spatially shifted in the vertical direction with respect to the highly doped n-type buried layer formed between the substrate and the first epitaxial layer directly under the P-MOS transistor. formed by a relatively low concentration p-type buried layer formed between the layers and a diffusion layer formed simultaneously with the low concentration collector layer of the vertical PNP transistor,
It has a p-well region whose surface concentration is controlled to 3 to 7 x 10^1^6 cm^-^3, and it has latch-up resistance by reducing the resistivity under the well while maintaining the interwell breakdown voltage at 15V or more. 5. The bipolar CMOS semiconductor device according to claim 1, further comprising an N-MOS transistor with improved performance. 6. at least a vertical NPN transistor on a single monolithic semiconductor substrate having a low doping level of a different type than the epitaxially grown layer grown in at least two separate growths with a low doping level; In the method for manufacturing a bipolar CMOS semiconductor device including a vertical PNP transistor, a lateral PNP transistor, a lateral N-MOS transistor, and a lateral P-MOS transistor, Sb is provided between the substrate and the first epitaxial layer. A step of doping to form a high concentration diffusion layer, a step of doping boron between the first and second epitaxial layers to form a collector buried layer, and a step of doping N-MO from above the second epitaxial layer.
forming a well diffusion layer by doping the same boron as that of the well diffusion layer of the S transistor, and by heat treatment, the collector buried layer and the well diffusion layer are simultaneously stretched from above and below to contact each other, and the collector low Make the concentration layer 1 to 2 x 10^1^6 cm^-^3,
Vertical PN with collector-emitter breakdown voltage of 12V or more and collector-buried layer sheet resistance of 100 to 500Ω/□
A method for manufacturing a bipolar CMOS semiconductor device, characterized in that a P transistor is obtained. 7. The emitter and collector raised electrode regions of the vertical PNP transistor, the external base region of the vertical NPN transistor, the source/drain region of the P-MOS transistor, and the emitter/collector region of the lateral PNP transistor as necessary, with the total charge amount 3~20×10^1^5c
m^-^2 p-type heavily doped diffusion layer, and also forms the emitter and collector regions of the vertical NPN transistor, the external base region of the vertical PNP transistor, and the N-M
The source/drain regions of the OS transistor are formed by As-doped n-type transistors with a total charge of 5 to 15 x 10^1^5 cm^-^2.
7. The method of manufacturing a bipolar CMOS semiconductor device according to claim 6, wherein a high concentration diffusion layer is formed at the same time. 8. The base region of the vertical PNP transistor has an energy of 40 to 70 keV and a dose of 5 to 10×10^1
Claim 6 characterized in that it is formed by performing shallow diffusion by an independent ion implantation process of ^3 cm^-^2.
Or the method for manufacturing a bipolar CMOS semiconductor device according to 7. 9. Vertical NPN formed by diffusion from the second epitaxial layer
Isolation region between base and substrate of transistor, horizontal PNP
The base region of the transistor and the n-well region of the P-MOS transistor are coated with a surface concentration of 2 to 5 x 10^1^6 cm.
9. Any one of claims 6 to 8, characterized in that ^-^2 n-type diffusion layers are formed at the same time to improve the collector-emitter breakdown voltage of the lateral PNP transistor and the source-drain breakdown voltage of the P-MOS transistor. A method for manufacturing a bipolar CMOS semiconductor device according to claim 1.