JPH02276271A - Bipolar cmos semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To decrease a collector in series resistance so as to obtain a vertical PNP transistor of small parasitic effect by a method wherein a P-type collector buried layer and a P-type collector diffusion layer are extended by a thermal treatment to be brought into contact with each other, and the sheet resistance of the collector buried layer is set within a specific range of value. CONSTITUTION:Sb is thermally diffused to form an N<+> buried layer 3 in an NPN transistor region and a PNP transistor region both of vertical type and a PNP transistor region and a P-MOS transistor both of lateral type respectively. then, a first epitaxial layer 4a is formed. A high concentration P<+> buried layer 5 (500OMEGA-1.5kOMEGA/square) and an inter-element isolating low concentration P<+> buried layer 6 are formed by the implantation of boron ions. Next, a thermal treatment is carried out, and then a second epitaxial layer 4b is formed. A P-type collector 7, an N-type collector electrode member 8, and a P-type well diffusion layer 10 are formed through ion implantation. Then, diffusion is promoted through an enough thermal treatment to extend a well region.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention provides vertical NPN transistors and
Bipolar C with $1 type PNP transistor, lateral type PNP transistor and complementary MOS transistor formed
The present invention relates to a MOS semiconductor device and its manufacturing method.

(Conventional technology) Conventionally, sensors, analog circuits,
Regarding semiconductor devices in which electronic circuits such as digital circuits and actuator drive circuits are configured on the same monolithic substrate, for example, Japanese Patent Laid-Open No. 52-2292 and Japanese Patent Laid-Open No. 54
Bipolar CMOS semiconductor devices for digital circuits, in which a CMOS transistor and a bipolar NPN transistor are integrally formed, have been proposed in Japanese Patent Application Laid-open No. 52-106278 and Japanese Patent Application Laid-Open No. 57-188862. No., Japanese Patent Publication No. 60-72255
No. 62-219555 discloses a bipolar CMOS semiconductor device for analog circuits that includes a vertical PNP transistor that can be formed simultaneously without increasing the number of masks. Furthermore, Japanese Patent Laid-Open No. 62-247558 and other publications propose means for realizing as many elements as possible using a bipolar CMOS process. However, these conventionally proposed semiconductor devices are constructed using only two types of buried layers, p-type and n-type, and a diffusion layer from the epitaxial surface using epitaxial layers grown on the same substrate. Therefore, it is almost impossible to simultaneously satisfy the breakdown voltage, current amplification factor, and high frequency characteristics of all elements.

On the other hand, in the field of compound semiconductors such as semiconductor lasers, HEMTs, and MODFETs, multiple epitaxial technology to obtain a head-to-head structure is a common technology, and it is also used especially for vertical PNP transistors, which are difficult to create. As a means to lower the collector resistance, a method of performing epitaxial growth twice is disclosed, for example, in Japanese Patent Laid-Open No. 49-3.
No. 6291, JP-A-49-52987, JP-A-57-
157567, etc., and the idea of using multiple epitaxial technology to integrate elements with different breakdown voltages is disclosed in, for example, JP-A-53-54983 and JP-A-54.
This method has been proposed in No. 47493, Japanese Unexamined Patent Publication No. 57-197640, etc. However, these semiconductor devices using multiple epitaxial techniques are only devices that integrate individual or two devices in a limited range.

In semiconductor devices, digital circuits require low power consumption and high-speed CMOS circuits, and analog circuits require relatively high breakdown voltage of 15V or higher, as high an early voltage as possible, and a gain bandwidth of IGHz.
High-performance vertical NPN with broader and more complementary characteristics than above.
and vertical PNP transistor circuits, but there is still no known bipolar CMOS semiconductor device that improves the performance of at least these four basic devices.
Currently, CMOS manufacturing technology is not well known.

[Problem to be solved by the invention] As mentioned above, the conventional technology is a high-speed static R
A vertical NPN bipolar transistor developed for AM that has a high gain bandwidth but has an extremely low collector-emitter breakdown voltage of less than 8cm and a low early voltage of about 20V.
A combination of short-channel CMOS transistors or an integrated CMOS transistor with vertical PNP and NPN transistors with a relatively low gain bandwidth of less than 0.3 Gl (z) for operational amplifiers and analog circuits. This is what I did.

By the way, peripheral circuits for sensors that operate at high speeds, such as high-speed cameras, require the ability to process input signals of any level at high speed in order to fully utilize their high-speed performance. The transistor has a gain bandwidth exceeding IGHz, a relatively high collector-emitter breakdown voltage of 15V or more, an early voltage of 30V or more, and a vertical PNP transistor with a high knee current, and a gain bandwidth exceeding 3GHz. A bipolar CMOS semiconductor device equipped with a high-speed vertical NPN transistor having a relatively high collector-emitter breakdown voltage of 15 V or more and an early voltage of 50 V or more and a high-speed CMOS device has become indispensable.

However, conventional semiconductor devices including vertical PNP transistors have a problem in that they cannot have characteristics compatible with peripheral circuits of such high-speed sensors.

And as mentioned above, a vertical PNP with a high gain bandwidth
In order to form bipolar CMOS semiconductor devices including transistors on the same substrate, the following techniques are used: (1) High concentration of ρ in a shallow epitaxial region
.

(Technology for forming a buried layer) A shallow PN2M diffusion transistor can be fabricated using a shallow NPN transistor with NP double diffusion and C
A technique is required to simultaneously form the source/drain junction of a MOS transistor with high precision.

The present invention was made in order to solve the above-mentioned problems in conventional bipolar CMOS semiconductor devices. High-speed vertical PNP with high current
An object of the present invention is to provide a bipolar CMOS semiconductor device including a transistor.

(Means and Effects for Solving the Problems) In order to solve the above-mentioned problems, the present invention provides an epitaxial growth layer having a low doping level and grown in at least two steps, which is different from the epitaxial growth layer. In a semiconductor device comprising a plurality of circuit components on a single monolithic semiconductor substrate having a low doping level, at least a buried p-type collector layer having a high doping level, a second epitaxial layer, and diffusion into the epitaxial layer. A vertical PNP transistor having a base region formed with an n-type diffusion layer, and a vertical NPN
transistor, lateral PNP transistor, and lateral N-
A MOS transistor and a lateral P-MOS transistor are integrally formed on a substrate.

Further, the method for manufacturing a bipolar CMOS semiconductor device of the present invention includes a step of doping Sb between the substrate and the first epitaxial layer to form a highly concentrated diffusion layer, and a step of doping boron between the first and second epitaxial layers. A step of forming a p-type collector buried layer, and doping a p-type collector diffusion layer by doping boron at a higher concentration than the well diffusion layer of the N-MOS transistor from the upper part of the second epitaxial layer surrounding the base activation region. The collector is A bipolar CMOS semiconductor device is manufactured by lowering the series resistance to 200Ω or less to obtain a vertical PNP transistor with small parasitic effects.

This allows the base to have a low-resistance p-type collector in a shallow epitaxial layer that is grown at least twice, and also has a second epitaxial layer and an n-type diffusion layer that is diffused into the epitaxial layer. Since a vertical PNP transistor having a region is formed, the vertical PNP transistor has a high CE breakdown voltage and early voltage, and a large gain bandwidth.
Transimeta is obtained. Therefore, high-speed, high-performance vertical NPN with complementary characteristics suitable for analog circuits) Langimeta and vertical PNP) Langimeta and horizontal PNP
It is possible to provide a bipolar CMOS semiconductor device that integrally includes a transistor and a CMOSI-range metal suitable for a digital circuit, and a method for manufacturing the same.

〔Example〕

Examples will be described below. FIG. 1 is a cross-sectional view showing one embodiment of a bipolar CMOS semiconductor device according to the present invention, and FIGS. 2 to 7 are process diagrams showing the manufacturing method thereof. The manufacturing process of the embodiment of the present invention will be explained based on FIG. First, as shown in Fig. 2, a thick oxide film 2 of about 1 μm is formed on a p-type single crystal silicon substrate 1 doped with boron and having a resistivity of 2 to 20 Ω·1, and selected using normal photolithography technology. The oxide film 2 is selectively etched and then thermally diffused using Sb to form the n0 buried layer 3 with ρ3=lθ~20Ω as a vertical NPN.
) range meta and PNP ) range meta area, horizontal PN
P) are formed in the range meta region, and P-MOS) are formed in the range meta region. Note that the substrate orientation is not specified.

Next, epitaxial growth is performed, and this epitaxial region is an important device constant that determines the CE breakdown voltage and the transition frequency ft of the vertical NPN transistor. When the CE withstand voltage is 15V or more, f? 10) f
In order to ensure z or higher and to ensure sufficiently low collector resistance with a small emitter size, the epitaxial layer thickness should be 2.5~2.
A p'' buried layer of a vertical PNP transistor is formed in this epitaxial layer with a thickness in the range of 500 to 15.
It is necessary to form it with a low sheet resistance of 00Ω/□. In order to form a low resistance 20 buried layer of a vertical PNP (range metal) in this shallow epitaxial layer, the epitaxial region must be formed using a two-layer technique.

The reason for this is that the diffusion constant of the p0 impurity (boron) in the high concentration n9 diffusion layer is approximately one order of magnitude lower than that in the low concentration Si (
R, B Fair Concentration P
rofilesof Diffused Dopant
a in 5ilicon In F, F, V.

Wang, Ed, + Impurity Do
ping Processes 1nSilico
n, North-Holland, New Y
orkt 1981+Chapter 7) phenomenon, the 2° diffusion layer 3 doped with Sb or A3
This is because it is impossible to form a p° buried layer by heavy diffusion.

First, as shown in FIG. 3, a first epitaxial growth is performed to form a first epitaxial layer 4a. Then, using normal photolithography technology and ion implantation silane technology, a high concentration p° buried layer 5 is formed.
(500Ω to 1.5Ω/□) and a low concentration p° buried layer 6 (IKΩ to 5Ω/□) for isolation between elements are formed by boron ion implantation. These two buried layers may be used together, and in order to improve latch-up resistance, N-
It is better to form it also in the well part of the MOS transistor.

Note that the first epitaxial layer 4a is doped with P or Sb, and has a thickness of 0.5×1 in order to increase the punch-through voltage between 83 and 20V or more of the vertical NPN l-range metal.
At a high concentration of 015 to 3 x 1015C11-2, 1.
It is formed within the range of 0 to 2.0 μm. This thickness is determined by the fact that the P buried layer 6 is connected to the p-type impurity region of the substrate l in the completed state, and that the high concentration p99 buried layer 5 and the n8 buried layer 3 are 10
It is necessary to optimize so that contact does not occur at a high concentration of "cm-" or higher.

Next, after heat treatment is performed for the purpose of recovering the damaged layer caused by ion implantation, a second epitaxial growth is performed as shown in FIG.
form. This second epitaxy +/L/ layer 4b is 2
~l0×1015cm-'nofi degree, 1.5-3.5
Formed to a thickness of gm. This second epitaxial 14
b forms the collector low concentration region of the vertical NPN range meta and also becomes a part of the metallurgical base of the vertical PNP transistor. Since the base low concentration layer consisting of the second epitaxial layer 4b needs to be depleted in actual use, the second epitaxial layer 4b is
The concentration of b needs to be sufficiently low. In addition, this second epitaxial layer 4b is an essential technology for realizing high speed performance higher than 1G&, high CE breakdown voltage, and high early voltage.
Furthermore, the thickness and concentration of this epitaxial layer 4b must be carefully set to optimize the performance of the five other components listed above.

Figure 8 shows the changes in CB, breakdown voltage, f, 88M, and punch-through breakdown voltage of the B-N terminal of the vertical PNP transistor when the thickness of the second epitaxial layer 114b is used as a parameter. Increasing the thickness as shown above increases the CE e breakdown voltage, but [, -all, B-N
Pressure resistance decreases. The optimal value of the thickness of the second epitaxial layer 4b is 2.5 to 3.0 μm, and the variable range is 1.5 to 3.0 μm.
It is 3.5 μm.

The first layer of the two-layer stack described above. Second epitaxial layer 4a, 4
b shows the 20 layers buried under the p-well of the MOS part and the P-M
This is an important technique to prevent the n'' logic layer placed under the n-well of the OS transistor from contacting with a high concentration.
Since the surfaces on which the buried layer and the p44 buried layer are formed are not the same through the first epitaxial layer 4a, it is possible to avoid contact of the peak high concentration layers with each other. As a result, the total charge amount of the p buried layer is QP 5 Xl013~I ×10
Even when the concentration is increased to 15CI-'', the interwell breakdown voltage is IO
V or more can be secured. This makes it possible to theoretically increase the latch-up resistance by one order of magnitude compared to the conventional technology.

After forming the second epitaxial layer [4b], the p-type collector electrode ? , n-type collector electrode section 8. p-type well diffusion layer9. N-type well diffusion layer 10
is formed by ion implantation. The n-type well diffusion layer IO is an n-well region of a P-MOS transistor, a vertical NPN
Used as a field channel stopper for transistors and as a base tilting wall for lateral PNP transistors. In the case of vertical NPN transistors, ensure that the field MOS ■, 1 is 15V or more, and have a sufficiently high C.
In order to ensure di-breakdown breakdown voltage between B, it is formed at a distance of 2 to 5 μm from the base region and with a width of 2 to 4 pm. In addition, in lateral PNP transistors, the base width is 2 to 4 μm.
In order to ensure a CE breakdown voltage of 15 V or more and an early voltage of 50 M or more, the n-type well diffusion layer 10 is required.

Further, the P-type well diffusion layer 9 is used together with a channel stopper layer 11 and a p-type buried layer 6, which will be described later, as a P-well region of a -N-MOS transistor and an isolating region under the surrounding oxidation layer.

The above p-type collector electrode? , n-type collector electrode section 8, p-type well diffusion layer 9. The conditions for ion implantation into the n-type well diffusion layer 10, together with the following stretching process, must satisfy the following requirements from the device side. That is, ■ the p-type collector electrode 7, the n-type well diffusion layer 10 and the p-type collector electrode 7, the n-type well diffusion layer 10 and the
The diffusion layer MXJ of the type well diffusion layer 9 is 1/2 the thickness of the second epitaxial layer 4b, and the diffusion depth XJ of the n-type collector electrode portion 8 is equal to or greater than the thickness of the second epitaxial layer. It is necessary that the surface concentration of the nn-type well diffusion layer 10 and the p-type well diffusion layer 90 be 3 to 10"cm-'. This value is equal to the collector resistance of the vertical PNP transistor. , the source-drain breakdown voltage of N-MOS and P-MOS transistors, the isolation breakdown voltage of vertical NPN transistors and vertical PNP transistors, and the CE breakdown voltage of lateral PNP transistors.

For example, the surface concentration of the P-type well diffusion 719 that forms the P-well region of an N-MOS transistor is set to 3 to 7Xl.
O"cm-", and x of this diffusion layer is 1.0 to 1.
．． By setting the thickness in the range of 58 m and setting the thickness of the second epitaxial layer 4b in the range of 1.5 to 3.5 μm,
Contact with the buried layer 6 is made in the range of 5×10'' to 2×10 15 cs-'.

Next, as shown in FIG. 5, sufficient heat treatment is performed to stretch and diffuse the well region. Next, boron ions are implanted into the isolating region to form the channel stopper layer 11.
form. The channel stopper layer 11 is also used to prevent channel leakage of the base-n''' raised portion of the vertical PNP transistor and the N-MOS transistor.

Next, as shown in FIG. 6, selective oxidation is performed using a conventional 5t3N4 film as a mask, leaving the active layer and the electrode lead-out portions. Next, the p-type diffusion layer 12 is formed into a vertical type N
Next, an n-type diffusion layer 13 is formed in the base region of the vertical PNP transistor by ion implantation. These two types of diffusion layers 12 and 13 are formed by independent ion implantation with different energies and doses in order to facilitate control of the current amplification factor h□ of the bipolar transistor and to improve performance.

What is particularly important here is that the base region of the vertical PNP transistor is formed of the n-type diffusion layer 13 and the low concentration second epitaxial layer 4b, as shown in the impurity profile in Figure 9. .

As described above, the base region made of the second epitaxial layer 4b is 1B
Keep the concentration below 16cm-' and BVo.

It is necessary to improve the withstand voltage and early voltage.

Next, as shown in FIG. 7, a thin gate oxide film 14 of 200 to 300 layers is formed on the entire surface, and immediately thereafter, low pressure CVD is applied.
Then, P or As is diffused into the polycrystalline silicon, and a gate electrode 15 is formed using ordinary photolithography. Note that the thickness of the polysilicon gate bridge is preferably 400 to 500 nm, and ρ is preferably 30 to 50 Ω/□ or less.

Next, in order to reduce the number of masks and the number of steps, vertical PN
P Transistor emitter 16 and collector raised electrode 1? , external base of vertical NPN transistor 18.
Emitter 19 and external collector 20, 21 . of the lateral PNP transistor. P-MOS transistor source
A shallow p diffusion layer is provided which also serves as the drain part 22 and the substrate lifting electrode, and the emitter 23 and collector lifting electrode 24 of the vertical NPN transistor are provided. External base 25 and N terminal pull-up electrode 26 of the vertical PNP transistor. External base electrode 27 of lateral PNP transistor. A shallow n° diffusion layer is also provided which also serves as the source/drain portion 28 of the N-MOS transistor.

A shallow p0 diffusion layer is created using BFL with a concentration of 30 to 50
The shallow n° diffusion layer is formed by ion implantation at keV, 3 to 10 × 1015 CI-2, using A1.
00~180keV, 3~l0×1015cm-
The oxide film (
(usually using BPSG or PSG), and then a contact hole is formed by normal photolithography. Next, an electrode is formed using A1 containing ^l or SL, which is a Ti material, preferably AI containing 1% St, by a sputtering method or a vacuum evaporation method, and then a pattern is formed to form the book shown in FIG. A bipolar CMOS semiconductor device according to the invention is obtained.

In the bipolar CMOS semiconductor device formed in this way, the vertical PNP transistor has a highly doped p-type buried layer 5 in a shallow epitaxial layer grown in at least two steps with optimized thickness and concentration. an n-type diffused layer 13 having a p-type collector layer and whose concentration is controlled by ion implantation silane; and a low-concentration second epitaxial layer 4b which is depleted during operation to ensure early voltage and breakdown voltage. and a p-type collector electrode portion which is diffused around the base region to reach the collector buried layer 5 for the purpose of isolating the element and pulling up the p-type collector buried layer 5. Furthermore, an n-type diffusion layer 8 for isolation is provided around the n-type diffusion layer 8 which is diffused and formed so as to reach the n-type buried layer 3.

In addition, in vertical NPN transistors, two n-type epitaxial layers are used to achieve sufficient collector-emitter breakdown voltage and low collector-base capacitance. Since the well layer 10 is arranged, good element isolation is achieved. In addition, since the lateral N-MOS transistor and the P-MOS transistor are respectively configured in a p-type buried layer, an n-type buried layer, and a p-type well layer and an n-type well layer formed thereon, Optimal characteristics can be obtained regardless of the thickness and concentration of the two epitaxial layers.

As described above, although the manufacturing method according to the present invention can produce a wide variety of components with high performance, the individual steps are extremely simple, mainly consisting of photolithography and ion implantation. This is an archaic method and is very effective in reducing costs.

In the vertical NPN transistor manufactured by the above manufacturing method, as a condition for forming an emitter base diffusion layer, a polysilicon emitter, which has various problems at the interface, is not used, and in order to compensate for this, the energy during emitter ion implantation is The electrode heat resistance is improved by increasing the voltage to 180 keV and securing the emitter xj of 0.2 pm or more. Also, the energy used in ion implantation to form the base is different from that of ordinary shallow NPN transistors, and a relatively high energy of 40 to 70 keV is used.

Further, in a vertical PNP transistor, as a condition for forming an emitter base diffusion layer, boron is formed in the form of BP at 30 to 50 keV to make the emitter shallow to achieve .chi.j-0.3 .mu.m.

In addition, the ion implantation conditions for base formation were adjusted to 100 to 200 keV to make the base shallower.
Ions are implanted at high energy.

In addition, in lateral PNP transistors, to form a layer with as high a concentration as possible in order to improve the injection effect into the emitter, a P diffusion layer, which forms the source and drain layers of a P-MOS transistor, is used, and in the collector region. In order to increase carrier capture efficiency, a p-type diffusion layer is used to form the base region of the vertical NPN transistor.

The isolation four is composed of a three-layer stack of a low concentration P buried layer 6, a P well diffusion layer 9, and a channel stopper layer 11, and a high concentration P buried layer is used in the substrate lifting part. .

Figure 9 shows an impurity profile showing the impurity concentration distribution in the depth direction of each constituent element configured as described above, where ^ is a vertical PNP transistor, and ■) is a vertical NPN transistor.
Transistor, (the mouth is a horizontal N-MOS transistor,
(D) is an impurity profile of a lateral P-MOS transistor, and the symbols indicate the concentrations in the portions indicated by the same symbols in FIG.

Next, the device performance achieved in each component of the bipolar CMO8 semiconductor device obtained as described above will be shown below.

(1) In the *-type PNP transistor, a device complementary to the vertical NPN transistor was obtained, which has unprecedented high speed, high gain, and high early voltage. That is, gain bandwidth 2 maximum 1.0 to 1.5 GHz (particularly 0.8 GHz or more at low current 0.1 mA) Current gain: 50 to 100 Early voltage: 30 ■ or more C8 breakdown voltage: 15 V or more (2) Vertical NPN In the transistor, a device with a small element size and sufficient gain bandwidth necessary for analog circuits including the video band was obtained.

Gain bandwidth 2 Maximum 3.0 to 5.0 GHz (especially 1.5 GHz or more at low current 0.1 mA) Current gain: 100 to 200 Early voltage: 50 V or more C8 breakdown voltage: 15 V or more (3) In lateral PNP transistors , a device with a low gain bandwidth due to holes accumulated in the epitaxial region is obtained. This allows the circuit to be used for special purposes such as delay circuits.

Also, by simply changing the base width layout, C
8-hour withstand voltage can be increased.

Gain bandwidth: 20-50M Current gain: 50-100 Early voltage: 30cm or more C8 breakdown voltage: 15V or more (4) In the N-MOS transistor, characteristics suitable for an interface circuit with a microprocessor were obtained. .

Saturation phase pressure conductance: 50 to 65 s/m SD breakdown voltage: 12 V or more (5) In the P-MOS transistor, the above N
- Sufficient characteristics were obtained to form a complementary circuit with MOS transistors.

Mutual conductance at saturation: 20 to 35 s/m SD withstand voltage = 12 V or more, characteristics of each component are bipolar CMOS that performs analog data processing centered on video signal processing.
It is the most suitable for the circuit. Particularly high gain bandwidth, current gain, knee current, and early voltage can be obtained with vertical PNP transistors, making them ideal for differential amplifiers and ECL circuits using PNP transistors, as well as complementary Circuit configuration becomes possible.

In the embodiment shown in Fig. 1 above, in order to increase the device breakdown voltage and reduce the parasitic capacitance of the device, the high concentration diffusion layer was not brought into contact with the other, but the purpose of the embodiment is to have a low breakdown voltage and high integration. In this case, it is also possible to make the n9 buried layer 3 and the p buried layer 6 in contact with each other. In this case, due to problems with alignment accuracy, the element size is reduced by about 2 to 4 μm. Further, in this case, it is more effective to arrange the n-well diffusion layer 10 in the vertical NPN transistor over the entire active layer. However, CB breakdown voltage, CB breakdown voltage, and C8 breakdown voltage all decrease to 1/2, and CT C+ Ct m is 2.
~5 times increase.

Furthermore, although the embodiment shown in FIG. 1 shows an example in which only active elements are formed as constituent elements, the bipolar CMOS semiconductor device according to the present invention has a resistor, a MOS capacitor, and a diffused junction capacitor integrated at the same time. It is also possible to form For resistors, use n-type diffused resistors, P-type diffused resistors, and polysilicon resistors.

Six types of resistors, an n-type pinch resistor and a p-type pinch resistor, can be obtained, and a resistor can also be formed by adding another diffusion layer.

FIG. 1O shows a p-type diffused resistance. It is the diffusion layer 12 that determines the resistance value, and is the same as the diffusion layer for forming the base of the vertical NPN transistor. The resistance value due to this diffusion layer is 0.5 to 1. OKΩ/□. If other sheet resistances are required or more precise control is required, separate diffused resistors can be created using conventional photolithography and diffused layers. Note that the electrode portion of the diffused resistor shown in FIG. 10 utilizes a high concentration p diffusion layer 18 in order to reduce contact resistance.

FIG. 11 similarly shows a pinch high resistance using a tilted base of a vertical NPN transistor, and 31 is an n9 diffusion layer. FIG. 12 shows an n-type diffused resistor using an n-diffusion layer 13 forming the base region of a vertical PNP transistor. FIG. 14 shows a MOS resistor composed of polysilicon 34 for a gate electrode, which is automatically formed when creating a MOS transistor.
Indicates capacity. Further, in the semiconductor device shown in FIG. 1, the high 4 degree p'' buried layer 5 can also be used to form a p-type resistor that allows a high current to flow.

Further, in the embodiment shown in FIG. 1, in order to reduce the number of masks during manufacturing, the emitter diffusion layer of the bipolar transistor is formed of the same diffusion layer as the source and drain of the MOS transistor. However, what is the limit on the current amplification factor hrt of bipolar transistors? In order to make the base region shallower, it is necessary to form a diffusion layer separate from that of the MOS transistor, or to form an opening in the emitter region's passive region, t g 7 CV DIl [(usually BPSG or PSG). After forming the part first, then forming the n1 diffusion layer in the emitter part in a self-aligned manner,
Alternatively, it is also possible to use polysilicon as an electrode and obtain a shallow junction by solid-phase diffusion from within the polysilicon.

Regarding the electrode structure, simple AI or A containing Si
Although the one using the I electrode is shown, in consideration of improving the heat resistance of the electrode and especially reducing the emitter resistance, ptst and Tl electrodes are used.
Silicidation with high melting point metal such as 5T, and TIN,
It is also possible to use a barrier metal made of a high melting point metal or alloy such as TiV/W.

As described above, according to the present invention, a Zebipolar CMOS semiconductor device is constructed by combining high-performance vertical PNP transistors that have a gain bandwidth of IGHz or more and are complementary to vertical NPN transistors.
When you want to process signals from diodes, PN diodes, or even one-dimensional or two-dimensional photo array sensors, the output signals may be low and close to the GND level, but this can be differentially amplified using a vertical PNP transistor. Therefore, it is possible to perform high-speed, high-gain, and highly accurate control using a single power supply. Therefore, according to the semiconductor device of the present invention, a sensor interface, a microprocessor interface, etc. can be integrated into an IC that processes signals using conventional vertical transistors, regardless of whether it is for consumer use or industrial use. Not only can it bring out great capabilities, but it also makes it possible to create ICs with unprecedented speed and precision.

〔Effect of the invention〕

As described above based on the embodiments, according to the present invention, a high-speed, high-performance vertical PNP transistor with high CE breakdown voltage, high early voltage, and large gain bandwidth can be obtained.
It is possible to provide a bipolar CMOS semiconductor device that integrally includes a vertical NPN transistor, a vertical PNP transistor that can be used complementary thereto, a horizontal PNP transistor, and a CMOS transistor. Further, according to the manufacturing method of the present invention, it is possible to provide a method for manufacturing a bipolar CMOS semiconductor device that can easily improve the performance of each component.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing an embodiment of a bipolar CMOS semiconductor device according to the present invention, and FIGS. 2 to 7 are views showing the manufacturing process of the semiconductor device shown in FIG. 1, and FIG. is the vertical NPN with respect to the thickness of the second epitaxial layer.
CE of transistor and vertical PNP transistor,
A diagram showing the relationship between the breakdown voltage and the punch-through breakdown voltage of the B-N@ child of a vertical PNP transistor (see Figure 9) is the first diagram.
A diagram showing the impurity profile of each component of the semiconductor device shown in the figure, Figure 1θ is a diagram showing the p-type diffused resistance,
Figure 1 is a diagram showing a vinyl type diffused resistor, Figure 12 is a diagram showing n
FIG. 13 is a diagram showing a type diffusion resistance, FIG. 13 is a diagram showing a polysilicon resistance, and FIG. 14 is a diagram showing a MOS capacitance. In the figure, 1 is a substrate, 2 is an oxide film, 3 is an n-type buried layer,
4a is a first epitaxial layer, 4b is a second epitaxial layer, 5 is a high concentration p-type buried layer, 6 is a low concentration p-type buried layer,
7 is a p-type collector electrode part, 8 is an n-type collector electrode part, 9
is a p-type well layer, IO is an n-type well layer, 11 is a p-type channel stopper layer, 12 is a p-type diffusion layer, 13 is an n-type diffusion layer, 14 is a gate oxide film, 15 is a gate electrode, 16 is a vertical type The emitter of the PNP transistor, 17 is the n-type collector pull-up electrode, 18 is the external base of the vertical NPN transistor, 19 is the emitter of the horizontal PNP transistor,
20. 21 is its collector, 22 is the source/drain part of the P-MOS transistor, 23 is the emitter of the vertical NPN transistor, 24 is the collector raising electrode, 25
26 shows the external base of the vertical PNP transistor, 26 shows the N terminal pull-up electrode, 27 shows the external base of the horizontal PNP transistor, and 28 shows the source/drain terminal of the N-MOS transistor. Patent applicant O. Rimbus Optical Industry Co., Ltd. Figure 6 Figure 7 Figure 8 Thickness of second epitaxial layer → Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14

Claims (1)

Claims: 1. A plurality of epitaxially grown layers on a single monolithic semiconductor substrate having a low doping level of a different type than the epitaxially grown layers grown in at least two separate stages with a low doping level. A semiconductor device configured as a circuit component includes at least a buried p-type collector layer having a high doping level, a base region consisting of a second epitaxial layer and an n-type diffusion layer diffused into the epitaxial layer. A bipolar CMOS semiconductor device comprising a vertical PNP transistor, a vertical NPN transistor, a horizontal PNP transistor, a horizontal N-MOS transistor, and a horizontal P-MOS transistor. 2. The low doping level semiconductor substrate is boron-doped p^ with a resistivity of 2-20 Ωcm.
- It is composed of a single crystal silicon wafer, and the epitaxial growth layer is 0.5 to 3 x 10^1^6 cm^
-^3 P or Sb doped thickness 1.0~2.0μ
m n-type first epitaxial layer, and 2 to 10×10^1
^5cm^-^3 P or Sb doped thickness 1.5
The collector buried layer of the vertical PNP transistor is formed by doping boron at a high concentration between the first epitaxial layer and the second epitaxial layer. and an inter-element isolation region formed by doping boron at a low concentration in the same or different ion implantation process as the collector buried layer and a well lead-out electrode part of the N-MOS transistor. The bipolar CMOS semiconductor device according to claim 1. 3. An n-type buried layer doped with Sb formed between the substrate and the first epitaxial layer, and an n-type buried layer doped with Sb formed by diffusing phosphorus from the surface of the second epitaxial layer so as to be in contact with the n-type buried layer. PN vertical PNP transistor with type diffusion layer
Vertical PNP from vertical and horizontal directions by surrounding with a bond
1. A vertical PNP transistor section electrically separating a collector region and a substrate region of the transistor and forming an electrode extraction section for setting a potential of the n-type buried layer. or bipolar CM described in 2.
OS semiconductor device. 4. The Sb-doped n-type buried layer formed between the substrate and the first epitaxial layer is used as a collector region, and the n-type diffusion region is formed by diffusion from the second epitaxial layer at a distance of 2 to 5 μm from the base active region. Claims 1 to 3 characterized in that the transistor comprises a vertical NPN transistor having a region that secures a punch-through withstand voltage between the base and the substrate and a sufficient base-collector withstand voltage and prevents channel leakage.
The bipolar CMOS semiconductor device according to any one of the above. 5. The first epitaxial layer and the second epitaxial layer are spatially shifted in the vertical direction with respect to the highly doped n-type buried layer formed between the substrate and the first epitaxial layer directly under the P-MOS transistor. A p-type buried layer with a relatively low concentration formed between
It has a p-well region controlled at ^-^3, and is equipped with an N-MOS transistor that reduces the resistivity under the well and improves latch-up resistance while maintaining the interwell breakdown voltage at 15V or higher. The bipolar CMOS semiconductor device according to any one of claims 1 to 4. 6. at least a vertical NPN transistor on a single monolithic semiconductor substrate having a low doping level of a different type than the epitaxially grown layer grown in at least two separate growths with a low doping level; In the method for manufacturing a bipolar CMOS semiconductor device including a vertical PNP transistor, a lateral PNP transistor, a lateral N-MOS transistor, and a lateral P-MOS transistor, Sb is provided between the substrate and the first epitaxial layer. A step of doping to form a heavily doped diffusion layer, a step of doping boron between the first and second epitaxial layers to form a p-type collector buried layer, and a second epitaxial layer surrounding the base activation region. forming a p-type collector diffusion layer by doping boron at a higher concentration than the well diffusion layer of the N-MOS transistor from the upper part of the layer, and forming the p-type collector buried layer and the p-type collector diffusion layer by heat treatment. By stretching and making contact, and by setting the sheet resistance of the collector buried layer to 500 to 1500 Ω/□, the collector series resistance was lowered to 200 Ω or less, and a vertical PNP transistor with small parasitic effects was obtained. A method for manufacturing a bipolar CMOS semiconductor device. 7. The emitter and collector raised electrode regions of the vertical PNP transistor, the external base region of the vertical NPN transistor, the source/drain region of the P-MOS transistor, and the emitter/collector region of the lateral PNP transistor as necessary, with the total charge amount 3~20×10^1^5c
The collector region of the vertical NPN transistor, the external base region of the vertical PNP transistor, and the source/drain region of the N-MOS transistor are simultaneously formed with a p-type high concentration diffusion layer of m^-^2, and the total charge amount is 5~15×1
7. The method of manufacturing a bipolar CMOS semiconductor device according to claim 6, wherein an As-doped n-type high concentration diffusion layer of 0^1^5 cm^-^2 is formed at the same time. 8. The concentration of the base region of the vertical PNP transistor is set to 1×10^1^6c so that it becomes a depletion layer when in use.
An n-type second epitaxial layer controlled to be less than m^-^3, and an energy of 100 to 2 on the surface of the second epitaxial layer.
00keV, dose amount 3-10×10^1^3cm^-
It is formed with a shallow base diffusion layer formed by ^2 independent ion implantation process, and has an early voltage of 30V or more.
Vertical type P with collector-emitter breakdown voltage of 15V or more
8. The method of manufacturing a bipolar CMOS semiconductor device according to claim 6, wherein an NP transistor is obtained. 9. Vertical NPN formed by diffusion from the second epitaxial layer
Isolation region between base and substrate of transistor, horizontal PNP
The base region of the transistor and the n-well region of the P-MOS transistor are coated with a surface concentration of 2 to 5 x 10^1^6 cm.
^-^2 are simultaneously formed with n-type diffusion layers to improve the collector-emitter breakdown voltage of the lateral PNP transistor and the source-drain breakdown voltage of the P-MOS transistor. A method for manufacturing a bipolar CMOS semiconductor device according to any one of the above.