JPS59149045A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce base resistance by isolating base regions of a plurality of reverse operation vertical type transistors by an insulator and reducing base ineffective areas while the base regions are connected mutually by an extracting electrode consisting of a metallic silicide layer formed in a self-alignment manner. CONSTITUTION:Inverter transistors T1, T2 are isolated by an oxide 41, and an injector transistor T4 is also isolated and made independent. A common base connects the bases 34 of each incerter transistor and a coolsector 36 of an injector by an extracting electrode 34' consisting of polycrystalline silicon remaining through selective oxidation and platinum silicide 34'' formed in a self- alignment manner. Since the extracting electrode has platinum silicide, its resistance can be brought to a very low value, and base series resistance can be reduced. Consequently, a base lateral voltage drop is not generated even by the increase of the number of collectors, and uniform current gains are obtained, thus remarkably improving the speed of switching. Since sections except intrinsic transistor regions are also isolated by oxides in each inverter transistor, parastic capacitance is small, and the ratio of a collector area to a base area is large, thus also improving current gains.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor devices, particularly I"L (Integra
tedInjection Logic).

I"L has a composite structure of an inverter transistor, which is a so-called inverted vertical transistor in which the emitter and collector of a normal bivorous 2 transistor are reversed, and a complementary injector transistor, whose collector is the base of this transistor. I'm doing it again.
L has a small logic amplitude, can operate at high speed and with low power consumption, and because it does not require element isolation, it can be highly integrated, and can coexist on the same chip with conventional Bibo 2 integrated circuits. have.

As shown in Fig. 1(a) and (b), the conventional IL consists of two NPN transistors 'I', , T as an inverter.
The common base electrode 4 of L, T, is input, and a lateral PNP transistor for carrier injection is integrated.

FIG. 2 shows the circuit of I2L, and as the transistor becomes farther away from the base electrode 4, the base resistance r8. It has r, , rs.

For this reason, a base lateral voltage drop occurs during large currents, and the difference in distance from the base contact causes the transistor (
A difference occurs in the current gain of the inverter). Another drawback is that the base resistance slows down the switching time. Furthermore, the effective transistor area 112,3
On the other hand, the invalid base area 5 is large and reduces the current gain of the reverse operation NPN.

The purpose of the present invention is to solve the drawbacks of I2L of conventional structure and (
The object of the present invention is to provide a structure in which the collector area/base area ratio can be increased and the base resistance can be reduced. In order to achieve such an object, the present invention separates the base regions of a plurality of reverse-acting vertical transistors with an insulator, and
In addition to reducing the base effective area, the base resistance is significantly reduced by interconnecting the base regions with extraction electrodes made of metal silicide layers formed in a self-aligned manner.

Hereinafter, the present invention will be described in detail based on Examples.

FIGS. 3(a) and 3(b) are a plan view and a sectional view, respectively, showing an embodiment in which the present invention is applied to a case where there are two inverter transistors.

In both figures, 37 is the emitter of the injector horizontal PNP transistor, 37' is the P+ type polycrystalline silicon for the extraction electrode, 37'' is platinum silicide on the polycrystalline silicon, 36 is the collector of the injector horizontal PNP transistor, and 34' is the common base. P+ type polycrystalline silicon for input,
34' is platinum silicide on polycrystalline silicon, 35.3
4 is an inverter NPN transistor P type base; 31.
32 is an N+ type collector of an inverter NPN transistor, 32' and 31' are polycrystalline silicon for extracting the collector electrode, and 31N.

32'' is platinum silicide on polycrystalline silicon, 32 is a common N1 emitter, 33', 33' are polycrystalline silicon and platinum silicide for common emitter extraction electrodes, 41 is a field oxide film, 39 is an N-type epitaxial layer, 40 As can be seen from the diagram, inverter transistors T1.
T, is separated by an oxide 41, and the injector transistor T4 is also separated and independent. Furthermore, the common base is connected to the base of each inverter transistor and the collector 36f of the injector by an extraction electrode made of platinum silicide formed in self-alignment with the polycrystalline silicon remaining after selective oxidation. Since this extraction electrode contains platinum silicide, it can have a very low resistance (>5Ω), and the base series resistance can be made very small. Additionally, as a result, even with an increase in the number of collectors, no base lateral voltage drop occurs and a uniform current gain can be obtained. The switching speed is therefore also significantly improved.

In addition, since each inverter transistor is separated by oxide except for the intrinsic transistor region, parasitic capacitance is small and (
Since the collector area/(base area) ratio is large, the current gain is also improved. Next, the manufacturing method of the above example was applied to a fourth method.
This will be explained with reference to Figures (81 to (d)).

First, a P-type silicon substrate 30 with a specific resistance of 0.5 to 50Ωα
0 surface with a high concentration of antimony, for example, N+ type embedding 6
4 (1' Diffusion formation. Next, on this substrate, a thickness of 3 to 1
An N-type epitaxial layer 39 with a resistivity of 0 μm and a resistivity of 0.5 to 5 Ω is grown (FIG. 4(a)).

Next, by chemical vapor deposition, a silicon nitride film (1000 to 1500 A) was placed on top of the 500 A thin oxide film.
sN4) and buttering by plasma etching. The nitride film is removed leaving the transistor region 5-3, and if necessary, the silicon is partially etched, and using this nitride film 43 as a mask, a 1000-mm film is etched.
A field oxide film 41 with a thickness of 1.0 to 1.5 μm is formed by thermal oxidation at ~1100″C. To form the base region 35.34 of the NPN transistor, the acceleration energy IQQkevs injection amount is 1 to 5× 1014cIrL-
In step 2, boron ions are implanted into the photoresist mask (FIG. 4(b)).

Edge from which the nitride film and thin oxide film were removed, approximately 500 OA
A polysilicon film 44 having a thickness of 100 nm is formed by chemical vapor deposition. Then, the polysilicon surface was coated with a thickness of 500A.
A thermal oxide film is formed, and a nitride film 45 is grown to a thickness of 150 OA by chemical vapor deposition (FIG. 4(C)).

Next, the nitride film is patterned, and by selective oxidation using this as a mask, polysilicon 'IkJIJ 1.0 to 1
．． It is separated by an oxide film 42 with a thickness of 5 μm. Next, the nitride film and thin oxide film on the polysilicon in the regions where the external base regions 35 and 34 and the emitters 37 and collectors 36 of the lateral PNP are to be formed are selectively removed, and then boron is heated at 900°C to 1100°C. is diffused through the polysilicon to form a region approximately 0.6 μm deep in the single crystal silicon, and the polysilicon surface is oxidized.

Next, the nitride film and thin oxide film in the areas where the I2L collectors 31, 32 and emitters 33 are to be formed are removed, and the temperature is heated to 900°C.
Diffusion of phosphorus through polysilicon at ~1050°C;
Emitters and collectors with a depth of approximately 0.4 μm are formed in single crystal silicon.

Next, selectively remove the oxide film and nitride film in the area that will become the electrode,
Platinum is deposited on the entire surface to form platinum silicide 31", 32',
33", 34", and 37" are formed in a self-aligned manner, and the polysilicon lead electrode has a low resistance of 5 Ω/hole or less (FIG. 4(d)).

Next, another embodiment of the present invention will be described with reference to FIG.

This example uses a high-resistance 38" tl- of polycrystalline silicon with impurity ions implanted into a horizontal PNP wire as a current source.
It was formed. ``Since the polycrystalline silicon resistor can be formed on an oxide film, there is no parasitic capacitance, and the switching speed can be further increased. Furthermore, since platinum silicide on polycrystalline silicon is formed only on polycrystalline silicon that is not selectively oxidized, platinum on the oxide film is removed in a self-aligned manner with an etching solution such as aqua regia. Therefore, no alignment is required between the pace diffusion region and the extraction electrode.

As explained above, according to the present invention, the I2L inverters are independently separated by an insulator such as an oxide, and the common space of each transistor is connected by an extraction electrode made of a metal silicide layer self-aligned with polycrystalline silicon. By doing so, the pace series resistance can be reduced and the switching speed can be increased.

[Brief explanation of drawings]

Figures 1 (a) and (b) are a plan view and a sectional view of a conventional I"L, respectively, Figure 2 is its equivalent circuit diagram, and Figure 3 (a)
and (b) are respectively a plan view and a sectional view of one embodiment of the present invention, FIGS. 4(a) to (d) are sectional views showing the manufacturing method of the embodiment, and FIG. 5 is a plan view and a sectional view of an embodiment of the present invention. It is a sectional view showing an example. 1.2.3...Collector, 4...Base contact, 5...Common pace area, 6...
...Injector" t+T11T1...
Inverter transistor, T4...Injector transistor, rl, r2. ra... Base series resistance, 30... P-type silicon substrate, 31.
32... Collector, 31', 32' and 31'
, 32'...Polycrystalline silicon and platinum silicide for collector extraction electrode, 33...Common emitter, 33' and 33''...Polycrystalline silicon for emitter extraction electrode and platinum silicide, 34.
35...Invar 2 base, 34' and 34'・
... Polycrystalline silicon and platinum silicide for pace extraction electrode, 36 ... Injector PNP collector, 37 ... Injector PNP emitter, 3
7' and 37''... Polycrystalline silicon and platinum silicide for injector emitter extraction electrode, 38
...Ion-implanted polycrystalline silicon resistor, 39...
...N type epitaxial layer, 40...N+
Shaped buried layer, 41...field 9- Oxide film, 42...polycrystalline silicon oxide film, 4
3゜45...Silicon emptying membrane, 44...
- Polycrystalline silicon (polysilicon). 10- Figure 1 (Shen) Figure 3 (ω) Figure 4 (Figure 4 (b) Figure 4 (C) Figure 4 rd,) Figure 5

Claims (1)

[Claims] Base regions of a plurality of reverse-operating vertical transistors are formed on the surface of a semiconductor substrate, and the base regions are formed of a polycrystalline silicon layer and a metal silicide formed in a self-aligned manner on the surface of the polycrystalline silicon layer. A semiconductor device characterized in that the semiconductor device is interconnected by extraction electrodes made up of layers.