JPH0425711B2 - - Google Patents
Info
- Publication number
- JPH0425711B2 JPH0425711B2 JP58023960A JP2396083A JPH0425711B2 JP H0425711 B2 JPH0425711 B2 JP H0425711B2 JP 58023960 A JP58023960 A JP 58023960A JP 2396083 A JP2396083 A JP 2396083A JP H0425711 B2 JPH0425711 B2 JP H0425711B2
- Authority
- JP
- Japan
- Prior art keywords
- polycrystalline silicon
- base
- transistor
- forming
- separated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 36
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- 229910021332 silicide Inorganic materials 0.000 claims description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 3
- 238000000034 method Methods 0.000 claims 2
- 238000000151 deposition Methods 0.000 claims 1
- 230000001590 oxidative effect Effects 0.000 claims 1
- ZXEYZECDXFPJRJ-UHFFFAOYSA-N $l^{3}-silane;platinum Chemical compound [SiH3].[Pt] ZXEYZECDXFPJRJ-UHFFFAOYSA-N 0.000 description 12
- 229910021339 platinum silicide Inorganic materials 0.000 description 12
- 238000000605 extraction Methods 0.000 description 11
- 229920005591 polysilicon Polymers 0.000 description 9
- 150000004767 nitrides Chemical class 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- QZPSXPBJTPJTSZ-UHFFFAOYSA-N aqua regia Chemical compound Cl.O[N+]([O-])=O QZPSXPBJTPJTSZ-UHFFFAOYSA-N 0.000 description 1
- -1 boron ions Chemical class 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
- H01L27/0229—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of bipolar structures
- H01L27/0233—Integrated injection logic structures [I2L]
Description
【発明の詳細な説明】
本発明は半導体装置、特にI2L（Integrated
Injection Logic）に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor devices, particularly I 2 L (Integrated
Injection Logic).
I2Lは通常のバイポーラトランジスタのエミツ
タとコレクタを逆にしたいわゆる逆構造バーチカ
ルトランジスタからなるインバータ用トランジス
タと、このトランジスタのベースをコレクタとす
るこれと相補形のインジエクタ用トランジスタの
複合構造を有している。またI2Lは論理振幅が、
小さく、高速かつ、低消費電力の動作が可能であ
り、素子分離を要しないため高集積化が可能で、
従来のバイポーラ集積回路と同一チツプ上に共存
できるという特徴を有している。 I 2 L has a composite structure of an inverter transistor, which is a so-called inverted vertical transistor in which the emitter and collector of a normal bipolar transistor are reversed, and a complementary injector transistor, whose collector is the base of this transistor. ing. Also, I 2 L has a logic amplitude of
It is small, high-speed, and can operate with low power consumption, and because it does not require element isolation, it can be highly integrated.
It has the feature that it can coexist on the same chip with conventional bipolar integrated circuits.
従来I2Lは第１図ａ，ｂに示すように、インバ
ータとしてのNPNトランジスタT1，T2，T3の
共通ベース電極４が入力となり、キヤリヤ注入用
横方向PNPトランジスタが一体化されている。 Conventional I 2 L, as shown in Fig. 1a and b, has a common base electrode 4 of NPN transistors T 1 , T 2 , T 3 as an inverter as an input, and a lateral PNP transistor for carrier injection is integrated. There is.
第２図は前記I2Lの等価回路を示すものである
が、ベース電極４からトランジスタが遠くなるに
つれて大きなベース抵抗γ1，γ2，γ3を有してい
る。 FIG. 2 shows an equivalent circuit of the above-mentioned I 2 L, and as the transistor becomes farther from the base electrode 4, the base resistances γ 1 , γ 2 , and γ 3 become larger.
このため、大電流時にベース横方向電圧降下を
生じ、ベースコンタクトからの距離の差によつて
トランジスタ（インバータ）の電流利得に差が生
じる。また、このベース抵抗のためスイツチング
時間が遅くなるという欠点があつた。さらに、実
効的なトランジスタ領域１，２，３に対し無効ベ
ース面積５が大きく逆動作NPNの電流利得を低
下させている。 Therefore, a voltage drop occurs in the lateral direction of the base at the time of a large current, and the current gain of the transistor (inverter) varies depending on the distance from the base contact. Another drawback is that the base resistance slows down the switching time. Furthermore, the invalid base area 5 is large compared to the effective transistor areas 1, 2, and 3, reducing the current gain of the reverse operation NPN.
本発明の目的は、従来構造のI2Lの欠点を解決
し、（コレクタ面積）／（ベース面積）比を大き
くでき、かつベース抵抗を小さくした構造を提供
することにある。かかる目的を達成するために、
本発明では、複数個の逆動作縦形トランジスタの
ベース領域を絶縁物で分離して、ベース無効面積
を減少させるとともに、前記ベース領域を自己整
合的に形成された金属シリサイド層からなる引き
出し電極で相互に接続することによりベース抵抗
を大幅に減少させるものである。 An object of the present invention is to solve the drawbacks of the conventional structure I 2 L, to provide a structure in which the (collector area)/(base area) ratio can be increased and the base resistance can be reduced. In order to achieve this purpose,
In the present invention, the base regions of a plurality of reverse-acting vertical transistors are separated by an insulator to reduce the base ineffective area, and the base regions are interconnected by an extraction electrode made of a metal silicide layer formed in a self-aligned manner. By connecting it to the base, the base resistance can be significantly reduced.
以下、実施例に基づき本発明を詳細に説明す
る。第３図ａ及びｂはそれぞれ本発明をインバー
タトランジスタが２個の場合に適用した一実施例
を示す平面図及び断面図である。 Hereinafter, the present invention will be explained in detail based on Examples. FIGS. 3a and 3b are a plan view and a sectional view, respectively, showing an embodiment in which the present invention is applied to a case where there are two inverter transistors.
両図において、３７はインジエクタ横形PNP
トランジスタのエミツタ、３７′は引き出し電極
要P+形多結晶シリコン、３７″は多結晶シリコン
上の白金シリサイド、３６はインジエクタ横形
PNPトランジスタのコレクタ、３４′は共通ベー
ス入力用P+形多結晶シリコン、３４″は多結晶シ
リコン上の白金シリサイド、３５，３４はインバ
ータNPNトランジスタＰ形ベース、３１，３２
はインバータNPNトランジスタのN+形コレク
タ、３２′，３１′はコレクタ電極引き出し用多結
晶シリコン、３１″，３２″は多結晶シリコン上の
白金シリサイド、３２は共通N+エミツタ、３
３′，３３″は共通エミツタ引き出し電極用多結晶
シリコン及び白金シリサイド、４１はフイールド
酸化膜、３９はＮ形エピタキシヤル層、４０は
N+形埋込層、３０はＰ形シリコン基板をそれぞ
れ示す。 In both figures, 37 is the injector horizontal PNP
Emitter of transistor, 37' is P + type polycrystalline silicon for extraction electrode, 37'' is platinum silicide on polycrystalline silicon, 36 is horizontal injector
Collector of PNP transistor, 34' is P + type polycrystalline silicon for common base input, 34'' is platinum silicide on polycrystalline silicon, 35, 34 is P type base of inverter NPN transistor, 31, 32
is the N + type collector of the inverter NPN transistor, 32' and 31' are polycrystalline silicon for extracting the collector electrode, 31'' and 32'' are platinum silicide on polycrystalline silicon, 32 is a common N + emitter, 3
3' and 33'' are polycrystalline silicon and platinum silicide for the common emitter extraction electrode, 41 is a field oxide film, 39 is an N-type epitaxial layer, and 40 is a
30 represents an N + type buried layer and a P type silicon substrate, respectively.
図からわかるように、インバータトランジスタ
T1，T2は酸化物４１で分離され、インジエクタ
トランジスタT4も分離独立している。さらに、
共通ベースは選択酸化により残つた多結晶シリコ
ンと自己整合的に形成された白金シリサイドから
なる引き出し電極によつて各インバータトランジ
スタのベース及びインジエクタのコレクタ３６を
接続している。この引き出し電極は白金シリサイ
ドを有するため、非常に抵抗抗（＞５Ω）にで
き、ベース直列抵抗を非常に小さくできる。ま
た、この結果、コレクタ数の増加によつても、ベ
ース横方向電圧降下は発生せず、均一な電流利得
が得られる。従つてスイツチング速度も著しく改
善される。 As you can see from the diagram, the inverter transistor
T 1 and T 2 are separated by an oxide 41, and the injector transistor T 4 is also separated and independent. moreover,
The common base connects the base of each inverter transistor and the collector 36 of the injector by an extraction electrode made of platinum silicide formed in self-alignment with the polycrystalline silicon left after selective oxidation. Since this extraction electrode contains platinum silicide, it can be made to have a very high resistance (>5Ω), and the base series resistance can be made very small. Furthermore, as a result, even with an increase in the number of collectors, no base lateral voltage drop occurs, and a uniform current gain can be obtained. The switching speed is therefore also significantly improved.
また各インバータトランジスタも真性トランジ
スタ領域以外は酸化物で分離されるため、寄生容
量が少なく、（コレクタ面積）／（ベース面積）
比が大きいので、電流利得も改善される。次に、
前記実施例の製造方法を第４図ａ〜ｄを参照して
説明する。 In addition, since each inverter transistor is separated by oxide except for the intrinsic transistor region, parasitic capacitance is small, and (collector area) / (base area)
Since the ratio is large, the current gain is also improved. next,
The manufacturing method of the above embodiment will be explained with reference to FIGS. 4a to 4d.
まず、比抵抗0.5〜50ΩcmのＰ形シリコン基板
３０の表面に例えばアンチモンを高濃度に含む
N+形埋込層４０を拡散形成する。次にこの基板
上に厚さ３〜10μｍ、比抵抗0.5〜50ΩcmのＮ形エ
ピタキシヤル層３９を成長させる（第４図ａ）。 First, the surface of a P-type silicon substrate 30 having a specific resistance of 0.5 to 50 Ωcm contains a high concentration of antimony, for example.
An N + type buried layer 40 is formed by diffusion. Next, an N-type epitaxial layer 39 having a thickness of 3 to 10 .mu.m and a resistivity of 0.5 to 50 .OMEGA.cm is grown on this substrate (FIG. 4a).
次に化学的気相成長法によつて、500Åの薄い
酸化膜の上に、1000〜1500Åのシリコン窒化膜
（Si3N4）を形成し、プラズマエツチングによつ
てパターニングする。トランジスタ領域を残して
前記窒化膜を除去し、必要であればシリコン部分
的にエツチングし、この窒化膜４３をマスクに
1000〜1100℃で熱酸化し、厚さ1.0〜1.5μｍのフ
イールド酸化膜４１を形成する。NPNトランジ
スタのベース領域３５，３４を形成するため、加
速エネルギー100kev、注入量１〜５×1014cm-2で
フオトレジストをマスクにボロンのイオン注入を
行う（第４図ｂ）。 Next, a 1000-1500 Å silicon nitride film (Si 3 N 4 ) is formed on the 500 Å thin oxide film by chemical vapor deposition, and patterned by plasma etching. The nitride film is removed leaving the transistor region, and if necessary, the silicon is partially etched, using this nitride film 43 as a mask.
Thermal oxidation is performed at 1000 to 1100° C. to form a field oxide film 41 with a thickness of 1.0 to 1.5 μm. In order to form the base regions 35 and 34 of the NPN transistors, boron ions are implanted using a photoresist as a mask at an acceleration energy of 100 keV and an implantation amount of 1 to 5.times.10.sup.14 cm.sup. -2 (FIG. 4b).
前記窒化膜及び薄い酸化膜を除去した後、約
5000Åの厚さのポリシリコン４４を化学的気相成
長法によつて形成する。ついで前記ポリシリコン
表面に厚さ500Åの熱酸化膜を形成し、窒化膜４
５を化学的気相成長法によつて1500Åの厚さに成
長する（第４図ｃ）。 After removing the nitride film and thin oxide film, approximately
Polysilicon 44 with a thickness of 5000 Å is formed by chemical vapor deposition. Next, a thermal oxide film with a thickness of 500 Å is formed on the polysilicon surface, and a nitride film 4 is formed.
5 was grown to a thickness of 1500 Å by chemical vapor deposition (FIG. 4c).
次に、窒化膜をパターニングし、これをマスク
にした選択酸化によつてポリシリコンを厚さ1.0
〜1.5μｍの酸化膜４２で分離する。ついで、外部
ベース領域３５，３４及びラテラルPNPのエミ
ツタ３７、コレクタ３６を形成すべき領域のポリ
シリコン上の窒化膜及び薄い酸化膜を選択除去し
て、900℃〜1100℃でボロンをポリシリコンを通
して拡散し、深さ約0.6μｍの上記領域を単結晶シ
リコン中に形成し、ポリシリコン表面を酸化す
る。 Next, the nitride film is patterned, and polysilicon is deposited to a thickness of 1.0 mm by selective oxidation using this as a mask.
It is separated by an oxide film 42 of ~1.5 μm. Next, the nitride film and thin oxide film on the polysilicon in the areas where the external base regions 35, 34 and the emitter 37 and collector 36 of the lateral PNP are to be formed are selectively removed, and boron is passed through the polysilicon at 900°C to 1100°C. Diffusion is performed to form the above region with a depth of about 0.6 μm in single crystal silicon, and the polysilicon surface is oxidized.
次にI2Lのコレクタ３１，３２エミツタ３３を
形成すべき領域の窒化膜及び薄い酸化膜を除去し
て900℃〜1050℃でリンをポリシリコンを通して
拡散し、深さ約0.41μｍのエミツタ及びコレクタ
を単結晶シリコン中に形成する。 Next, the nitride film and thin oxide film in the area where I 2 L collectors 31, 32 and emitters 33 are to be formed are removed, and phosphorus is diffused through the polysilicon at 900°C to 1050°C to form emitters with a depth of about 0.41 μm. A collector is formed in single crystal silicon.
次に電極となる領域の酸化膜及び窒化膜を選択
除去し、全面に白金を蒸着して白金シリサイド３
１″，３２″，３３″，３４″，３７″を自己整合的
に形成し、ポリシリコン引き出し電極を層抵抗５
Ω／口以下の低抵抗にする（第４図ｄ）。 Next, the oxide film and nitride film in the area that will become the electrode are selectively removed, and platinum is deposited on the entire surface to form platinum silicide 3.
1″, 32″, 33″, 34″, and 37″ are formed in a self-aligned manner, and polysilicon lead electrodes are formed with layer resistance 5.
The resistance should be low, less than Ω/mm (Fig. 4 d).
次に、本発明の他の実施例について第５図を参
照しと説明する。 Next, another embodiment of the present invention will be described with reference to FIG.
この実施例は電流源として横形PNPのかわり
に不純物をイオン注入した多結晶シリコンの高抵
抗３８を形成したものである。 In this embodiment, a high resistance 38 made of polycrystalline silicon into which impurity ions are implanted is formed instead of a horizontal PNP as a current source.
多結晶シリコン抵抗は酸化膜の上に形成できる
ので、寄生容量がなく、さらにスイツチング速度
を速くできる。また、多結晶シリコン上の白金シ
リサイドは、選択酸化されない多結晶シリコンの
上にのみ形成されるので、酸化膜上の白金は王水
等のエツチング液で自己整合的に除去される。従
つてベース拡散領域と引き出し電極の間には目合
わせは不要である。 Since the polycrystalline silicon resistor can be formed on an oxide film, there is no parasitic capacitance, and the switching speed can be further increased. Furthermore, since platinum silicide on polycrystalline silicon is formed only on polycrystalline silicon that is not selectively oxidized, platinum on the oxide film is removed in a self-aligned manner with an etching solution such as aqua regia. Therefore, no alignment is required between the base diffusion region and the extraction electrode.
以上説明したように、本発明によれば、I2Lの
インバータを独立に酸化物などの絶縁物で分離
し、各トランジスタの共通ベースを多結晶シリコ
ンと自己整合した金属シリサイド層からなる引き
出し電極で接続することによつて、ベース直列抵
抗を小さくでき、スイツチング速度を速くするこ
とができる。 As explained above, according to the present invention, I 2 L inverters are independently separated using an insulator such as an oxide, and the common base of each transistor is connected to an extraction electrode made of a metal silicide layer self-aligned with polycrystalline silicon. By connecting the two, the base series resistance can be reduced and the switching speed can be increased.
第１図ａ及びｂはそれぞれ従来のI2Lの平面図
及び断面図、第２図はその等価回路図、第３図ａ
及びｂはそれぞれ本発明の一実施例の平面図及び
断面図、第４図ａ〜ｄは前記実施例の製法を示す
断面図、第５図は本発明の他の実施例を示す断面
図である。
１，２，３……コレクタ、４……ベースコンタ
クト、５……共通ベース領域、６……インジエク
タ、T1，T2，T3……インバータトランジスタ、
T4……インジエクタトランジスタ、γ1，γ2，γ3
……ベース直列抵抗、３０……Ｐ型シリコン基
板、３１，３２……コレクタ、３１′，３２′及び
３１″，３２″……コレクタ引き出し電極用の多結
晶シリコン及び白金シリサイド、３３……共通エ
ミツタ、３３′及び３３″……エミツタ引き出し電
極用の多結晶シリコン及び白金シリサイド、３
４，３５……インバータベース、３４′及び３
４″……ベース引き出し電極用の多結晶シリコン
及び白金シリサイド、３６……インジエクタ
PNPコレクタ、３７……インジエクタPNPエミ
ツタ、３７′及び３７″……インジエクタエミツタ
引き出し電極用の多結晶シリコン及び白金シリサ
イド、３８……イオン注入の多結晶シリコン抵
抗、３９……Ｎ形エピタキシヤル層、４０……
N+形埋込層、４１……フイールド酸化膜、４２
……多結晶シリコンの酸化膜、４３，４５……シ
リコン窒化膜、４４……多結晶シリコン（ポリシ
リコン）。
Figures 1a and b are a plan view and a cross-sectional view of a conventional I 2 L, respectively, Figure 2 is its equivalent circuit diagram, and Figure 3a
and b are respectively a plan view and a cross-sectional view of one embodiment of the present invention, FIGS. 4 a to d are cross-sectional views showing the manufacturing method of the above-mentioned embodiment, and FIG. be. 1, 2, 3...Collector, 4...Base contact, 5...Common base region, 6...Injector, T1 , T2 , T3 ...Inverter transistor,
T 4 ... Injector transistor, γ 1 , γ 2 , γ 3
...Base series resistance, 30...P-type silicon substrate, 31, 32...Collector, 31', 32' and 31'', 32''...Polycrystalline silicon and platinum silicide for collector extraction electrode, 33...Common Emitters, 33' and 33''...Polycrystalline silicon and platinum silicide for emitter extraction electrodes, 3
4, 35...Inverter base, 34' and 3
4″...Polycrystalline silicon and platinum silicide for base extraction electrode, 36...Injector
PNP collector, 37... Injector PNP emitter, 37' and 37''... Polycrystalline silicon and platinum silicide for injector emitter extraction electrode, 38... Ion-implanted polycrystalline silicon resistor, 39... N-type epitaxial Layer, 40...
N + type buried layer, 41...field oxide film, 42
...Polycrystalline silicon oxide film, 43, 45...Silicon nitride film, 44...Polycrystalline silicon (polysilicon).
Claims (1)
タ用トランジスタを有し、これらトランジタが埋
込絶縁膜で分離され、さらに前記インバータ用ト
ランジスタは互いに埋込絶縁膜で分離された複数
のベース領域を有する半導体装置の製造方法にお
いて、前記埋込絶縁膜を形成した後に前記ベース
領域を形成し、その後全面に多結晶シリコン層を
形成し、前記多結晶シリコン層を選択的に酸化す
ることにより前記ベース領域間を結ぶ第１の多結
晶シリコンパターンと各ベース領域にそれぞれ接
触する複数の第２の多結晶シリコンパターンとを
酸化膜で分離形成し、前記第１の多結晶シリコン
パターンに不純物を導入してベース配線を形成
し、前記第２の多結晶シリコンパターンに不純物
を導入して各ベース領域にコレクタ領域を形成
し、金属を全面に蒸着し熱処理することにより各
多結晶シリコンパターン上に前記酸化膜で分離さ
れた金属シリサイド層を形成することを特徴とす
る半導体装置の製造方法。1. A method for manufacturing a semiconductor device having an injector transistor and an inverter transistor, these transistors being separated by a buried insulating film, and the inverter transistor having a plurality of base regions separated from each other by a buried insulating film. , forming the base region after forming the buried insulating film, then forming a polycrystalline silicon layer on the entire surface, and selectively oxidizing the polycrystalline silicon layer to form a first base region connecting the base regions. forming a polycrystalline silicon pattern and a plurality of second polycrystalline silicon patterns in contact with each base region, separated by an oxide film, and introducing impurities into the first polycrystalline silicon pattern to form a base wiring; A collector region is formed in each base region by introducing impurities into the second polycrystalline silicon pattern, and metal silicide separated by the oxide film is formed on each polycrystalline silicon pattern by vapor depositing metal over the entire surface and heat-treating it. A method for manufacturing a semiconductor device, comprising forming a layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58023960A JPS59149045A (en) | 1983-02-16 | 1983-02-16 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58023960A JPS59149045A (en) | 1983-02-16 | 1983-02-16 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59149045A JPS59149045A (en) | 1984-08-25 |
| JPH0425711B2 true JPH0425711B2 (en) | 1992-05-01 |
Family
ID=12125110
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58023960A Granted JPS59149045A (en) | 1983-02-16 | 1983-02-16 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59149045A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06820Y2 (en) * | 1986-01-22 | 1994-01-05 | 株式会社日立製作所 | Active matrix substrate |
| US4951102A (en) * | 1988-08-24 | 1990-08-21 | Harris Corporation | Trench gate VCMOS |
| US5032529A (en) * | 1988-08-24 | 1991-07-16 | Harris Corporation | Trench gate VCMOS method of manufacture |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55103740A (en) * | 1979-01-31 | 1980-08-08 | Nec Corp | Semiconductor device |
| JPS55125651A (en) * | 1979-03-22 | 1980-09-27 | Nec Corp | Production of semiconductor integrated circuit |
| JPS5613020A (en) * | 1979-07-13 | 1981-02-07 | Norio Owaki | Purifying apparatus of polluted air |
| JPS56116618A (en) * | 1980-02-20 | 1981-09-12 | Toshiba Corp | Manufacture of semiconductor device |
-
1983
- 1983-02-16 JP JP58023960A patent/JPS59149045A/en active Granted
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55103740A (en) * | 1979-01-31 | 1980-08-08 | Nec Corp | Semiconductor device |
| JPS55125651A (en) * | 1979-03-22 | 1980-09-27 | Nec Corp | Production of semiconductor integrated circuit |
| JPS5613020A (en) * | 1979-07-13 | 1981-02-07 | Norio Owaki | Purifying apparatus of polluted air |
| JPS56116618A (en) * | 1980-02-20 | 1981-09-12 | Toshiba Corp | Manufacture of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59149045A (en) | 1984-08-25 |
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