JP3135615B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an IIL (Integrated I
The present invention relates to a semiconductor device provided with njection logic (I ² L) and a method of manufacturing the same.

[0002]

2. Description of the Related Art IIL is one of the components of a bipolar IC that has attracted attention in terms of high speed, high integration, and low power consumption.
For example, a lateral PNP transistor (a PNP portion functioning as a current source or injector) and a reverse-acting multi-collector NPN transistor (II) whose base is current-biased by the lateral PNP transistor
(An NPN portion as an L switching element).

As one of the semiconductor devices, a vertical PN
There is known a bipolar IC in which a P transistor, a vertical NPN transistor, and an IIL are simultaneously formed in parallel on a common semiconductor substrate while forming an element isolation region therebetween (Japanese Patent Laid-Open No. 59-141261). Gazette). A vertical transistor has an emitter-base junction and a base-
Unlike a lateral transistor in which the junction between collectors is formed along the surface of the substrate, the junction has a structure in which both junctions face each other in the thickness direction of the substrate. Are better.

FIG. 6 shows a vertical PNP transistor and a vertical NNP transistor.
FIG. 11 is a cross-sectional view showing an IIL portion of a conventional semiconductor device in which a PN transistor and an IIL are formed on a common semiconductor substrate. Hereinafter, a conventional example of a semiconductor device will be described with reference to FIG.

In FIG. 1, reference numeral 1 designates a P-type semiconductor substrate. On the same main surface of the P-type semiconductor substrate 1, there are provided three layers of IIL and a vertical PNP transistor and a vertical NPN transistor (not shown). Are separated from each other by element isolation regions. 5 is a vertical NPN transistor second N ⁺ -type buried layer formed in the first N ⁺ -type buried layer simultaneously and in the same process as the collector buried layer of the emitter region of the NPN part of IIL It will be a part. 6 is a second P ⁺ -type buried layer formed in the first P ⁺ -type buried layer simultaneously and in the same process as the collector buried layer of the vertical PNP transistor, constitutes a part of the isolation region It becomes a lower isolation region.

Reference numeral 9 denotes an N ⁻ type epitaxial layer,
It becomes a part of the emitter region of the NPN portion of the IIL and the like. Reference numerals 12 and 10 denote second and third P ⁻ -type diffusion layers formed simultaneously and in the same process as the first P ⁻ -type diffusion layer that is a part of the collector region of the vertical PNP transistor, The second P ^- type diffusion layer 12 is made of NIL of IIL.
Part of the base region of the third P ⁻ -type diffusion layer 1
Numeral 0 is an upper isolation region constituting a part of the element isolation region. 14, a vertical and a second N ⁺ -type diffusion region formed in the first N ⁺ -type diffusion region and simultaneously and the same process as the collector wall region of the NPN transistor, the emitter region of the NPN part of IIL It will be a part.

[0007] Reference numerals 17 and 18 denote second and third P-type diffusion layers formed simultaneously and in the same process as the first P-type diffusion layer serving as the base region of the vertical NPN transistor. The third P-type diffusion layer 17 becomes an injector region of IIL, and the third P-type diffusion layer 18 becomes a part of the base region of the NPN portion of IIL.

Reference numerals 20 and 100 denote second and third N-type diffusion layers formed simultaneously and in the same process as the first N-type diffusion layer serving as a base region of the vertical PNP transistor. The N-type diffusion layer 20 becomes a plurality of collector regions in the NPN portion of the IIL, and the third N-type diffusion layer 100
It becomes a part of the emitter region of the NPN portion of L. However, the plurality of second N-type diffusion layers 20 are in contact with both the second P ⁻ -type diffusion layer 12 and the third P-type diffusion layer 18. 23, the first N ⁺ -type diffusion layer and the second and third N ⁺ -type diffusion layer simultaneously and as a collector contact region and the emitter region of each vertical NPN transistor as the base contact region of the vertical PNP transistor A fourth N ⁺ -type diffusion layer formed by the same process and serving as a plurality of IIL collector contact regions.

As described above, the second P-type semiconductor substrate 1 side
The N ⁺ type buried layer 5, the N ⁻ type epitaxial layer 9, the second N ⁺ type diffusion region 14 and the third N type diffusion layer 100 are used as the emitter region, and the second P ⁻ type diffusion layer 12 and the third P-type diffusion layer 18 as a base region, and a plurality of second N
-Operation type multi-collector NPN transistor is formed using the N type diffusion layer 20 and the fourth N ⁺ type diffusion layer 23 as a plurality of collector regions and collector contact regions, respectively, and the NPN transistor functions as an IIL switching element. .

Further, a lateral PNP transistor is formed in which the second P-type diffusion layer 17 is used as an emitter region, the third N-type diffusion layer 100 is used as a base region, and the third P-type diffusion layer 18 is used as a collector region. ing. A base region and a collector region of the lateral PNP transistor are respectively common to a part of an emitter region and a part of a base region of the multi-collector NPN transistor, and the lateral PNP transistor serves as a current source for the multi-collector NPN transistor. It works. That is, the horizontal PN
The second P-type diffusion layer 17, which is the emitter region of the P transistor, is the IIL injector region.

[0011]

In the above-mentioned conventional semiconductor device, the N ^-- type epitaxial layer 9 and the second P ^-- type diffusion layer 12 having a low impurity concentration are composed of an IIL multi-collector NP.
Since the emitter-base junction of the N transistor is formed, there is an advantage that the emitter injection efficiency of the transistor is increased and the current amplification factor of the IIL is increased.

However, the low-concentration second P ⁻ -type diffusion layer 12 and the second N-type diffusion layer 20 are connected to the multi-collector NP.
Base of the N-transistor - since to form the collector junction, N ^- a problem which can not be obtained collector-emitter breakdown voltage required when thin type epitaxial layer 9 occurs, the N ^- -type epitaxial layer 9 However, it has not been possible to realize further higher speed and higher integration by thinning the film. That, N ^- -type When epitaxial layer 9 thinner, the N along with this ^- the second type epitaxial layer 9
The P ⁻ -type diffusion layer 12 must be formed shallow, and the base width of the multi-collector NPN transistor determined by the thickness of the second P ⁻ -type diffusion layer 12 decreases. When the base region of the multi-collector NPN transistor has a low concentration and a small base width, the collector-emitter region of the multi-collector NPN transistor enters a punch-through state at a low voltage and the IIL does not operate normally.

On the other hand, when the impurity concentration of the second P ⁻ -type diffusion layer 12 is to be uniformly increased in order to increase the collector-emitter breakdown voltage, the base-side junction at the emitter-base junction is required. The impurity concentration of the second P ⁻ -type diffusion layer 12 is higher than that of the N ⁻ -type epitaxial layer 9 on the emitter side, and the current amplification factor of the IIL decreases. Also,
As described above, when the first P ⁻ -type diffusion layer is formed as a part of the collector region of the vertical PNP transistor at the same time and in the same process as the second P ⁻ -type diffusion layer 12,
Since the impurity concentration of the first P ⁻ -type diffusion layer also increases with the increase in the concentration of the P ⁻ -type diffusion layer 12, the vertical PNP
There is also a problem that the early voltage of the transistor is reduced.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and further increases the speed and speed of a semiconductor device while maintaining a high current amplification factor of an IIL and a collector-emitter breakdown voltage required for the IIL. The purpose is to realize integration.

[0015]

In order to solve the above-mentioned problems, the present invention divides an emitter region and a base region of an IIL into two layers, respectively , to form an emitter- base junction.
In this configuration, the impurity concentration of each of the base portion and the base portion is low, and the impurity concentration of the other base portion forming the base-collector junction is high.

More specifically, the invention of claim 1 is
A first emitter layer of a first conductivity type, and the first emitter layer
Formed thereon and having a lower impurity concentration than the first emitter layer
A second emitter layer of a first conductivity type and the second emitter layer
A first base layer of a second conductivity type formed on the first base layer to form an emitter-base junction only with the second emitter layer; and a first base formed on the first base layer . a second base layer in impurity concentration than the layer of the higher second conductivity type, said
A semiconductor device including an IIL having a first conductivity type collector layer formed on a second base layer and forming a base-collector junction only with the second base layer; It is.

The invention according to claims 2 to 4 is a first conductivity type of the first type .
And a method for manufacturing a semiconductor device having an IIL having a second emitter layer, first and second base layers of the second conductivity type, and a collector layer of the first conductivity type. The invention of Item 2 provides a semiconductor substrate having a first conductivity type.
Forming one emitter layer; and forming the emitter layer on the semiconductor substrate.
The first emitter layer is formed on the first emitter layer by epitaxial growth.
A second impurity of the first conductivity type having an impurity concentration lower than that of the first emitter layer;
Of forming an emitter layer, forming a first base layer of a second conductivity type in said second emitter layer by doping of the second emitter layer, the first base layer Forming a second base layer of a second conductivity type having a higher impurity concentration than the first base layer on the first base layer by doping; and doping the second base layer by doping the second base layer. the configuration and forming a collector layer of a first conductivity type on the second base layer is adopted, the second emitter
Emitter-base indirect only between the layer and the first base layer
The base is only between the second base layer and the collector layer
The collector junctions are to be formed, respectively .

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device in which a vertical PNP transistor and an IIL are formed on a common semiconductor substrate.
Of the first base layer is formed simultaneously with the same process as the formation of the collector layer of the vertical PNP transistor.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device in which a vertical NPN transistor and an IIL are formed on a common semiconductor substrate.
Of the second base layer is formed simultaneously with the same process as the formation of the base layer of the vertical NPN transistor.

[0020]

According to the first aspect of the present invention, the first base layer, which is a low-concentration portion, forms an emitter-base junction with the low-concentration second emitter layer, and the first base layer, which is a high-concentration portion, Since the base layer 2 is almost depleted during the operation of the IIL, the emitter injection efficiency is increased as in the related art, and the high current amplification factor of the IIL can be maintained. Further, the second base layer, which is a high-concentration portion, forms a base-collector junction with the collector layer, and the interposition of the second base layer causes depletion of the base-collector junction toward the base. Since the spread of the layer can be suppressed, punch-through between the collector and emitter hardly occurs even if the base width is reduced, and a high collector /
An emitter breakdown voltage is obtained.

According to the second aspect of the present invention, the high-density first
The emitter layer and the low-concentration second emitter layer form an IIL
A low-concentration first base layer and a high-concentration second base layer form an IIL base region, and a low-concentration second emitter layer and a low-concentration first base. emitter only between the layers - while base junction is formed, only the base between a high concentration second base layer and the collector layer of the - collector junction is formed. Therefore, not only can the high current amplification factor of the IIL be maintained as in the related art, but also a high collector-emitter breakdown voltage can be obtained even if the base width is reduced.

According to the third aspect of the present invention, since the low concentration first base layer of the IIL and the collector layer of the vertical PNP transistor are formed simultaneously and in the same process, the collector of the vertical PNP transistor is formed. The layer does not increase in concentration. Therefore, the vertical PNP transistor and the IIL can be formed on a common semiconductor substrate without lowering the early voltage of the vertical PNP transistor. Moreover, the number of steps does not increase as compared with the conventional case.

According to the fourth aspect of the present invention, the high concentration second base layer of the IIL and the base layer of the vertical NPN transistor are formed simultaneously and in the same process. The vertical NPN transistor and the IIL can be formed on a common semiconductor substrate without increasing.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to one embodiment of the present invention and a method for manufacturing the same will be described below with reference to the drawings.

FIGS. 1 to 4 are cross-sectional views showing a manufacturing process of a semiconductor device according to an embodiment of the present invention in which a vertical PNP transistor, a vertical NPN transistor, and an IIL are formed on a common semiconductor substrate.

First, as shown in FIG. 1, the main surface of a P-type (111) semiconductor substrate 1 having a specific resistance of, for example, 10 to 20 .OMEGA.cm
After ion implantation under the condition of 1 × 10 ¹³ / cm ² , 120
By performing heat treatment at 0 ° C. for about 120 minutes, the vertical P
An N-type buried layer 2 for separating the collector region of the NP transistor from the P-type semiconductor substrate 1 is formed. Next, arsenic is applied at 60 keV and 1 × 1 using a resist as a mask, for example.
After ion implantation under the condition of 0 ¹⁵ / cm ² ,
By heat treatment of about 0 minutes, the first N ⁺ -type buried layer 4 serving as a collector buried layer of the vertical NPN transistor, a second N ⁺ -type buried to be a part of the emitter region of the NPN part of IIL The layer 5 is formed at the same time. further,
For example, using a resist as a mask, boron is
After ion implantation under the condition of × 10 ¹⁴ / cm ² , 1100
Heat treatment at 180 ° C for about 180 minutes allows vertical PN
A first P ⁺ -type buried layer 7 serving as a collector buried layer of a P transistor and a second P ⁺ -type buried layer 6 serving as a lower isolation region constituting a part of an element isolation region are simultaneously formed.
In this case, since the diffusion coefficient of the impurity increases in the order of arsenic, boron, and phosphorus, the depth of the buried layer is, as shown, the first and second N ⁺ -type buried layers 4, 5, the first and second N ⁺ buried layers. The P ⁺ -type buried layers 6 and 7 become deeper in the order of the N-type buried layer 2.

Next, as shown in FIG. 2, P-type on the semiconductor substrate 1 becomes a part such as the emitter region of the NPN part of IIL example resistivity 1 [Omega · cm, a thickness of 2.5 [mu] m N ^- type After the epitaxial layer 9 is formed, boron is applied at 80 keV, 2 × 10 ¹² / cm using, for example, a resist as a mask.
After the ion implantation under the conditions of ² , a heat treatment at about 1100 ° C. for about 100 minutes is performed so that the first P ⁻ -type diffusion layer 11 which becomes a part of the collector region of the vertical PNP transistor is formed.
And a second part of the base region of the NPN portion of the IIL
Of the P ⁻ type diffusion layer 12 and the third P ⁻ type diffusion layer 10 serving as an upper isolation region which constitutes a part of the element isolation region. Furthermore, for example, after ion implantation of phosphorus at 80 keV and 3 × 10 ¹⁵ / cm ^{2 using} a resist as a mask, a heat treatment is performed at 950 ° C. for about 30 minutes to form a collector wall region of the vertical NPN transistor. A first N ⁺ -type diffusion region 13 and a second N ⁺ -type diffusion region 14 that is part of the emitter region of the NPN portion of the IIL
And are formed.

Next, as shown in FIG. 3, for example, using a resist as a mask, boron is applied at 30 keV and 2 × 10 ¹³ / c.
After the ion implantation under the condition of m ² , a heat treatment at 900 ° C. for about 30 minutes is performed, whereby the first P-type diffusion layer 16 serving as the base region of the vertical NPN transistor and the second P-type diffusion layer serving as the IIL injector region are formed. P-type diffusion layer 17 and IIL
The third P-type diffusion layer 18 which becomes a part of the base region of the NPN portion and the fourth P-type diffusion layer 15 which becomes a part of the element isolation region are simultaneously formed.

Further, as shown in FIG. 4, for example, using a resist as a mask, phosphorous is 80 keV, 4 × 10 ¹³ / cm.
The first N-type diffusion layer 19 serving as a base region of the vertical PNP transistor is formed by performing ion implantation under the condition ( ² ).
A plurality of second N-type diffusion layers 20 serving as a collector region of the NPN portion of the IIL are simultaneously formed. However, the third P
Plurality of second N-type diffusion layers 2 formed on type diffusion layer 18
0 prevents any of them from reaching the second P ⁻ type diffusion layer 12. Next, on each region serving as a collector contact, a base contact and an emitter of a vertical PNP transistor, on each region serving as a collector contact, a base contact and an emitter of a vertical NPN transistor, and
After a polysilicon film (not shown) is formed on each of the IIL injector contact, collector contact, base contact, and emitter contact, a region serving as a base contact of the vertical PNP transistor using, for example, a resist as a mask. Arsenic is applied at 60 keV and 1 × 10 ¹⁶ / cm ^{2 in} the polysilicon film on the upper region, on each region serving as the collector contact and the emitter contact of the vertical NPN transistor, and on each region serving as the collector contact and the emitter contact of the IIL. Then, heat treatment is performed at 950 ° C. for about 60 minutes to diffuse arsenic from the polysilicon film, thereby forming a vertical P
A first N ⁺ -type diffusion layer 25 serving as a base contact region of the NP transistor, a second N ⁺ -type diffusion layer 22 serving as a collector contact region of the vertical NPN transistor, and an emitter region of the vertical NPN transistor Third N
^{A +} type diffusion layer 21, a fourth N ⁺ type diffusion layer 23 serving as an IIL collector contact region, and a fifth N ⁺ type diffusion layer 24 serving as an IIL emitter contact region are simultaneously formed. Subsequently, for example, on a region serving as a base contact of a vertical NPN transistor using a resist as a mask, on a region serving as a collector contact and an emitter of a vertical PNP transistor, and on a region serving as an injector contact and a base contact of an IIL Boron in the polysilicon film of 30 keV, 2 × 10 ¹⁶ / c
By implanting ions under the condition of m ² and then performing a heat treatment at 900 ° C. for about 45 minutes to diffuse boron from the polysilicon film, the first P ⁺ -type diffusion which becomes the base contact region of the vertical NPN transistor is formed. Layer 28 and vertical PN
A second P ⁺ -type diffusion layer 27 serving as a collector contact region of the P-transistor, a third P ⁺ -type diffusion layer 26 serving as an emitter region of the vertical PNP transistor, and a fourth P-type diffusion layer 26 serving as an IIL injector contact region P ⁺ type diffusion layer 2
9 and a fifth P serving as a base contact region of the IIL.
^{The +} type diffusion layer 30 is formed simultaneously. Finally, for example, A
An electrode wiring using l (aluminum) or the like is formed to complete the present semiconductor device.

As described above, in this embodiment , NP of IIL
The N-part emitter region is formed by the second N ⁺ type buried layer 5 and the second
N ⁻ type epitaxy having a lower impurity concentration than the N ⁺ type buried layer 5 of FIG.
Composed of two layers of a Kisharu layer 9 and the base region of the NPN part of the IIL of the 2 P ^- type diffusion layer 12 and said 2 P ^-
Third P-type diffusion layer 1 having an impurity concentration higher than that of p-type diffusion layer 12
And an emitter-base junction is formed only between the low-concentration N ⁻ -type epitaxial layer 9 and the low-concentration second P ⁻ -type diffusion layer 12. On the other hand, a base-collector junction is formed only between the high-concentration third P-type diffusion layer 18 and the plurality of second N-type diffusion layers 20. In addition, the second P ⁻ -type diffusion layer 12 on the emitter side is formed simultaneously and in the same process as the low-concentration first P ⁻ -type diffusion layer 11 that becomes a part of the collector region of the vertical PNP transistor.
A third P-type diffusion layer 18 on the collector side is formed simultaneously with the same process as the high-concentration first P-type diffusion layer 16 serving as a base region of a vertical NPN transistor.

FIG. 5 is a conceptual diagram showing an impurity concentration profile at a position where the IIL collector contact region 23 of the semiconductor device of FIG. 4 is formed. As shown in the figure, a second emitter-base junction is formed with the N ⁻ -type epitaxial layer 9 constituting a part of the emitter region.
The impurity concentration of the P ⁻ -type diffusion layer 12 (lower layer of the base region) is kept as low as the conventional one, while the base concentration between the P ⁻ -type diffusion layer 12 and the second N-type diffusion layer 20 constituting a part of the collector region is reduced.
The impurity concentration of the third P-type diffusion layer 18 (upper layer of the base region) which forms the collector-to-collector junction can be made higher than before.

Therefore, according to the present embodiment, the third P
The diffusion of the depletion layer to the base side of the base-collector junction of the IIL can be suppressed by the interposition of the type diffusion layer 18.
The IIL collector-emitter breakdown voltage can be made higher than before. On the other hand, the impurity concentration distribution at the junction between the emitter and the base is the same as the conventional one, and the high concentration portion on the base side of the junction between the base and the collector, that is, the third P-type diffusion layer 18 is formed.
Is almost depleted at the time of IIL operation, so that a current amplification rate that is not different from the conventional one can be obtained. That is, according to the present embodiment, the N ⁻ -type epitaxial layer 9 can be made thinner in order to achieve higher speed and higher integration, and the high-speed integration of the vertical PNP transistor, the vertical NPN transistor, and the IIL. Thus, a semiconductor device with high density and high withstand voltage can be realized. In addition, the first P ^- type diffusion layer 11 of the vertical PNP transistor and the second P ^- type diffusion layer 12 of the IIL are formed simultaneously and in the same process, and the first P ^- type diffusion layer 11 of the vertical NPN transistor is formed. Since the layer 16 and the third P-type diffusion layer 18 of IIL are formed simultaneously and by the same process, the number of manufacturing steps does not increase compared to the related art. However, the formation of the first P ⁻ -type diffusion layer 11 and the second P ⁻ -type diffusion layer 12 can be performed in separate steps. The first P-type diffusion layer 16 and the third
The same applies to the formation of the P-type diffusion layer 18.

[0033]

As described above, according to the first aspect of the present invention, the high concentration first emitter layer is formed in the IIL emitter region.
And a lightly doped second emitter layer, and II
The base region of L is divided into a low-concentration first base layer and a high-concentration second base layer, and the emitter is disposed only between the low-concentration second emitter layer and the low-concentration first base layer. while forming the base junction, the base only between the high-concentration second base layer and the collector layer of - because adopting the structure of the semiconductor device forms the collector junction, the second emitter So及
By the action of the first base layer, the high current amplification factor of the IIL can be maintained as in the conventional case, and a high collector-emitter breakdown voltage can be obtained even if the base width is reduced by the interposition of the second base layer. Speed and high integration can be realized.

According to the second aspect of the present invention, the semiconductor substrate has a shape.
Epitaxial on the high concentration first emitter layer formed
The semiconductor device formed on in terms of the formation of the second emitter layer of a low concentration of the first and second base layers and sequentially each collector layer by performing one after another doping to the second emitter layer by growing Since the manufacturing method was adopted,
An emitter-base junction is formed only between the low-concentration second emitter layer and the low-concentration first base layer, while only between the high-concentration second base layer and the collector layer. A base-collector junction is formed. Therefore, not only can the high current amplification factor of the IIL be maintained as in the related art, but also a high collector-emitter breakdown voltage can be obtained even if the base width is reduced, and higher speed and higher integration can be realized.

In particular, according to the invention of claim 3, the above II
Since the first base layer having a low concentration of L is formed simultaneously with the formation of the collector layer of the vertical PNP transistor by the same process, the vertical PNP transistor can be formed without lowering the Early voltage. The PNP transistor and the IIL can be formed on a common semiconductor substrate. Moreover, the number of steps does not increase as compared with the conventional case. According to the fourth aspect of the present invention, the formation of the high concentration second base layer of IIL is performed simultaneously with the same process as the formation of the base layer of the vertical NPN transistor. Thus, the vertical NPN transistor and the IIL can be formed on a common semiconductor substrate without increasing the number of steps.

[Brief description of the drawings]

FIG. 1 is a first manufacturing process sectional view of a semiconductor device according to an embodiment of the present invention in which a vertical PNP transistor, a vertical NPN transistor, and an IIL are formed on a common semiconductor substrate.

FIG. 2 is a second manufacturing process sectional view showing a manufacturing process following FIG. 1;

FIG. 3 is a third manufacturing process sectional view showing a manufacturing process following FIG. 2;

FIG. 4 is a fourth manufacturing process sectional view showing the completed state of the semiconductor device according to one embodiment of the present invention;

5 is a conceptual diagram showing an impurity concentration profile at a position where an IIL collector contact region is formed in the semiconductor device of FIG. 4;

FIG. 6 is a cross-sectional view showing an IIL portion of a conventional semiconductor device in which a vertical PNP transistor, a vertical NPN transistor, and an IIL are formed on a common semiconductor substrate.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... P-type semiconductor substrate 2 ... N-type buried layer (separation area between the collector region of a vertical PNP transistor and a substrate) 4 ... 1st N ⁺ type buried layer (collector buried layer of a vertical NPN transistor) 5 ... Second N ⁺ type buried layer (part of emitter region of IIL ) [First emitter layer of first conductivity type of IIL] 6 ... Second P ⁺ type buried layer (part of element isolation region lower isolation region) 7 ... first P ⁺ -type buried layer (vertical PNP transistor collector buried layer of) 9 ... N made ^- -type epitaxial layer [the first conductivity type IIL first
2 emitter layer] 10... Third P ⁻ -type diffusion layer (upper isolation region that becomes a part of the element isolation region) 11... First P ⁻ -type diffusion layer (a part of the collector region of the vertical PNP transistor) [Collector layer of vertical PNP transistor] 12... Second P ⁻ type diffusion layer (part of base region of IIL) [first base layer of second conductive type of IIL] 13. First N ⁺ type Diffusion region (collector wall region of vertical NPN transistor) 14... Second N ⁺ -type diffusion region (part of emitter region of IIL) 15 .. fourth P-type diffusion layer (part of element isolation region) 16. First P-type diffusion layer (base region of vertical NPN transistor) [Base layer of vertical NPN transistor] 17... Second P-type diffusion layer (IIL injector region) 18... Third P-type diffusion layer ( Part of the base region of IIL)
[Second base layer of second conductivity type of IIL] 19: first N-type diffusion layer (base region of vertical PNP transistor) 20: second N-type diffusion layer (collector region of IIL) [I
IL first conductivity type collector layer] 21... Third N ⁺ type diffusion layer (emitter region of vertical NPN transistor) 22... Second N ⁺ type diffusion layer (collector contact region of vertical NPN transistor) 23 ... Fourth N ⁺ -type diffusion layer (collector contact region of IIL) 24 .. Fifth N ⁺ -type diffusion layer (emitter contact region of IIL) 25 .. First N ⁺ -type diffusion layer (base of vertical PNP transistor) Contact region) 26: third P ⁺ type diffusion layer (emitter region of vertical PNP transistor) 27: second P ⁺ type diffusion layer (collector contact region of vertical PNP transistor) 28: first P ⁺ type diffusion layers (vertical base contact region of the NPN transistor) 29 ... fourth P ⁺ -type diffusion layer (injector contact region IIL) 30 ... fifth P ⁺ -type diffusion layer (IIL the base Contact area)

────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Mitsuo Tanaka 1006 Kazuma Kadoma, Kadoma-shi, Osaka Matsushita Electric Industrial Co., Ltd. (56) References JP-A-58-98957 (JP, A) (58) Survey Field (Int.Cl. ⁷ , DB name) H01L 21/8226 H01L 27/082

Claims (4)

(57) [Claims] A first emitter layer of a first conductivity type and a first emitter layer formed on the first emitter layer;
Second emitter layer of first conductivity type having lower impurity concentration
A first base layer of a second conductivity type formed on the second emitter layer and forming an emitter-base junction only with the second emitter layer; and the first base layer A second conductive type second base layer having a higher impurity concentration than the first base layer, and a second conductive type second base layer formed on the second base layer. A semiconductor device comprising: an IIL having a first conductivity type collector layer forming a base-collector junction. 2. A semiconductor device comprising an IIL having first and second emitter layers of a first conductivity type, first and second base layers of a second conductivity type, and a collector layer of a first conductivity type. A method for manufacturing , comprising: forming the first emitter layer on a semiconductor substrate; and epitaxially growing the first emitter layer on the semiconductor substrate.
The impurity concentration on the emitter layer is lower than that of the first emitter layer.
Forming a have the second emitter layer, and forming the first base layer to said second emitter <br/> jitter layer by doping into the second emitter layer, the The second base layer having a higher impurity concentration than the first base layer on the first base layer by doping the first base layer.
Forming a base layer on the second base layer, and forming the collector layer on the second base layer by doping the second base layer , wherein the second emitter layer and the first base are formed. Between the layers
The emitter-base junction is in front of the second base layer.
The base-collector junction only occurs with the collector layer.
A method for manufacturing a semiconductor device, wherein each of the semiconductor devices is formed . 3. The method for manufacturing a semiconductor device according to claim 2, wherein forming the first base layer of the IIL comprises forming a collector layer of a vertical PNP transistor provided on a semiconductor substrate common to the IIL. A method for manufacturing a semiconductor device, wherein the method is performed simultaneously and in the same process. 4. The method of manufacturing a semiconductor device according to claim 2, wherein forming the second base layer of the IIL comprises forming a base layer of a vertical NPN transistor provided on a semiconductor substrate common to the IIL. A method for manufacturing a semiconductor device, wherein the method is performed simultaneously and in the same process.