JPH0629374A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To facilitate the integration of an integrated circuit device by reducing the chip area to be used by a connecting layer for leading out a terminal for providing a burying layer from the front plane when the burying layer is to be provided at the bottom of a semiconductor area for circuit element for the integrated circuit. CONSTITUTION:A double structure burying layer composed of a first burying layer 2 and a second burying layer 3 is provided at the bottom of a semiconductor area 5 permitting the second burying layer 3 to be uplifted into the semiconductor area 5 and a connecting layer 7 is diffused more shallowly from the surface of the semiconductor area 5 compared with the conventional case and is connected with the second burying layer 3. The horizontal diffusion width of the connecting layer 7 on the surface of the semiconductor area 5 is decreased and a chip area necessitated for the diffusion of the connecting layer 7 is decreased to be the half or less than the half of the conventionally necessitated area.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device in which circuit elements such as a bipolar transistor, a vertical field effect transistor and an insulated gate bipolar transistor are formed in a semiconductor region which is separated from each other and has a buried layer at the bottom. .

[0002]

2. Description of the Related Art In a semiconductor integrated circuit device composed of circuit elements as described above, the circuit elements are distributed in the semiconductor region such as an epitaxial layer which is separated from each other by means such as junction separation. In order to have necessary characteristics such as current capacity and withstand voltage, a so-called buried layer of the same conductivity type is provided at the bottom of the semiconductor region with a higher impurity concentration than that.
In many cases, the connection layer for deriving the terminal for it has a structure that diffuses from the surface of the semiconductor region to reach it.

As is well known, a structural example of such an integrated circuit device will be briefly described with reference to FIG. In the illustrated example, the transistor 10 on the surface of the p-type substrate 1
The n-type buried layer 2 is diffused in a range where 30 and 30 are to be formed, and the p-type buried separation layer 4 is diffused in a pattern that surrounds it, and then the n-type epitaxial layer 5 is grown to a predetermined thickness. Then, the p-type isolation layer 6 is diffused from the surface so as to reach the buried isolation layer 4, and the epitaxial layer 5 is junction-separated into a plurality of semiconductor regions. Transistors in this semiconductor region 5
Before forming 10 and 30, the n-type connecting layer 7 is diffused from the respective surfaces to reach the buried layer 2.

The npn transistor 10 is an n-type semiconductor region 5
The p-type base layer 11 and the n-type emitter layer 12 are sequentially diffused from the surface as a collector region, and the pnp transistor 30 uses the semiconductor region 5 as the n-type base region to form the p-type emitter layer. 31 and the collector layer 32 are diffused and formed. The p-type emitter layer 31 and the collector layer
Normally, 32 is simultaneously diffused with the p-type base layer 11 and, at this time, the p-type electrode connecting layer 8 is diffused at a predetermined position on the surface of the separation layer 6. Similarly, at the same time when the n-type emitter layer 12 is diffused, the n-type electrode connection layers 13 and 33 are diffused on the surface of the connection layer 7 of the transistors 10 and 30, respectively.

Terminals for the base B, collector C, and emitter E of these transistors 10 and 30 are respectively led out as shown in the drawing, and the ground terminal G is the electrode connection layer 8 having the same potential as the substrate 1.
In this case, the buried layer 2 below the transistors 10 and 30 is connected to the collector terminal C and the base terminal B, respectively. In the transistor 10, the buried layer 2 serves to increase the breakdown voltage by allowing a current to flow vertically in the transistor 10 to reduce the collector resistance and to spread the depletion layer into the semiconductor region 5 when the transistor 10 is turned off. 30
Then, it serves to reduce the base resistance and improve its operating characteristics. However, in the pnp transistor 30 in which the power supply voltage is applied to the emitter terminal E, the pnp type parasitic transistor 40 exists between the emitter layer 31, the semiconductor region 5 and the isolation layer 6, which causes a problem that leakage current becomes large.

The pnp transistor 30 of FIG. 4 solves this problem. In this structure, the connection layer 7 is formed as a so-called wall layer having an annular pattern that surrounds the emitter layer 31 and the collector layer 32 from the outside and is connected to the peripheral portion of the buried layer 2. Even in this structure, the parasitic transistor still exists, but since the connection layer 7 having a high impurity concentration is interposed in the n-type semiconductor region 5 which is the base region of the parasitic transistor, the current amplification factor is significantly reduced, and therefore the leakage current is practically used. Reduced to a negligible level.

[0007]

As described above, by providing the buried layer 2 of the same conductivity type at the bottom of the semiconductor region for the circuit element in the integrated circuit device having the planar structure, the operating characteristics and the breakdown voltage of the circuit element are provided. Although the value can be improved, the connection layer 7 needs to be deeply diffused to reach the buried layer 2 in order to derive the terminal for the buried layer 2 from the surface because of the planar structure. However, there is a problem that the chip area required to build each circuit element increases considerably.

For example, in order to give the transistor 10 of FIG. 4 a withstand voltage of several tens to 100 V, the epitaxial layer of the semiconductor region 5 is grown to a thickness of 10 μm, and the buried layer 2 is grown at this time or during the subsequent heat treatment. If the so-called rise is about 3 μm, the connection layer 7 must be at least 7 μm to connect to it.
Therefore, if the impurities for the connection layer 7 are ion-implanted with a pattern width of 8 μm, the diffusion width of the connection layer 7 is 20 μm due to the lateral expansion during the thermal diffusion.
As a result, the same chip area as the base layer 11 is occupied. If the connection layer 7 is an annular wall layer like the transistor 30, it occupies twice as much chip area as the area including the emitter layer 31, the collector layer 32 and the periphery thereof. Furthermore, if the diffusion depth of the connection layer 7 exceeds 5 μm, the impurity concentration below the connection layer 7 decreases and the connection with the buried layer 2 is not always sufficient, which tends to cause a reduction in yield due to defective characteristics of circuit elements. In view of such problems, an object of the present invention is to reduce the diffusion width of the connection layer for the buried layer and improve the utilization efficiency of the chip area of the integrated circuit device.

[0009]

According to the integrated circuit device of the present invention, the above-mentioned object is to provide a semiconductor layer diffused in a predetermined conductivity type and a pattern from the surfaces of the semiconductor regions separated from each other, and a semiconductor layer. A first buried layer of the same conductivity type as that buried in the bottom of the semiconductor region in a pattern including the diffusion range of the first buried layer, and a second buried layer of the same conductivity type buried in a predetermined pattern over the first buried layer This is achieved by forming a circuit element having a layer and a connection layer of the same conductivity type diffused from the surface of the semiconductor region so as to be connected to the second buried layer, and deriving terminals from each of the semiconductor layer and the connection layer. To be done.

It should be noted that it is preferable to use an impurity having a higher thermal diffusion rate than the impurity for the first buried layer as the impurity for the second buried layer in the above-mentioned structure, and the buried layer is usually n. In the case of the shape, it is advantageous to use either antimony or arsenic as the impurity of the first buried layer and phosphorus as the impurity of the second buried layer. It is preferable that the impurity concentration for the second buried layer is higher than that for the first buried layer. For example, if the impurity for the first buried layer is doped at a concentration that gives a sheet resistance of 10 to 50 Ω / □, It is preferable to introduce the impurities for the buried layer in a concentration such that the sheet resistance is 1 to 10 Ω / □. The diffusion pattern of the second embedding layer should include the pattern of the connecting layer, and the two patterns are usually matched, but the pattern of the second embedding layer is almost overlapped with the pattern of the first embedding layer in some cases.

When the circuit element is a transistor having a semiconductor region as a base region, the second buried layer, the connection layer as a wall layer, the emitter layer and the collector layer are formed in order to reduce the parasitic transistor effect. It is advantageous to form an annular pattern that surrounds from the outside and runs along the periphery of the first buried layer. Further, when the integrated circuit device is used for low voltage, an impurity having a high thermal diffusion rate is used for the second buried layer and it is introduced at a high impurity concentration to increase the so-called rise, and the connecting layer is made of the same conductivity type. It is advantageous to co-diffuse with the emitter layer and the like. The present invention is advantageous for application to an integrated circuit device having not only bipolar transistors but also vertical field effect transistors and insulated gate bipolar transistors as circuit elements.

[0012]

According to the present invention, the first buried layer, which is a conventional buried layer, is overlaid and the second buried layer of the same conductivity type is diffused so as to project or rise upward from below into the semiconductor region. By connecting the connection layer diffusing from the surface of the semiconductor region to the upper end portion of the second buried layer, the depth at which the connection layer should be diffused is substantially reduced as compared with the prior art, and the lateral direction on the surface of the semiconductor region is The width or diffusion width of the connection layer is suppressed to reduce the chip area consumed by the connection layer, and the connection between the connection layer and the first burying layer or the second burying layer is made more reliable than before.

For example, when the thickness of the semiconductor region is 10 μm,
When the second buried layer is raised by 3 to 4 μm in addition to the first buried layer being raised by 3 μm, the connection layer has a diffusion depth of 4 to 5 μm. When the impurity of (4) is introduced with a pattern width of 4 μm, which is almost the same as the depth, the lateral diffusion width of the connection layer on the surface of the semiconductor region after the thermal diffusion is 10 to 12 μm, which is conventionally 7 to 8 μm. The diffusion width of the connection layer, which has been diffused, is about half that of 20 μm as described above. Therefore, according to the present invention, the chip area occupied by the connection layer can be reduced to about half that of the conventional case, and when the connection layer is a wall layer having an annular pattern, it can be reduced to one third or less of the conventional case.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a first embodiment of an integrated circuit device according to the present invention in a state of each main manufacturing process and a completed state, and FIG. 2 shows a second embodiment of the same in a completed state. 3 and FIG. 4 are denoted by the same reference numerals, and the description of the overlapping portions will be appropriately omitted. In these embodiments, the circuit element forming the integrated circuit device is a bipolar transistor, but the present invention is not limited to this, and a general integrated circuit device having a vertical field effect transistor, an insulated gate bipolar transistor or the like as a circuit element is generally used. It can be widely applied.

FIG. 1 (a) shows an impurity introducing step for the first buried layer. In this example, the circuit elements 10 to 30 shown in FIG. 1 (g) on the surface of the p-type substrate 1 are to be formed. First buried layer 2 in range
For example, antimony Sb is introduced as an n-type impurity for use by an ion implantation method using a photoresist film or an oxide film as a mask M2. For the substrate 1, for example, one having a specific resistance of 10 to 20 Ωcm is used, and antimony Sb is, for example, 10 to 50 Ω / after thermal diffusion.
It is preferable to introduce it at a concentration at which the sheet resistance of □ can be obtained. In addition,
As the impurity for the first buried layer 2, arsenic having a relatively low thermal diffusion rate may be used similarly to antimony.

FIG. 1B shows an impurity introducing step for the second buried layer. It is preferable to use phosphorus P having a high thermal diffusion rate as the n-type impurity for the second buried layer 3, which is higher than the first buried layer 2 in a pattern designated by the mask M3 by an ion implantation method. Introduce to concentration. The pattern of the second burying layer 3 is overlapped with the first burying layer 2, and in this embodiment, for the first burying layer 2 on the left side of the drawing, the pattern along the right peripheral edge is formed.
The central first buried layer 2 is formed in a pattern covering the entire surface, and the right first buried layer 2 is formed in an annular pattern along the periphery thereof. Phosphorus P as an impurity for the second buried layer 3 is preferably introduced at a high concentration so that a sheet resistance of, for example, 1 to 10 Ω / □, which is considerably lower than that of the first buried layer 2, can be obtained after thermal diffusion.

FIG. 1C shows an impurity introduction step for the buried isolation layer 4, for example, boron B is used as a mask M4 as a p-type impurity.
The ion implantation method is carried out in a frame-like pattern surrounding each first buried layer 2 designated by. Next, FIG. 1 (d) shows a step of growing the epitaxial layer 5. As usual, the n-type epitaxial layer 5 is grown to a thickness of 10 .mu.m in this embodiment on the entire surface of the substrate 1 by the thermal CVD method. This Figure 1 (d)
The impurities in the first buried layer 2, the second buried layer 3, and the buried separation layer 4 are thermally diffused by the high temperature applied during the epitaxial growth process of FIG. 1 and the process of FIG. It goes up into the epitaxial layer 5. The degree of this rise in this embodiment is, for example, 3 μm for the first buried layer 2 and 2
The buried layer 3 has a thickness of 3 to 4 μm in addition to the first buried layer 2, and the buried separation layer 4 has a thickness of about 4 μm.

FIG. 1 (e) shows the diffusion process of the separation layer 6, in which the p-type separation layer 6 is diffused deeply so as to reach it by using boron as an impurity in a frame pattern corresponding to the buried separation layer 4. Thus, the n-type epitaxial layer is divided from the substrate 1 into a plurality of semiconductor regions 5 which are junction-separated from each other. The following Fig. 1 (f) shows the diffusion process of the connection layer 7,
From the surface of each semiconductor region 5, phosphorus is used as an impurity to diffuse the n-type connection layer 7 to a depth of 4 to 5 μm in this example at a concentration such that the surface resistance is 10 to 50 Ω / □. Connect to the buried layer 3. At this time, the pattern for introducing the impurities may have a width of 4 μm, which is almost the same as the depth, so that the lateral spread of the connection layer 7 after the thermal diffusion can be suppressed to 10 to 12 μm. Note that the connection layer 7 is diffused so as to be connected to the second buried layer 3 in the center of the figure along the peripheral portion on the right side thereof.

FIG. 1 (g) schematically shows a completed state of the integrated circuit device. The p-type base layers 11 and 21 are formed in the npn transistors 10 and 20 by boron diffusion to a depth of, for example, 3 μm, and at the same time, the emitter layer 31 and the collector layer 32 are formed in the pnp transistor 30. The electrode connection layer 8 is diffused on the surface of the separation layer 6. Also, npn transistor 10
For n and 20, the n-type emitter layers 12 and 22 are formed to a depth of, for example, 2 μm by phosphorus diffusion, and at the same time, the transistors 10 to 30 are formed.
After the electrode connection layers 13 to 33 are diffused on the surface of the connection layer 7 for use respectively, the terminals B, C, E and G are derived to complete the figure.

In the circuit element constituting the integrated circuit device of this embodiment, the npn transistor 10 has a high breakdown voltage due to the thick semiconductor region 5 existing between the npn transistor 10 and the first buried layer 2 below the base layer 11. In the npn transistor 20, the base layer 21
Since the semiconductor region 5 between the first buried layer 3 and the second buried layer 3 is thin, a low collector resistance can be obtained although the breakdown voltage is low. In the pnp transistor 30, the emitter layer 31 and the collector layer 32 are surrounded by the ring-shaped connection layer 7 from the outside, and parasitic. The transistor effect can be suppressed. Also,
In either case, the diffusion width of the connection layer 7 can be reduced as compared with the conventional case, and the chip area required for the reduction can be saved, and the connection of the connection layer 7 with the first embedded layer 2 or the second embedded layer 3 can be improved. It is possible to reduce variations in the characteristics of the circuit elements as compared with the conventional case.

FIG. 2 shows, in a completed state, an embodiment suitable for highly integrating the usual low breakdown voltage integrated circuit device of the present invention. In this embodiment, the procedure for diffusing the first buried layer 2 and the second buried layer 3 may be substantially the same as the previous embodiment, but the epitaxial layer 5 is made thinner, for example, 7 to 8 μm thick. And the second buried layer 3 is formed by high-concentration diffusion of impurities having a high thermal diffusion rate to form the connection layer 7 by 2 to 3 μm.
It only needs to be diffused to a depth of m.
Simplifying the manufacturing process by diffusing the same n-type connection layer 7 at the same time as the emitter layers 12 and 22 for the pn transistors 10 and 20. Accordingly, the base layers of npn transistors 10 and 20
The depth of the p-type diffusion for the emitter layer 31 and the collector layer 32 of the 11, 21 and pnp transistor 30 is 3 to 4 μm, and FIG.
The electrode connection layers 13 to 33 for the transistors 10 to 30 are omitted.

In this embodiment, the diffusion depth of the connection layer 7 is 2 to
Since 3 μm is sufficient, the width of the pattern for introducing impurities for that purpose is set to 2 μm, whereby the lateral width of the connection layer 7 after thermal diffusion of impurities can be suppressed to about 7 μm and the integrated circuit device can be highly integrated. Note that in the example of FIG.
The transistors 10 and 30 differ from the previous embodiment only in that they are easier to miniaturize and have a different breakdown voltage, but in the transistor 20, the breakdown voltage is because the p-type base layer 21 is in contact with the n-type second buried layer 3. Although it has a low voltage drop, the forward voltage drop thereof is as low as that of a diode, so that it can be provided with characteristics suitable for large current control. As described above, the present invention is not limited to the embodiments and can be implemented in various modes.

[0023]

As described above, in the integrated circuit device of the present invention, the semiconductor regions diffused from the surfaces of the semiconductor regions separated from each other in a predetermined conductivity type and a pattern, and the semiconductor regions in a pattern including the range thereof. Connect to the first buried layer of the same conductivity type that is buried in the bottom of the second buried layer, the second buried layer of the same conductivity type that is buried in the predetermined pattern and is overlaid on the first buried layer, and the second buried layer By forming a circuit element including a connection layer of the same conductivity type diffused from the surface of the semiconductor region and deriving terminals from the respective semiconductor layers and connection layers, the following effects can be obtained.

(A) The second buried layer is diffused so as to be overlaid on the first buried layer to rise into the semiconductor region, and the connection layer diffused from the surface of the semiconductor region is connected to the second buried layer to form the connection layer. The depth to be diffused can be reduced to suppress the lateral diffusion width, and the chip area required for diffusion of the connection layer can be reduced to half or less of the conventional chip area. (b) By connecting the connection layer to the first buried layer via the second buried layer, the connection between the connection layer and the buried layer, which has been liable to vary from the past, is ensured and the characteristics of the circuit element are improved. It is possible to reduce variations and improve the manufacturing yield of integrated circuit devices.

(C) According to the aspect in which an impurity having a higher thermal diffusion rate than that of the first buried layer is used for the second buried layer or the impurity concentration thereof is higher than that of the first buried layer, the second buried layer It is possible to further reduce the chip area required for diffusion of the connection layer by increasing the rise of the connection layer into the semiconductor region and making the diffusion depth of the connection layer shallow. (d) In the aspect in which the second buried layer is formed with a high concentration of impurities having a high thermal diffusion rate to increase the rise and thereby simultaneously diffuse the connecting layer with the emitter layer and the like, the manufacturing process is simplified and the connecting layer is formed. It is possible to further reduce the chip area required for high integration of the integrated circuit device.

[Brief description of drawings]

FIG. 1 shows a first embodiment of a semiconductor integrated circuit device according to the present invention in a state of main steps, FIG. 1A is a step of introducing impurities for a first buried layer, and FIG. The step of introducing impurities for the second buried layer, the figure (c) shows the step of introducing impurities for the buried isolation layer, the figure (d) shows the epitaxial growth step, the figure (e) shows the diffusion step of the isolation layer, Figure (f) shows the connection layer diffusion process.
(g) is an enlarged cross-sectional view of a main part showing a state at the time of completion.

FIG. 2 is an enlarged sectional view of an essential part showing a second embodiment of the present invention in a completed state.

FIG. 3 is an enlarged cross-sectional view of a main part of an integrated circuit device having a conventional structure.

FIG. 4 is an enlarged sectional view of an essential part of an integrated circuit device having a different conventional structure.

[Explanation of symbols]

 2 First buried layer 3 Second buried layer 4 Buried separation layer for junction separation of semiconductor region 5 Semiconductor region or epitaxial layer 6 Separation layer for junction separation of semiconductor region 7 Connection layer 10 npn transistor as circuit element 20 npn Transistor as Circuit Element 30 pnp Transistor as Circuit Element P Phosphorus Sb as Impurity for Second Buried Layer Sb Antimony as Impurity for First Buried Layer

Claims (3)

[Claims] 1. An integrated circuit device in which circuit elements are formed in mutually separated semiconductor regions, and a semiconductor layer diffused from the surface of the semiconductor region for the circuit elements in a predetermined conductivity type and a pattern, respectively. A first conductivity type buried in the bottom of the semiconductor region in a pattern including the diffusion range of the semiconductor layer.
A buried layer, a second buried layer of the same conductivity type that is buried in a predetermined pattern so as to be overlaid on the first buried layer, and the same diffused from the surface of the semiconductor region so as to be connected to the second buried layer. A semiconductor integrated circuit device, comprising: a conductive type connection layer, wherein terminals are respectively derived from the semiconductor layer and the connection layer. 2. A semiconductor integrated circuit device according to claim 1, wherein an impurity having a higher thermal diffusion rate is used for the second buried layer than for the first buried layer. 3. A semiconductor integrated circuit device according to claim 1, wherein the impurity concentration of the second buried layer is higher than that of the first buried layer.