JP2653019B2 - Bipolar transistor and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bipolar transistor and a method of manufacturing the same, and more particularly, to a bipolar transistor having improved lateral transistor characteristics and a method of manufacturing the same.

[0002]

2. Description of the Related Art A conventional lateral PNP transistor will be described with reference to FIGS. FIG. 5 is a cross-sectional view of a lateral PNP transistor which is an example of the related art, and FIG. 6 is a lateral PNP transistor which is another example of the related art.
It is sectional drawing of a type transistor.

A generally used lateral PNP transistor has a structure shown in FIG.
An N ⁺ -type buried region 52 and an N-type epitaxial region 53 are formed in a P-type silicon substrate 51. In the N-type epitaxial region 53, a P ⁺ emitter region 54, a P ⁺ collector region 55, and an N ⁺ base contact region 56 are formed.

Further, a lower surface P ⁺ isolation region 57 and an upper surface P ⁺ isolation region 58 are formed on the outer periphery thereof to perform electrical element isolation. In addition, 59 in FIG. 5 is a protective film,
Through the contact holes of the protective film 59, the respective regions 54, 5
An emitter electrode 60, a collector electrode 61, and a base electrode 62 which are electrically connected to 5, 56 are formed.

The lateral PNP transistor shown in FIG. 5 has the above-described structure, so that the hole injected from the emitter into the base is diffused in the lateral direction and collected at the collector, and is used as a lateral transistor. Operate.

In the lateral transistor having the structure shown in FIG. 5, the P ⁺ diffusion layers of the P ⁺ emitter region 54 and the P ⁺ collector region 55 are formed in an NPN-based diffusion layer forming step. The junction depth is small and the effective emitter-collector facing area is small. For this reason, the collection efficiency of the hole injected from the emitter at the collector is low, and as a result, the current amplification factor (hereinafter abbreviated as “H _FE ”) is low, and the reduction of H _FE at a high current is _suppressed . There was a problem of being big.

In order to solve the above problem, a lateral PNP transistor having a structure shown in FIG. 6 has been proposed. This is because, as shown in FIG. 6 is a lateral transistor structure depth of the emitter region 54 and collector region 55 which are both, extends to the buried region 52 of the underlying (JP-3-15
No. 9245).

That is, the lateral PNP transistor having the structure shown in FIG. 6 is intended to increase the efficiency of collecting holes injected from the emitter, and to reduce the emitter region.
The P ⁺ diffusion layer 63 and the P ⁺ buried layer region 64
And a structure in which the opposing area between the emitter and the collector is increased. Note that the other symbols in FIG.
Therefore, the description is omitted.

[0009]

According to the lateral transistor having the conventional structure shown in FIG. 6, the P ⁺ buried layer region 64 is formed by the autodoping of the epitaxial growth and the high-temperature heat treatment in the manufacturing process. It diffuses considerably to the surface of the mold silicon substrate 51. At the same time, the P ⁺ buried layer region 64 also diffuses in the lateral direction. Therefore, it is necessary to increase the distance between the emitter region 54 and the collector region 55 corresponding to the base width in advance.

When the arrangement of the emitter region 54 and the collector region 55 is determined as described above, the respective areas of the diffusion layer and the base width of the emitter region 54 and the diffusion layer of the collector region 55 are increased. In this case, there is a problem that the effect is the same as that obtained when a plurality of lateral PNP transistors shown in FIG. 5 are arranged so as to have the same area as the area.

In addition, since the bottom surface of P ⁺ emitter region 54 has a large area in contact with N ⁺ buried region 52, the injection of carriers into N ⁺ buried region 52 becomes excessive, and the base current is reduced. increases, the percentage mentioned the collection efficiency of the carrier, there is a problem that H _FE is not high.

Further, as a factor for determining the base width, the P ⁺ diffusion layer 63 of the collector region 55 (or the P ⁺ diffusion layer 63 of the emitter region 54) ^.
The distance between the diffusion layer 63) and the P ⁺ buried layer region 64 is also added. In general, in epitaxial growth, a pattern shift due to the thickness direction or the like, that is, a position shift between the P ⁺ buried layer region 64 and the P ⁺ diffusion layer 63 in the collector region 55 as viewed from the substrate surface occurs. ⁺ P ^{+ of} buried layer region 64 and collector region 55
A shift of the mask overlap with the diffusion layer 63 also occurs.

In the case of a lateral PNP transistor, H _FE
In order to increase the base width, the base width must be reduced to the limit. However, if the pattern shift of the epitaxial layer and the mask overlay shift occur, the base width may be smaller than the design value in some cases. Has a small value, punch-through occurs between the collector and the emitter, and the operation as a transistor cannot be satisfied. Further, when the deep diffusion layers of the collector region 55 and the emitter region 54 are opposed to each other, there is a problem that punch-through easily occurs in a deep portion inside the epitaxial layer.

The present invention has been made in view of the above-mentioned problems, and has as its object to solve the above-mentioned problems.
In particular, it is an object of the present invention to provide a bipolar transistor having improved lateral transistor characteristics and a method of manufacturing the same.
More specifically, the present invention can prevent the diffusion of the hole to the substrate side due to the built-in potential between the N-type buried region and the N-type epitaxial region, and can prevent the hole injected from the emitter into the base. Can be collected efficiently without diffusing to the outside of the collector,
Moreover Baipo it is possible to suppress the reduction of H _FE at a high current - and to provide a La transistor and a manufacturing method thereof.

[0015]

SUMMARY OF THE INVENTION A bipolar transistor according to the present invention comprises a deep P-type diffusion layer reaching an N ⁺ buried layer on an N-type epitaxial layer having an N ⁺ buried layer on a P-type substrate. A shallow P ⁺ diffusion layer, a collector region has at least a deep P type diffusion layer, and an emitter region has a shallow P ⁺ diffusion layer.
It has a structure having a diffusion layer, thereby providing the above-mentioned bipolar transistor.

That is, the bipolar transistor according to the present invention is characterized in that “ a buried region of opposite conductivity type is formed on a semiconductor substrate of one conductivity type.
And an epitaxial region of the opposite conductivity type , wherein the epitaxial region has an emitter region of one conductivity type and an emitter region of the opposite conductivity type.
And the base region, the formed one conductivity so as to surround said emitter region in contact therewith buried region and the base region
Bipolar transistor having a collector region of
Wherein the collector region is in contact with the buried region.
1 diffusion layer and a portion facing the emitter layer.
The impurity concentration is higher than that of the first diffusion layer,
A bipolar transistor having a second diffusion layer not in contact with a buried region . ”.

[0017] A method of manufacturing a bipolar transistor of the present invention, "the one conductivity type semiconductor substrate having a <br/> buried region and the opposite conductivity type epitaxial region of the opposite conductivity type, said <br /> Epitaxial region, one conductivity type emitter region and reverse
A conductive type base region and the buried region,
An emitter region and the base region are formed to surround the base region.
Bipolar transistor having a collector region of one conductivity type
In the method for manufacturing a transistor, the buried region is formed in the collector region.
Forming a first diffusion layer of one conductivity type in contact with the embedded region;
In the part facing the emitter layer, the first diffusion layer is also not formed.
Pure substance concentration is high, one conductivity type not in contact with the buried region
Forming a second diffusion layer; and a one-conductivity type emitter region.
Forming a region simultaneously or separately with the second diffusion layer
And a method for manufacturing a bipolar transistor. ” .

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to FIGS. 1 to 3 are diagrams for explaining a first embodiment (Example 1) of the present invention, and FIG. 4 is a diagram for explaining a second embodiment (Example 2) of the present invention. FIG. In the following Examples 1 and 2, a PNP transistor will be described. However, the present invention is not limited to this, and can be applied to an NPN transistor, which is also included in the present invention. It is.

(Embodiment 1) FIG. 1 is a sectional view of a bipolar transistor showing a first embodiment (Embodiment 1) of the present invention.
FIG. 2 is a sectional view taken along the line AA of FIG. 2, and FIG. 2 is a plan view thereof.

The bipolar transistor 10 of the first embodiment
As shown in FIGS. 1 and 2, an N ⁺ buried region 12 and an N-type epitaxial region 13 are formed on a P-type semiconductor substrate 11, and the periphery thereof is provided for electrical insulation of a semiconductor element. Is formed so as to reach the P-type semiconductor substrate 11.

In the epitaxial region 13 between the P-type insulating diffusion layers 19, an emitter P ⁺ diffusion layer 14, a collector P ⁺ diffusion layer
15 and a deep P-type diffusion layer 20 reaching the N ⁺ buried region 12 are formed. In the epitaxial region 13, a base contact N-type diffusion layer 16 is formed.

Further, an emitter electrode 22, a collector electrode 23, and a base electrode 24, which are electrically connected to the respective diffusion layers 14, 15, 16 through the contact holes of the interlayer film 21, are formed. The first embodiment is a bipolar transistor 10 having such a structure.

Next, a method of manufacturing the bipolar transistor 10 will be described with reference to FIG. FIG. 3 is a view for explaining the method for manufacturing the bipolar transistor of the first embodiment, and is a cross-sectional view in the order of steps A to C.

First, as shown in FIG. 3A, an N ⁺ buried region 1 is formed on a P-type semiconductor substrate 11 by diffusion or ion implantation.
2 is formed, and subsequently, an N-type epitaxial region 13 is deposited, and then a P-type insulating diffusion layer 19 is formed by diffusion or ion implantation.
And a deep P-type diffusion layer 20 are simultaneously formed. In the present invention, the P-type insulating diffusion layer region 19 and the deep P-type diffusion layer
20 and can also be formed separately.

The formation of the P-type insulating diffusion layer 19 is performed, for example, by the following steps: 1.
In the case of the 4 μm N-type epitaxial layer region 13, boron ion implantation is divided into three times according to the ion implantation method, and each of 5 × 10 ¹² to 1 is performed at an energy of 700 keV, 300 keV, and 100 keV.
A ^dose of × 10 ¹³ cm ^-2 is applied, and then annealing is performed at 1000 ° C. for about 60 minutes to activate and diffuse boron.

Next, as shown in FIG. 3B, the emitter P and the emitter P are implanted into the emitter region and the collector region by ion implantation.
^{A +} diffusion layer 14 and a collector P ⁺ diffusion layer 15 are formed. In the present invention, it is preferable to form the P ⁺ diffusion layers 14 and 15 simultaneously. The deep P formed in the previous step (step A in FIG. 3)
The reason why the type diffusion layer 20 is arranged farther from the emitter than the collector P ⁺ diffusion layer 15 is to facilitate determination of the base width.

Next, as shown in FIG. 3C, a base contact N-type diffusion layer 16 is formed in the base contact region, and an interlayer film 21 is deposited on the substrate surface. Then, the interlayer film 21
A contact hole is opened in the metal electrode (emitter electrode 2).
2. By forming the collector electrode 23 and the base electrode 24), the bipolar transistor having the structure shown in FIGS. 1 and 2 is obtained.

(Embodiment 2) FIG. 4 is a sectional view of a bipolar transistor showing a second embodiment (Embodiment 2) of the present invention.

The bipolar transistor 30 of the second embodiment
As shown in FIG. 4, an N ⁺ -type buried region 32, a P ^{+ -type} buried region 37 and an N-type epitaxial region 3 are formed on a P-type semiconductor substrate 31.
3 is formed, and a P-type insulating diffusion layer 38 is formed in an insulating region for electrical insulation of the semiconductor element so as to reach the P ⁺ -type buried region 37.

The epitaxial region 33 between the insulating regions of the P-type insulating diffusion layer 38 has a deep P-type diffusion reaching the emitter P ⁺ diffusion layer 34, the collector P ⁺ diffusion layer 35, and the N ⁺ -type buried region 32. Layers 40 are each formed. In the epitaxial region 33, a base contact N-type diffusion layer 36 is formed. Further, the emitter electrode 42, which is electrically connected to each of the diffusion layers 34, 35, 36 through the contact hole of the interlayer film 41,
A collector electrode 43 and a base electrode 44 are formed.

The deep P-type diffusion layer 40 reaching the N ⁺ -type buried region 32 in the bipolar transistor 30 according to the second embodiment will be described. The depth of the deep P-type diffusion layer 40 depends on the concentration of the epitaxial region 33. : 10 ¹⁵ -10 ¹⁶ cm ^-3 , thickness: 1.4
In the case of μm, if 0.7 μm or more, solid concentration: 10 ¹⁸ to 10 ²⁰ c
It can be in contact with the m ⁻³ N ⁺ type buried region 32 and reaches the P ⁺ buried region 37.

In order to form the deep P-type diffusion layer 40, for example, if an ion implantation method is used, an energy of 300 keV is required.
Two ion implantations of 100 keV resulted in 3 × 10 ¹² -1
Preferably, boron is implanted at a dose of × 10 ¹³ and heat treatment is performed.

In the second embodiment, as shown in FIG. 4, the collector P ⁺ diffusion layer 35 in the collector region is included in the deep P-type diffusion layer 40, which reduces the manufacturing variation of the base width. acceptable, base - by increasing the scan width, although a slight decrease in H _FE is observed, the effect of improving the characteristics of the transistor is obvious.

[0034]

As described above in detail, according to the present invention, the collector P-type diffusion layer reaching the N-type buried region is provided in the collector region on the N-type epitaxial region having the N-type buried region.
It is formed so as to surround the emitter, and
Has a structure in which an emitter P-type diffusion layer serving as an injection source of holes is formed, thereby preventing the hole from diffusing toward the substrate due to a built-in potential between the N-type buried region and the N-type epitaxial region. Effect.

Further, in the present invention, since the collector P-type diffusion layer in the collector region surrounds the emitter region while being in contact with the N-type buried region, the hole injected from the emitter into the base does not occurs efficiently collected effect without diffusing to the outer side, on which improves 20-30% compared to H _FE is conventional, yet that the decrease in H _FE at high current can be suppressed Significant effects occur.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view (cross-sectional view taken along line AA in FIG. 2) of a bipolar transistor according to a first embodiment (embodiment 1) of the present invention.

FIG. 2 is a plan view of the bipolar transistor of FIG.

FIG. 3 is a diagram for explaining a method of manufacturing the bipolar transistor according to the first embodiment (Embodiment 1) of the present invention,
FIG. 4 is a sectional view in the order of steps including steps A to C.

FIG. 4 is a sectional view of a bipolar transistor according to a second embodiment (Embodiment 2) of the present invention.

FIG. 5 is a cross-sectional view of a conventional lateral PNP transistor.

FIG. 6 is a cross-sectional view of a lateral PNP transistor as another conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 Bipolar transistor 11 P-type semiconductor substrate 12 N ⁺ buried region 13 N-type epitaxial region 14 Emitter P ⁺ diffusion layer 15 Collector P ⁺ diffusion layer 16 Base contact N-type diffusion layer 19 P-type insulating diffusion layer 20 P Diffusion layer 21 Interlayer film 22 Emitter electrode 23 Collector electrode 24 Base electrode 30 Bipolar transistor 31 P-type semiconductor substrate 32 N ⁺ type buried region 33 N-type epitaxial region 34 Emitter P ⁺ diffusion layer 35 Collector P ⁺ diffusion Layer 36 Base contact N-type diffusion layer 37 P ⁺ buried region 38 P-type insulating diffusion layer 40 Deep P-type diffusion layer 41 Interlayer film 42 Emitter electrode 43 Collector electrode 44 Base electrode 51 P-type silicon substrate 52 N ⁺ -type buried region 53 N-type epitaxial region 54 P ⁺ emitter region 55 P ⁺ collector region 56 N ⁺ - scan the contact region 57 lower surface P ⁺ isolation region 58 top P ⁺ isolation region 59 protective layer 60 emitter electrode 61 collector electrode 62 base - scan electrode 63 P ⁺ diffusion layer 64 P ⁺ buried layer region

Claims (4)

(57) [Claims] A buried region of the opposite conductivity type and an epitaxial region of the opposite conductivity type are provided on a semiconductor substrate of one conductivity type, and the epitaxial region has an emitter region of one conductivity type and a reverse conductivity type.
Conductivity type base region and is formed so as to surround said while in contact with the buried region <br/> the emitter region and the base region
Bipolar transistor having a collector region of one conductivity type
In the transistor, the collector region is formed with the buried region.
A first diffusion layer in contact with, and a portion facing the emitter layer
Formed at a higher impurity concentration than the first diffusion layer.
And a second diffusion layer not in contact with the buried region . 2. The method according to claim 1, wherein the second diffusion layer is provided in the first diffusion layer.
The bipolar transistor according to claim 1, wherein the bipolar transistor is included. 3. An opposite conductivity type semiconductor substrate on one conductivity type semiconductor substrate.
Having a buried region and a reverse conductivity type epitaxial region;
In the epitaxial region, one conductivity type emitter region and reverse
A conductive type base region and the buried region,
An emitter region and the base region are formed to surround the base region.
Bipolar transistor having a collector region of one conductivity type
In the method for manufacturing a transistor, the buried region is formed in the collector region.
Forming a first diffusion layer of one conductivity type in contact with the embedded region;
In the part facing the emitter layer, the first diffusion layer is also not formed.
Pure substance concentration is high, one conductivity type not in contact with the buried region
Forming a second diffusion layer; and a one-conductivity type emitter region.
Forming a region simultaneously or separately with the second diffusion layer
Of a bipolar transistor characterized by having
Production method. 4. The method according to claim 1, wherein the second diffusion layer is used as the first diffusion layer.
The method for manufacturing a bipolar transistor according to claim 3, wherein the bipolar transistor is formed so as to be included .