JP2888652B2 - Semiconductor integrated circuit device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to an improvement of a hetero-bipolar transistor.

[0002]

2. Description of the Related Art FIG. 6 is a sectional view showing a conventional semiconductor integrated circuit device, in particular, an NPN transistor thereof. In the figure, reference numeral 1 denotes a P-type semiconductor substrate on which an N-type epitaxial layer 3 is formed. An N-type buried layer 2 is formed at the bottom of the N-type epitaxial layer 3, and is connected to an N-type collector wall layer 4 penetrating the N-type epitaxial layer 3. An intrinsic base layer 8a is formed at the center of the surface of the N-type epitaxial layer 3 and is connected to an external base layer 8b formed on the side of the N-type epitaxial layer.
Reference numeral 5 denotes a field oxide film formed so as to surround the N-type layer, and a channel cut layer 6 is formed below the field oxide film 5. Reference numeral 15 denotes a collector electrode formed on the N-type buried layer 2 and the N-type collector wall layer 4, and reference numeral 13 denotes a base electrode formed on the external base layer 8b. Is formed in a two-layer structure. Reference numeral 9 denotes an N-type impurity-doped SiC layer formed on the intrinsic base layer 8a, on which an emitter electrode 14 composed of a barrier metal 12 and an aluminum wiring 11 is formed. 7a and 7b are interlayer oxide films that insulate the electrodes from each other;
Reference numeral 10 denotes a silicide film formed on a junction surface between the barrier metal 12 and the semiconductor layer.

Next, referring to FIGS. 4 (a) to 4 (c), FIGS. 5 (a) to 5 (c), and FIG. 6, manufacturing of a hetero-bipolar transistor of a semiconductor integrated circuit device by an isoplanar technique. The method will be described. First, an N-type semiconductor substrate 1
Buried layer 2 is formed, and N-type epitaxial layer 3 is formed thereon.
Is grown (FIG. 4 (a)). Next, silicon etching is performed to separate the elements, and the channel cut layer 6 is made of B ⁺
After being formed by (boron) implantation and heat treatment, a field oxide film 5 is formed (FIG. 4B). Then, the N-type collector wall layer 4, the intrinsic base layer 8a, the external base layer 8
b is formed by ion implantation of P ⁺ (phosphorus) and B ⁺ (boron) and heat treatment, respectively (FIG. 4C). Then, an interlayer oxide film 7a is formed by CVD (Chemical Vapor Deposition), an emitter hole is formed on the intrinsic base layer 8a, and SiC 9 doped with an N-type impurity (for example, P ⁺ (phosphorus)) is formed thereon. Epitaxial growth (heteroepitaxy) (FIG. 5 (a)). Thereafter, the SiC 9 doped with the N-type impurity is patterned by RIE (Reactive Ion Etching), and a collector contact hole and an external base contact hole are formed on the N-type collector wall layer 4 and the external base 8b, respectively (FIG. b)). Then, a silicide film 10 (for example, TiSi ₂ ) is selectively formed, and an interlayer oxide film 7b is formed by CVD (FIG. 5).
(c)). Further, the contact holes are opened again by dry etching of the oxide film, and the base electrode 1 is formed by forming and patterning the barrier metal 12 and the aluminum wiring 11.
3. An emitter electrode 14 and a collector electrode 15 are formed (FIG. 6).

Next, the hetero bipolar will be described. In this conventional example, SiC as a hetero material is used for the emitter. This SiC has a larger band gap than Si as a semiconductor substrate material, and thus has a wide band gap emitter (w
ide bandgap emitter). With this structure, the bandgap energy of the emitter layer becomes larger than that of the base layer, the reverse injection of minority carriers from the base to the emitter can be suppressed, and the emitter injection efficiency, that is, the current gain can be increased.

That is, the emitter injection efficiency r is represented by the following equation 1, where In is an electron current injected from the emitter to the base, Ip is a hole current injected from the base to the emitter, and Is is an emitter-base depletion layer. Where Ie is the emitter current (In + Ip + Is).
Therefore, by increasing the band gap energy, the hole current Ip injected from the base to the emitter can be increased.
And the emitter injection efficiency r can be increased.

[0006]

(Equation 1)

The current gain β is expressed by the following equation (2), where Ir is the recombination current in the base, Ic is the collector current (In-Ir), and Ib is the base current (Ip + Ir + I
s). Therefore, by increasing the band gap energy, the hole current Ip injected from the base to the emitter can be reduced, and the current gain β can be increased.

[0008]

(Equation 2)

Therefore, it is possible to increase the impurity concentration of the base while suppressing a decrease in current gain accompanying the increase in the impurity concentration, and to reduce the base resistance. In such an apparatus, even if the base width is small, the base resistance can be reduced, and the speed can be increased.

[0010]

Since the conventional semiconductor integrated circuit device is configured as described above, the N-type epitaxial layer 3 partially functioning as a collector and the N-type buried layer 2 for extracting a collector current are provided. Of the collector-base junction capacitance C _TC , that is, the junction between the intrinsic and external base layers 8 a and 8 b and the N-type epitaxial layer 3. Capacitance and collector-substrate junction capacitance C
There is a problem that _TS , that is, the junction capacitance between the N-type buried layer 2 and the P-type semiconductor substrate 1 increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and it is possible to reduce a parasitic junction capacitance in a transistor by reducing unnecessary portions as a transistor operation, thereby achieving a higher-speed operation. It is an object of the present invention to obtain a possible hetero bipolar semiconductor integrated circuit device.

[0012]

A semiconductor integrated circuit device according to the present invention comprises a plurality of semiconductor layers formed on a semiconductor substrate.
With a planar bipolar transistor element
In the semiconductor integrated circuit device, the transistor element
A portion immediately below a field oxide film for separation, and the portion
The external base region of the above transistor element, which is continuous every minute
Into the area directly below by high-energy oxygen injection .
An oxide film formed by oxidizing a material is formed .

Further, this invention, in the semiconductor integrated circuit device, the upper Quito transistor element, the emitter territory
Area, which is different from the semiconductor material composing the base
Using a semiconductor material with a large
This is a hetero bipolar transistor .

Further , according to the present invention , a semiconductor integrated circuit is manufactured.
The fabrication method involves forming a plurality of semiconductor layers on a semiconductor substrate and forming
Element type forming a Rainer type bipolar transistor element
Method of manufacturing semiconductor integrated circuit device having forming process
Thus, the element forming step includes the step of forming a second conductive layer on the surface of the first conductive type substrate.
An electric buried layer, and a first buried layer on both sides of the second conductive type buried layer.
Conductive type channel cut layer and the above-mentioned second conductive type embedding
Layer and the first conductivity type channel cut layer.
After forming each of the epitaxial layers,
A field oxide film for element isolation is formed
Part immediately below the part, and the subsequent part
In the process, the external base region of the transistor element is formed.
Oxygen with high energy into the area directly below
And the high-energy oxygen implanted portion
The material is oxidized by heat treatment to oxidize the part
Forming a film, and the second conductivity type epitaxial layer
A mask is formed in the upper area other than the area for element isolation
And a field for element isolation using this as a mask.
Forming a doped oxide film, and the second conductivity type epitaxy.
A collector wall layer of the second conductivity type as part of the
Intrinsic base on part of the surface of the second conductivity type epitaxial layer
Layer and the intrinsic base of the second conductivity type epitaxial layer.
Injecting oxygen with high energy continuous to the gas layer
An external base layer is formed directly above the oxide film.
And the step of performing

[0015]

[0016]

According to the present invention, a plurality of semiconductor devices are provided on a semiconductor substrate.
Planar type bipolar transistor formed with conductive layer
In a semiconductor integrated circuit device having a
Immediately below the field oxide film to separate transistor elements
Forming an oxide film formed by oxidizing the material of each part using the SOI (Silicon On Insulator) technique by the high energy oxygen implantation of the transistor, which is continuous with the part;
Therefore, the parasitic junction capacitance between the semiconductor layers included in the transistor and between the semiconductor layer and the semiconductor substrate can be reduced, and the operation of the transistor can be increased.

[0017] to the emitter area of or transistor element,
Unlike the semiconductor material forming the base region, a semiconductor material having a large bandgap energy is used, so that the base resistance can be reduced even if the base width is narrow. As a result, a hetero-bipolar type semiconductor capable of high-speed operation can be obtained. An integrated circuit device can be obtained. Also in the present invention
Is to form multiple planar semiconductor layers on a semiconductor substrate.
Forming Step of Forming Type Bipolar Transistor Device
The method for manufacturing a semiconductor integrated circuit device having
In the element forming step, the first conductivity type substrate surface is filled with the second conductivity type.
Embedded layer and first conductive type chips on both sides of the second conductive type buried layer.
On the channel cut layer and the buried layer of the second conductivity type, and
And a second conductivity type epitaxial layer on the first conductivity type channel cut layer.
After the formation of each taxi layer, the device
In the area where the field oxide film for separation is formed
The part immediately below and the part that follows it,
Part where the external base region of the transistor element is formed
Of oxygen injection with high energy into the area directly below
And heat the material in the part where oxygen was injected with this high energy.
Oxidation by performing treatment to form an oxide film on the part
Performing the steps of:
A mask is formed in a region other than the region for
A field oxide film for device isolation using a mask
Forming a second conductive type epitaxial layer;
Part of the second conductivity type collector wall layer, the second conductivity type
An intrinsic base layer on part of the surface of the epitaxial layer,
Continuing with the intrinsic base layer of the second conductivity type epitaxial layer
Of the oxide film formed by injecting oxygen with high energy
A step of forming an external base layer on the portion directly above
To reduce the junction capacitance between collector and base
And obtain a semiconductor integrated circuit device that can operate at high speed.
Can be.

[0018]

FIG. 3 is a sectional view showing a semiconductor integrated circuit device according to one embodiment of the present invention. 6, the same reference numerals as those in FIG. 6 denote the same or corresponding parts, and reference numeral 16 denotes an oxide film formed by implanting high-energy oxygen, a part of which is located below the external base layer 8b.

Next, the manufacturing method will be described with reference to FIGS. 1 (a) to 1 (c).
2 (a) to 2 (c) and FIG. First, an N-type buried layer 2 and a channel cut layer 6 are formed on a P-type semiconductor substrate 1, and an N-type epitaxial layer 3 is grown thereon (FIG. 1 (a)). Next, SOI (Silicon On Insu
Using a technique, that is, using a SiO ₂ mask, high-energy (MeV) oxygen is implanted, and heat treatment is performed to form an oxide film 16 (FIG. 1B). Then, a field oxide film 5 is formed using the nitride film as a mask.
(c)). After that, the N-type collector wall layer 4, the intrinsic base layer 8a, and the external base layer 8b are respectively changed to P ⁺ (phosphorus),
It is formed by ion implantation of B ⁺ (boron) and heat treatment (FIG. 2A). Then, an interlayer oxide film 7a is formed by CVD, an emitter hole is opened, and SiC9 doped with an N-type impurity (for example, P ⁺ (phosphorus)) is epitaxially grown thereon (FIG. 2B). Thereafter, the SiC 9 doped with the N-type impurity is patterned by RIE, and a collector contact hole and an external base contact hole are opened. Then, the silicide film 10 (for example, TiS
i ₂₎ selectively formed, it is formed by CVD interlayer oxide film 7b (FIG. 2 (c)). Further, a contact hole is formed by dry etching of an oxide film, and a base electrode 13, an emitter electrode 14, and a collector electrode 15 are formed by the barrier metal 12 and the aluminum wiring 11 (FIG. 3).

As described above, in this embodiment, the external base layer 8
The b lower semiconductor region is oxidized by high-energy oxygen implant, the N-type buried layer 2 and N-type epitaxial layer 3, since the reducing unnecessary portions transistor operation, the collector-base junction capacitance C _TC and The collector-substrate junction capacitance _CTS can be reduced, and higher-speed transistor operation can be realized.

Further, because of the use of Si C heteroatoms material to the emitter, a band gap energy of the emitter layer is greater than that of the base, suppressing reverse injection of minority carriers from the base to the emitter, the emitter injection efficiency, i.e., The current gain can be increased. Significantly raised the impurity concentration of the base without considering the reduction in this was because current gain, ie, narrow base width can be reduced base resistance, higher speed operation of the hetero bipolar capable semiconductor integrated circuit A device can be obtained.

In the above embodiment, the case where the semiconductor region below the external base layer 8b is oxidized by implanting high-energy oxygen has been described. However, the region oxidized by implanting oxygen is not limited to this. If the region is unnecessary, the effect of reducing the junction capacitance can be obtained.

[0023]

As described above, according to the semiconductor integrated circuit device of the present invention , a plurality of semiconductor layers are formed on a semiconductor substrate.
With a planar bipolar transistor element
In the semiconductor integrated circuit device obtained above,
Immediately below the field oxide film to separate the electrons, and
An external base of the transistor element continuous with the portion
SOI by high-energy oxygen implantation just below the region
The material of the respective portion with the (Silicon On Insulator) technology
Since an oxidized oxide film was formed, the collector base
This has the effect that the inter- junction capacitance C _TC can be reduced, and a hetero bipolar semiconductor integrated circuit device capable of operating at higher speed can be obtained. Also, the transistor element is
What is the semiconductor material constituting the base region in the emitter region?
Different semiconductor materials with large band gap energy
Since it is a hetero bipolar transistor using
Even if the base width is narrow, the base resistance can be reduced.
As a result, a hetero-bipolar semiconductor that can operate at high speed
There is an effect that a body integrated circuit device can be obtained.

Further, according to the semiconductor integrated circuit device of the present invention,
According to the manufacturing method, a plurality of semiconductor layers are formed on a semiconductor substrate.
To form a planar bipolar transistor device.
For manufacturing semiconductor integrated circuit device having element forming step
In the above element forming step, the first conductive type substrate surface
Buried layer of second conductivity type, both sides of buried layer of second conductivity type
The first conductivity type channel cut layer and the second conductivity type
On the embedding layer and the channel cut layer of the first conductivity type.
After forming each of the second conductivity type epitaxial layers,
A field oxide film is formed for device isolation in a later process.
The part immediately below the part to be formed and the part
The external base region of the transistor element in a later step.
In the part directly below the part where
Oxygen injection process and oxygen injection with this high energy
The material in the part is oxidized by heat treatment,
Forming an oxide film separately, and the second conductivity type epitaxy.
Mask other than the area for element isolation on the char layer
Is formed, and a mask for element isolation is formed using this as a mask.
Forming a field oxide film;
Second conductivity type collector wall layer on part of the taxi layer
And a part of the surface of the second conductivity type epitaxial layer.
Base layer and the second conductivity type epitaxial layer
Inject oxygen with high energy continuous to the intrinsic base layer
The external base layer directly above the oxide film
Since being and forming, it is possible to reduce the collector-base junction capacitance C _TC, thereby an effect that a semi-conductor integrated circuit device capable of high speed operation is obtained.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a part of a method of manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention.

FIG. 2 is a sectional view showing a part of a method of manufacturing a semiconductor integrated circuit device according to one embodiment of the present invention.

FIG. 3 is a sectional view showing a semiconductor integrated circuit device according to one embodiment of the present invention.

FIG. 4 is a sectional view showing a part of a conventional method for manufacturing a semiconductor integrated circuit device.

FIG. 5 is a cross-sectional view showing a part of a conventional method for manufacturing a semiconductor integrated circuit device.

FIG. 6 is a sectional view showing a conventional semiconductor integrated circuit device.

[Explanation of symbols]

Reference Signs List 1 P-type semiconductor substrate 2 N-type buried layer 3 N-type epitaxial layer 4 N-type collector wall layer 5 Field oxide film 6 Channel cut layer 7 a, 7 b Interlayer oxide film 8 a Intrinsic base layer 8 b External base layer 9 N-type impurity doped SiC 10 silicide film 11 aluminum wiring 12 barrier metal 13 base electrode 14 emitter electrode 15 collector electrode 16 oxide film formed by high energy oxygen implantation

Continuation of front page (56) References JP-A-62-160760 (JP, A) JP-A-1-143260 (JP, A) JP-A-4-33343 (JP, A) (58) Fields investigated (Int) .Cl. ⁶ , DB name) H01L 21/33-21/331 H01L 29/68-29/737 H01L 21/70-21/74 H01L 21/76-21/765 H01L 21/77

Claims (3)

(57) [Claims] In a semiconductor integrated circuit device having a planar type bipolar transistor element formed by forming a plurality of semiconductor layers on a semiconductor substrate, a field oxide for isolating the transistor element is provided.
A portion immediately below the membrane and the above-mentioned transistor connected to the portion;
A high-energy acid is placed just under the external base region of the
An oxide film formed by oxidizing the material of each part by element implantation is formed.
A semiconductor integrated circuit device characterized by being formed . 2. The semiconductor device according to claim 1, wherein said transistor element has an emitter region.
The band that is different from the semiconductor material that constitutes the base region
Using a semiconductor material with a large gap energy,
2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is a bipolar transistor . 3. A method for forming a plurality of semiconductor layers on a semiconductor substrate.
To form a planar bipolar transistor device
In a method of manufacturing a semiconductor integrated circuit device having a
And forming the second conductive type buried layer on the surface of the first conductive type substrate.
A first conductivity type channel cut layer on both sides of the electric type buried layer,
And the buried layer of the second conductivity type, and the first conductivity type
A second conductivity type epitaxial layer is formed on the channel cut layer.
After each formation, a field oxide film for device isolation in a later process is formed.
The part immediately below the part to be formed and the part
The external base region of the transistor element in a later step.
In the part directly below the part where
Oxygen implantation process and heat treatment of the material in the high energy oxygen implanted area
To form an oxide film on the portion
Process and device isolation on the second conductivity type epitaxial layer
A mask other than the area for
Step of forming field oxide film for performing element isolation
And a part of the second conductivity type epitaxial layer
Lecter wall layer and the second conductivity type epitaxial layer
An intrinsic base layer on a part of the surface of the
High energy continuous to the intrinsic base layer of the xial layer
An external barrier is placed just above the oxide film,
And a step of forming each of the source layers.
Of manufacturing a semiconductor integrated circuit device.