JP3778122B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a structure of a semiconductor device in which a lateral bipolar transistor is mounted on a semiconductor substrate and a manufacturing method thereof.
[0002]
[Prior art]
In recent years, many proposals regarding a semiconductor device having a lateral bipolar transistor mounted on a semiconductor substrate have been made, for example, those described in Japanese Patent No. 2654536. This conventional example will be described below with reference to the drawings. FIG. 8A to FIG. 9B are cross-sectional views showing manufacturing steps of the first conventional lateral PNP bipolar transistor. Note that a description of the resist film removal step is omitted. In the conventional example, a horizontal PNP bipolar transistor and a vertical NPN bipolar transistor are formed simultaneously, but the description of the vertical NPN bipolar transistor is omitted.
[0003]
First, as shown in FIG. 8A, arsenic is implanted into the bipolar transistor formation region on the semiconductor substrate 400 and heat treatment is performed to form an N-type buried layer 401. Further, an N type epitaxial layer 402 serving as a base layer is formed. Thereafter, as shown in FIG. 8B, after forming a field oxide film 403, photolithography is performed to selectively form a base contact layer 404 by an ion implantation method.
[0004]
Next, as shown in FIG. 9A, photolithography is performed, and an emitter layer 405 and a collector layer 406 are selectively formed by an ion implantation method. Finally, as shown in FIG. 9B, when the interlayer insulating film 407 and the metal electrode 408 are formed after annealing, the semiconductor device is completed.
[0005]
As a conventional example, there is one described in JP-A-2000-58664. This conventional example will be described below with reference to the drawings. FIG. 10 is a cross-sectional view showing a horizontal PNP bipolar transistor of the second conventional example. Here, only the lateral PNP bipolar transistor will be described.
[0006]
As shown in FIG. 10, the emitter layer 409, the collector layer 410, and the base layer 411 of the lateral PNP bipolar transistor are each formed on the buried oxide film 412 of the SOI substrate.
[0007]
[Problems to be solved by the invention]
However, the conventional example has a problem that it is difficult to achieve both high hFE and low base resistance.
[0008]
First, in the first conventional example, carriers injected into the base layer from the side surface of the emitter layer reach the collector layer, but some of the carriers injected into the base layer from the lower surface of the emitter layer reach the collector layer. Without recombination in the base layer. Therefore, there is a problem that the base transportation efficiency is lowered and high hFE cannot be obtained.
[0009]
In the second conventional example, since the lower surface of the emitter layer is in contact with the insulating film, carriers are not injected into the base layer from the lower surface of the emitter layer, but it is difficult to make a base contact. is there. The base contact layer takes the potential of the base layer, but since the lower surface of the base layer and the lower surface of the collector layer are in contact with the insulating film, the base contact is passed through the lower portion of the collector layer as in the first conventional example. Can not take. Therefore, in the layout viewed from the upper surface of the semiconductor substrate, it is necessary that the collector layer is not ring-shaped but partly cut into a “C” shape. In this case, carriers injected from the side surface of the emitter layer corresponding to the cut portion of the collector layer cannot reach the collector layer, and the base transport efficiency is lowered. That is, there is a problem that high hFE cannot be obtained. If the cut portion of the collector layer is reduced to prevent this, the parasitic resistance to the base contact layer increases. That is, there is a problem that the base resistance becomes high.
[0010]
As described above, the conventional lateral PNP bipolar transistor has a problem that it is difficult to achieve both high hFE and low base resistance. In addition, the SOI substrate is generally expensive, and there is a problem that the manufacturing cost of the semiconductor device increases.
[0011]
The present invention solves the above-described problems, and provides a semiconductor device having a lateral bipolar transistor mounted on a semiconductor substrate and an excellent semiconductor device capable of achieving both high hFE and low base resistance, and a method for manufacturing the same. The purpose is to do.
[0012]
[Means for Solving the Problems]
In order to achieve the above object, a semiconductor device according to the present invention is a semiconductor device having a lateral bipolar transistor on a semiconductor substrate, wherein an insulating film exists between the lower surface of the emitter layer and the base layer of the lateral bipolar transistor. In addition, the insulating film does not exist between the lower surface of the collector layer and the base layer, and is in direct contact.
[0013]
With this configuration, since the lower surface of the emitter layer is in contact with the insulating film, carriers are not injected into the base layer from the lower surface of the emitter layer. Therefore, the base transport efficiency is not lowered and high hFE can be obtained. In addition, since the insulating film does not exist between the lower surface of the collector layer and the base layer and is in direct contact, the base resistance does not increase. Therefore, both high hFE and low base resistance can be achieved.
[0014]
According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device having a lateral bipolar transistor on a semiconductor substrate, the second conductivity type embedding in a transistor formation region of the first conductivity type semiconductor substrate. Forming a layer, forming a second conductivity type epitaxial layer on the semiconductor substrate, selectively implanting oxygen ions into the emitter formation region, and then performing a heat treatment on the lower surface of the emitter formation region. A step of forming an oxide film; and a step of introducing an impurity of a first conductivity type into the emitter formation region to form an emitter layer in contact with the oxide film.
[0015]
With this configuration, an oxide film is selectively formed on the lower surface of the emitter layer by oxygen ion implantation, and the lower surface of the emitter layer and the base layer are blocked by the oxide film. For this reason, carriers are not injected into the base layer from the lower surface of the emitter layer. Therefore, the base transport efficiency is not lowered and high hFE can be obtained. Moreover, since there is no oxide film on the lower surface of the collector layer, the lower surface of the collector layer and the base layer are in direct contact with each other, so that the base resistance does not increase. Therefore, both high hFE and low base resistance can be achieved.
[0016]
The second method for manufacturing a semiconductor device according to the present invention is the method for manufacturing a semiconductor device having a lateral bipolar transistor on a semiconductor substrate, wherein the second conductivity type is embedded in the transistor formation region of the first conductivity type semiconductor substrate. Forming a layer; forming a second conductivity type first epitaxial layer on the semiconductor substrate; forming an insulating film on the first epitaxial layer; A step of leaving an insulating film, a step of forming a second conductive type second epitaxial layer on the first epitaxial layer so as to cover the insulating film, and an impurity of the first conductive type in the emitter forming region. And a step of forming an emitter layer in contact with the insulating film.
[0017]
With this configuration, an insulating film is formed in the emitter formation region, and an emitter layer is formed thereon by epitaxial growth, whereby the lower surface of the emitter layer and the base layer are blocked by this insulating film. For this reason, carriers are not injected into the base layer from the lower surface of the emitter layer. Therefore, the base transport efficiency is not lowered and high hFE can be obtained. In addition, since there is no insulating film on the lower surface of the collector layer, the lower surface of the collector layer and the base layer are in direct contact with each other, so that the base resistance does not increase. Therefore, both high hFE and low base resistance can be achieved.
[0018]
The third method for manufacturing a semiconductor device according to the present invention is the method for manufacturing a semiconductor device having a lateral bipolar transistor on a semiconductor substrate, wherein the second conductivity type is embedded in the transistor formation region of the first conductivity type semiconductor substrate. Forming a layer; forming a second conductivity type first epitaxial layer on the semiconductor substrate; and selectively opening a trench in the emitter formation region of the semiconductor substrate; The bottom surface of the trench is thicker than the side surface of the trench due to the step of introducing a two-conductivity type impurity, and thermal oxidation of the semiconductor substrate, and the accelerated oxidation of the second conductivity type impurity introduced into the bottom surface of the trench. Forming an oxide film, wet etching the oxide film, leaving the oxide film on the lower surface of the trench, and forming a side surface of the trench Removing the oxide film, performing epitaxial growth laterally from the side surface of the trench to form a second conductive type second epitaxial layer on the oxide film, and forming a second epitaxial layer on the second epitaxial layer. And introducing an impurity of one conductivity type to form an emitter layer in contact with the oxide film.
[0019]
With this configuration, an oxide film is formed only on the lower surface of the trench in the emitter formation region, and an emitter layer is formed in the trench by epitaxial growth thereon, whereby the lower surface of the emitter layer and the base layer are blocked by this oxide film. Yes. For this reason, carriers are not injected into the base layer from the lower surface of the emitter layer. Therefore, the base transport efficiency is not lowered and high hFE can be obtained. Further, since there is no insulating film on the lower surface of the collector layer, the lower surface of the collector layer and the base layer are in direct contact with each other, so that the base resistance does not increase. Therefore, both high hFE and low base resistance can be achieved.
[0020]
In the first, second, and third semiconductor device manufacturing methods, the semiconductor substrate is preferably a single crystal substrate and not an SOI substrate.
[0021]
With this configuration, an expensive SOI substrate is not used, so that the manufacturing cost of the semiconductor device can be suppressed.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0023]
(First embodiment)
First, the first embodiment will be described. FIG. 1A to FIG. 2B are cross-sectional views illustrating manufacturing steps of the semiconductor device according to the first embodiment. Note that the description of the resist film removal step is omitted unless otherwise specified.
[0024]
As shown in FIG. 1A, a resist film (not shown) is formed on a P-type semiconductor substrate 100 made of silicon single crystal whose principal surface is a (100) surface having a specific resistance of, for example, 10 to 15 Ω · cm. Using this, an N-type buried layer 101 is formed in the bipolar transistor formation region of the P-type semiconductor substrate 100, and after heat treatment, an N-type epitaxial layer 102 serving as a base layer is formed on the entire surface. Thereafter, as shown in FIG. 1B, a first oxide film 103 is formed on the entire surface, and then a resist film (not shown) is formed. Using this, a part of the first oxide film 103 is removed. To do. This portion is an emitter formation region, and an emitter layer is formed later.
[0025]
Next, as shown in FIG. 1C, oxygen ions are implanted using the first oxide film 103 as a mask, and further heat treatment is performed. As a result, the second oxide film 104 is formed below the region where the first oxide film 103 does not exist. Thereafter, as shown in FIG. 2A, after removing the first oxide film 103, a resist film (not shown) is formed, and by using this as a mask, ion implantation of P-type impurities is performed to form an emitter layer of the transistor. 105 and collector layer 106 are formed. As a result, the emitter layer 105 is in contact with the second oxide film 104. Further, a resist film (not shown) is formed, and using this as a mask, N-type impurity ions are implanted to form a base contact layer 107 of the transistor. Further, heat treatment is performed to activate the impurities.
[0026]
Finally, as shown in FIG. 2B, a third oxide film 108 is formed as an interlayer insulating film, and a part of the third oxide film 108 is etched using a resist film (not shown) as a mask. And a contact window is formed. Next, for example, an Al film is formed as a metal wiring by sputtering or the like, and then the Al film is etched using a resist film (not shown) as a mask to form an Al wiring 109, whereby the semiconductor device is completed. .
[0027]
As described above, according to this embodiment, an oxide film is selectively formed on the lower surface of the emitter layer by oxygen ion implantation, and the lower surface of the emitter layer and the base layer are blocked by the oxide film. For this reason, carriers are not injected into the base layer from the lower surface of the emitter layer. Therefore, the base transport efficiency is not lowered and high hFE can be obtained. Moreover, since there is no oxide film on the lower surface of the collector layer, the lower surface of the collector layer and the base layer are in direct contact. Accordingly, the base contact layer can be provided via the collector layer, and all the base layers around the emitter layer are connected to the base contact layer. Therefore, the base resistance does not increase. Therefore, both high hFE and low base resistance can be achieved.
[0028]
In addition, according to the present embodiment, since the buried oxide film is selectively formed without using an expensive SOI substrate, the manufacturing cost of the semiconductor device can be suppressed.
[0029]
(Second Embodiment)
Next, a second embodiment will be described. FIG. 3A to FIG. 4B are cross-sectional views illustrating manufacturing steps of the semiconductor device according to the second embodiment. Note that the description of the resist film removal step is omitted unless otherwise specified.
[0030]
As shown in FIG. 3A, a resist mask (not shown) is formed on a P-type semiconductor substrate 200 made of a silicon single crystal whose principal surface is a (100) surface having a specific resistance of, for example, 10 to 15 Ω · cm. Using this, an N-type buried layer 201 is formed in the bipolar transistor formation region of the P-type semiconductor substrate 200, and after heat treatment, first epitaxial growth is performed, and an N-type epitaxial layer 202 serving as a base layer is formed on the entire surface. Form. Thereafter, as shown in FIG. 3B, a first oxide film 203 is formed on the entire surface, and then a resist film (not shown) is formed. Using this, a part of the first oxide film 203 is left. Remove the rest. The portion where the first oxide film 203 is left is an emitter formation region, and an emitter layer is formed later.
[0031]
Next, as shown in FIG. 3C, second epitaxial growth is performed, and an N-type second epitaxial layer 204 is formed on the entire surface of the semiconductor substrate including on the first oxide film 203. Here, during epitaxial growth, the second epitaxial layer 204 is not directly formed on the first oxide film 203, but as the peripheral portion grows epitaxially, growth also occurs in the lateral direction, and the first oxide film 203 is formed on the first oxide film 203. However, the epitaxial layer protrudes. Finally, a second epitaxial layer 204 is formed so as to cover the first oxide film 203.
[0032]
Next, as shown in FIG. 4A, a resist film (not shown) is formed, and using this as a mask, ion implantation of P-type impurities is performed to form an emitter layer 205 and a collector layer 206 of the transistor. As a result, the emitter layer 205 is in contact with the first oxide film 203. Further, a resist film (not shown) is formed, and N-type impurity ions are implanted using the resist film as a mask to form a base contact layer 207 of the transistor. Further, heat treatment is performed to activate the impurities.
[0033]
Finally, as shown in FIG. 4B, a second oxide film 208 is formed as an interlayer insulating film, and a part of the second oxide film 208 is etched using a resist film (not shown) as a mask. And a contact window is formed. Next, for example, an Al film is formed as a metal wiring by sputtering or the like, and then the Al film is etched using a resist film (not shown) as a mask to form an Al wiring 209, thereby completing this semiconductor device. .
[0034]
As described above, according to the present embodiment, the first oxide film is selectively formed in the emitter formation region, and the second epitaxial growth is performed on the oxide film to form the emitter layer. Therefore, the lower surface of the emitter layer and the base layer are blocked by the oxide film. For this reason, carriers are not injected into the base layer from the lower surface of the emitter layer. Therefore, the base transport efficiency is not lowered and high hFE can be obtained. Moreover, since there is no oxide film on the lower surface of the collector layer, the lower surface of the collector layer and the base layer are in direct contact. Accordingly, the base contact layer can be provided via the collector layer, and all the base layers around the emitter layer are connected to the base contact layer. Therefore, the base resistance does not increase. Therefore, both high hFE and low base resistance can be achieved.
[0035]
In addition, according to the present embodiment, since the buried oxide film is selectively formed without using an expensive SOI substrate, the manufacturing cost of the semiconductor device can be suppressed. Furthermore, according to this embodiment, there is no need for oxygen ion implantation, which was necessary in the first embodiment. Since the oxygen ion implantation apparatus performs large dose implantation, a dedicated ion implantation apparatus is required. For this reason, there is a possibility that the manufacturing cost of the semiconductor device may increase. However, in the present embodiment, oxygen ion implantation is not necessary, and thus there is a further merit that the manufacturing cost of the semiconductor device can be suppressed.
[0036]
(Third embodiment)
Next, a third embodiment will be described. FIG. 5A to FIG. 7 are cross-sectional views showing manufacturing steps of the semiconductor device according to the third embodiment. Note that the description of the resist film removal step is omitted unless otherwise specified.
[0037]
As shown in FIG. 5A, a resist mask (not shown) is formed on a P-type semiconductor substrate 300 made of a silicon single crystal whose principal surface is a (100) plane having a specific resistance of, for example, 10 to 15 Ω · cm. Using this, an N-type buried layer 301 is formed in the bipolar transistor formation region of the P-type semiconductor substrate 300, and after heat treatment, first epitaxial growth is performed, and an N-type epitaxial layer 302 serving as a base layer is formed on the entire surface. Form.
[0038]
Next, as shown in FIG. 5B, a first oxide film 303 is formed on the entire surface, and then a resist film 304 is formed. Using this as a mask, one of the first oxide film 303 and the N-type epitaxial layer 302 is formed. Etching is performed to form a trench 305. The trench 305 is an emitter formation region, and an emitter layer is formed later. Further, ion implantation of N-type impurities is performed using the resist film 304 as a mask to form an N-type layer 306 under the trench 305.
[0039]
Next, as shown in FIG. 5C, after removing the resist film 304, thermal oxidation is performed to form a second oxide film 307 on the side surfaces and the lower surface of the trench 305. Here, since the N-type layer 306 exists on the lower surface of the trench 305, an oxide film having a thickness larger than that of the side surface is formed by the accelerated oxidation phenomenon.
[0040]
Next, as shown in FIG. 6A, the second oxide film 307 on the side surface of the trench 305 is removed by wet etching. At this time, since the second oxide film 307 on the lower surface of the trench 305 is thicker than the second oxide film 307 on the side surface, it remains without being removed. As a result, the second oxide film 307 remains only on the lower surface of the trench 305. Note that the first oxide film 303 is sufficiently thick, so that the first oxide film 303 remains even after wet etching.
[0041]
Next, as shown in FIG. 6B, second epitaxial growth is performed to form a P-type second epitaxial layer 308 on the second oxide film 307. Here, at the time of epitaxial growth, the second epitaxial layer 308 is not directly formed on the first oxide film 303 and the second oxide film 307, but silicon is exposed on the side surface of the trench 305, and the lateral direction extends from here. Epitaxial growth is performed, and an epitaxial layer protrudes onto the second oxide film 307 as well. Finally, the second epitaxial layer 308 is formed on the second oxide film 307.
[0042]
Next, as shown in FIG. 6C, after removing the first oxide film 303, a resist film (not shown) is formed, and using this as a mask, ion implantation of P-type impurities is performed, and the emitter of the transistor is formed. Layer 309 and collector layer 310 are formed. As a result, the emitter layer 309 is in contact with the second oxide film 307. Further, a resist film (not shown) is formed, and using this as a mask, N-type impurity ions are implanted to form a base contact layer 311 of the transistor. Further, heat treatment is performed to activate the impurities.
[0043]
Finally, as shown in FIG. 7, a third oxide film 312 is formed as an interlayer insulating film, and further, a part of the third oxide film 312 is etched using a resist film (not shown) as a mask. Form a window. Next, for example, an Al film is formed as a metal wiring by sputtering or the like, and then the Al film is etched using a resist film (not shown) as a mask to form an Al wiring 313, thereby completing the semiconductor device. .
[0044]
As described above, according to the present embodiment, no oxide film remains on the side surface of the trench in the emitter formation region, and the oxide film remains only on the lower surface. Thereafter, the second epitaxial growth is performed to fill the trench and form an emitter layer. Therefore, the lower surface of the emitter layer and the base layer are blocked by the oxide film. For this reason, carriers are not injected into the base layer from the lower surface of the emitter layer. Therefore, the base transport efficiency is not lowered and high hFE can be obtained. Further, since no oxide film exists on the lower surface of the collector layer, the lower surface of the collector layer and the base layer are in direct contact. Accordingly, the base contact layer can be provided via the collector layer, and all the base layers around the emitter layer are connected to the base contact layer. Therefore, the base resistance does not increase. Therefore, both high hFE and low base resistance can be achieved.
[0045]
In addition, according to the present embodiment, since the buried oxide film is selectively formed without using an expensive SOI substrate, the manufacturing cost of the semiconductor device can be suppressed. Furthermore, according to this embodiment, there is no need for oxygen ion implantation, which was necessary in the first embodiment. Since the oxygen ion implantation apparatus performs large dose implantation, a dedicated ion implantation apparatus is required. For this reason, there is a possibility that the manufacturing cost of the semiconductor device may increase. However, in the present embodiment, oxygen ion implantation is not necessary, and thus there is a further merit that the manufacturing cost of the semiconductor device can be suppressed.
[0046]
Furthermore, according to the present embodiment, hFE of a parasitic PNP transistor having the P-type semiconductor substrate 300 as a collector layer can be reduced. The base layer of the parasitic PNP transistor is the same as the base layer of the original PNP transistor, but current flows in the vertical direction. Here, in the present embodiment, since the N-type layer 306 is present in the base layer, carriers flowing through the base layer recombine and disappear, making it difficult to reach the collector layer. That is, there is a further merit that hFE of the parasitic PNP transistor can be reduced.
[0047]
(Other embodiments)
In the first, second, and third embodiments, the lateral PNP bipolar transistor has been described as an example among the bipolar transistors, but this may be a lateral NPN bipolar transistor.
[0048]
In the second embodiment, the first oxide film 203 may be made of other materials as long as it is an insulating film such as a nitride film.
[0049]
In the third embodiment, the second epitaxial growth is performed to form the P-type second epitaxial layer. However, this may be an N-type second epitaxial layer.
[0050]
【The invention's effect】
As described above, according to the present invention, since the lower surface of the emitter layer is in contact with the insulating film, carriers are not injected into the base layer from the lower surface of the emitter layer. Therefore, the base transport efficiency is not lowered and high hFE can be obtained. In addition, since there is no insulating film between the lower surface of the collector layer and the base layer and is in direct contact, the base contact layer can be provided via the lower surface of the collector layer. In this way, since all the base layers around the emitter layer are connected to the base contact layer, the base resistance does not increase. Therefore, it is possible to form an excellent semiconductor device that can achieve both high hFE and low base resistance.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a manufacturing process of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view showing a manufacturing process of a semiconductor device according to a first embodiment of the present invention. Sectional drawing which shows the manufacturing process of the semiconductor device in 2nd Embodiment of this invention FIG. 4 is sectional drawing which shows the manufacturing process of the semiconductor device in 2nd Embodiment of this invention FIG. 5 is 3rd Embodiment of this invention FIG. 6 is a cross-sectional view showing a semiconductor device manufacturing process in the third embodiment of the present invention. FIG. 7 is a cross-sectional view showing a semiconductor device manufacturing process in the third embodiment of the present invention. FIG. 8 is a cross-sectional view showing a manufacturing process of a semiconductor device of a first conventional example. FIG. 9 is a cross-sectional view showing a manufacturing process of a semiconductor device of a first conventional example. Sectional view of an example semiconductor device [Explanation of symbols]
100, 200, 300, 400 P-type semiconductor substrate 101, 201, 301, 401 N-type buried layer 102, 202, 302, 402 N-type epitaxial layer 103, 203, 303 First oxide film 104, 208, 307 Second Oxide films 105, 205, 309, 405, 409 Emitter layers 106, 206, 310, 406, 410 Collector layers 107, 207, 311, 404 Base contact layers 108, 312 Third oxide films 109, 209, 313 Al wiring 204 Second epitaxial layer 304 Resist film 305 Trench 306 N-type layer 308 Second epitaxial layer 403 Field oxide film 407 Interlayer insulating film 408 Metal electrode 411 Base layer 412 Embedded oxide film

Claims (2)

In a method for manufacturing a semiconductor device having a lateral bipolar transistor on a semiconductor substrate,
Forming a second conductivity type buried layer in a transistor formation region of the first conductivity type semiconductor substrate;
Forming a second conductivity type first epitaxial layer on the semiconductor substrate;
Selectively opening a trench in the emitter formation region of the first epitaxial layer , and introducing a second conductivity type impurity into the lower surface of the trench;
Thermally oxidizing the semiconductor substrate and forming an oxide film in which the lower surface of the trench is thicker than the side surface of the trench by accelerated oxidation of the second conductivity type impurity introduced into the lower surface of the trench;
Wet etching the oxide film, leaving the oxide film on the lower surface of the trench, and removing the oxide film on the side surface of the trench;
Performing epitaxial growth laterally from a side surface of the trench to form a second conductivity type second epitaxial layer on the oxide film;
And a step of introducing an impurity of a first conductivity type into the second epitaxial layer to form an emitter layer in contact with the oxide film. The method of manufacturing a semiconductor device according to claim 1 , wherein the semiconductor substrate is a single crystal substrate and is not an SOI substrate.

Images