JPH11354535A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve high breakdown strength and at the same time reduce collector resistance by providing a collector wall made of a first conductive impurity layer which is formed from a buried layer to a collector contact in a boundary among an insulation film, a buried material within a trench and a trench. SOLUTION: A collector wall (n-type diffusion layer 18n) with a higher concentration of impurity than that of an n-type collector area 7 is formed between an n-type buried layer 4 with a high concentration of impurity and an n-type collector contact 13. Further a collector wall (p-type diffusion layer 18p) with a higher concentration of impurity than that of a p-type collector area 8 is formed between a p-type buried layer 5 with a high concentration of purity and a p-type collector contact 15. Thus the collector resistance of the collector areas 7 and 8 is reduced, so that the n- and p-type collector areas 7 and 8 made of n-type epitaxial layer can be made larger in film thickness and the breakdown strength between base collectors be made higher as well.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a dielectric isolation type complementary bipolar transistor having both a high breakdown voltage between a base and a collector and a reduced collector resistance. And a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, transistors used for audio amplifiers, display drivers, and the like have been required to have higher breakdown voltage and higher integration. In order to achieve high integration and high speed of the high breakdown voltage integrated circuit, it is preferable to employ a dielectric isolation technology in order to prevent an increase in chip size due to formation of a parasitic transistor and formation of element isolation. Among dielectric isolation technologies for separating each element using an oxide film, from the viewpoint of cost, in particular, a bonded SOI (silicon oxide) is preferred.
Attention has been paid to n insulator substrates.

A manufacturing process for forming a high breakdown voltage bipolar transistor on an SOI substrate by a conventional manufacturing method will be described below with reference to FIGS.
FIG. 17 shows a high breakdown voltage vertical NPN transistor formation region and a high breakdown voltage vertical PNP transistor formation region. First, a buried oxide film 2 having a thickness of about 2 μm is formed on the surface of an n-type substrate 3 made of silicon by, for example, a thermal oxidation method. An n-type substrate 3 is bonded to a supporting substrate 1 at room temperature via a buried oxide film 2. In the subsequent steps, the n-type substrate 3 becomes an n-type buried layer 4 and a p-type buried layer 5 which are active layers. As the n-type substrate 3, for example, a silicon substrate having a specific resistance of about 10 Ωcm is used. Then, for example, at 1100 ° C
For about 2 hours in an oxygen atmosphere to increase the bonding strength between the buried oxide film 2 and the support substrate 1. Subsequently, for example, mechanical polishing or chemical mechanical polishing (CM
By P), the n-type substrate 3 is set to a predetermined thickness, for example, 2 μm.

Next, in order to form the n-type buried layer 4,
Perform ion implantation. An n-type impurity such as, for example, a photoresist (not shown) having an opening formed in an NPN transistor portion by a known photolithography technique is used as a mask.
Arsenic (As) with an ion energy of 50 keV and a dose of 3
Ion implantation is performed at × 10 ¹⁵ / cm ² . After that, the photoresist is removed. Further, ion implantation is performed to form the p-type buried layer 5. Using a photoresist (not shown) having an opening in the PNP transistor portion by a known photolithography technique as a mask,
For example, boron (B) is ion energy of 50 keV,
Ions are implanted at a dose of 3 × 10 ¹⁵ / cm ² . afterwards,
Remove the photoresist.

Subsequently, for example, at 1100 ° C. for about 1 hour,
By annealing in a steam atmosphere, N
Arsenic introduced into the PN transistor part, and PNP
The boron introduced into the transistor portion is thermally diffused to form an n-type buried layer 4 and a p-type buried layer 5. In this annealing step, an oxide film (not shown) is formed on the surface of the active layer. After the annealing, the oxide film is removed by light etching using a hydrofluoric acid solution or the like. As a result, a structure as shown in FIG. 17 is obtained.

Next, as shown in FIG. 18, an n-type epitaxial layer 6 having a specific resistance of 10 Ωcm and a thickness of 15 μm is grown on the n-type buried layer 4 and the p-type buried layer 5 as active layers. NP of n-type epitaxial layer 6
The N-transistor portion becomes an n-type collector region 7, and the PNP transistor portion of the n-type epitaxial layer 6 becomes a p-type collector region 8 in a subsequent step. An oxide film 9 having a thickness of about 50 nm is formed on the n-type epitaxial layer 6 by a thermal oxidation method. A p-type impurity, for example, boron (B), with an ion energy of 300 keV and an introduction amount of 8 × 1, using a photoresist having an opening in a PNP transistor portion by a known photolithography technique as a mask.
Ion implantation is performed at 0 ¹² / cm ² . Annealing is performed in an inert gas atmosphere at, for example, about 1200 ° C. for about 7 hours to form a P-type collector region 8 of the PNP transistor. As a result, a structure as shown in FIG. 18 is obtained.

Next, by a known photolithography technique, a p-type impurity such as boron (B) is ion-energyd to 40 k using a photoresist (not shown) having an opening formed in an upper layer of the base region of the NPN transistor as a mask.
Ion implantation is performed at eV and a dose of 1 × 10 ¹⁴ / cm ² . After the photoresist is removed, an n-type impurity, for example, phosphorus (P) is ion-energized at 60 keV by a known photolithography technique using a photoresist (not shown) provided with an opening in the upper layer of the base region of the PNP transistor as a mask. Ions are implanted at a dose of 1 × 10 ¹⁴ / cm ² . After removing the photoresist, in an inert gas atmosphere,
For example, by annealing at 900 ° C. for about 30 minutes,
The impurities are thermally diffused, and the p-type base region 10 of the NPN transistor and the n-type base region 1 of the PNP transistor
1 are formed respectively.

Next, by a known photolithography technique, an n-type impurity such as arsenic (As) is formed by using a photoresist (not shown) having an opening in an n-type emitter region and an n-type collector contact upper layer of the NPN transistor as a mask. ) With an ion energy of 110 keV and an introduced amount of 5
Ion implantation is performed at × 10 ¹⁵ / cm ² . After that, the photoresist is removed. Subsequently, a p-type impurity such as boron (B) is ion-implanted by a known photolithography technique using a photoresist (not shown) provided with an opening in a p-type emitter region and a p-type collector contact upper layer of the PNP transistor as a mask. Ion implantation is performed at an energy of 40 keV and a dose of 3 × 10 ¹⁵ / cm ² . After removing the photoresist, for example, 1000
By annealing at 30 ° C. for about 30 minutes, the impurities are thermally diffused to form the n-type emitter region 12 and the n-type collector contact 13 of the NPN transistor and the p-type emitter region 14 and the p-type collector contact 15 of the PNP transistor, respectively. You. As a result, FIG.
The structure is as shown in FIG.

Thereafter, the oxide film 9, the n-type collector layer 7 and the n-type buried layer 4 in the NPN transistor portion are etched until they reach the buried oxide film 2.
A trench 16 for element isolation is formed. At the same time, PNP
The oxide film 9, the p-type collector layer 8, and the p-type buried layer 5 in the transistor portion are etched until reaching the buried oxide film 2, thereby forming a trench 16 for element isolation. As a result, a structure as shown in FIG. 20 is obtained. Next, an oxide film 17 having a thickness of about 500 nm is formed on the inner wall of the trench 16 by, for example, a thermal oxidation method. As a result, a structure as shown in FIG. 21 is obtained. In the trench 16 in which the oxide film 17 is formed, a polysilicon 18 is deposited while being buried by, for example, a CVD method. afterwards,
The polysilicon 18 exposed from the trench is etched back by, for example, reactive ion etching (RIE) to planarize the surface. As a result, a structure as shown in FIG. 22 is obtained.

Next, an oxide film 19 is deposited on the entire surface by, for example, a CVD method. Further, a photoresist (not shown) is deposited on the entire surface, and an opening is provided in the photoresist on the electrode forming portion by a known photolithography technique. Using the photoresist as a mask, for example, RIE is performed to provide openings in the oxide film 19 and the electrode formation portion of the oxide film 9.
As a result, a structure as shown in FIG. 23 is obtained. Aluminum 20 is deposited by, for example, a sputtering method on the entire surface of the oxide film 19 where the opening is formed in the electrode formation portion. Thereafter, a photoresist (not shown) is deposited on the entire surface, and the photoresist other than the electrode portions is removed by a known photolithography technique. Using the photoresist as a mask, the aluminum 20 is patterned by, for example, the RIE method. After the electrodes are formed, the photoresist is removed to obtain a semiconductor device having a cross section shown in FIG.

In the semiconductor device having the above structure, the adjacent NPN transistor and P
Electrical insulation and separation from the NP transistor are performed. Accordingly, the integration density can be increased, and the parasitic capacitance of the pn junction of each transistor can be reduced, which is advantageous for speeding up. In the semiconductor device having the above structure, the base-collector breakdown voltage is secured by lowering the impurity concentration of the collector regions 7 and 8. However, if the collector regions 7 and 8 as a whole have a low impurity concentration, , The series resistance increases and the characteristics deteriorate.
Therefore, as shown in FIG. 24, an n-type buried layer 4 and a p-type buried layer 5 having a high impurity concentration are provided below the collector regions 7 and 8 having a low impurity concentration. As a result, a high withstand voltage of the bipolar transistor is realized while taking advantage of the high speed property which is an advantage of the bipolar transistor.

[0012]

In the above-mentioned conventional method for manufacturing a semiconductor device, the collector regions 7, 8 having a low impurity concentration, that is, the n-type epitaxial layer 6, must be formed thick to achieve a high breakdown voltage. There is. By forming the collector regions 7 and 8 thick, the collector resistance of each of the vertical NPN transistor and the vertical PNP transistor increases, which hinders the speeding up of the transistors. To solve the problem of increasing the collector resistance due to the increase in the thickness of the collector regions 7 and 8, a high concentration impurity is diffused from the surface of the n-type epitaxial layer (n-type collector region 7) and the surface of the p-type collector region 8 to take out the collector. There is also a method of forming a diffusion layer (collector contact) for use. This makes it possible to reduce the collector resistance while maintaining the base-collector breakdown voltage.

However, in the case of a vertical bipolar transistor, if the collector region is further thickened in order to increase the base-collector breakdown voltage, as described above, it is necessary to diffuse impurities from the surface of the n-type epitaxial layer. Higher temperature and longer time heat treatment is required. Therefore, there is a limit in the process for increasing the thickness of the collector region, and the cost increases. Furthermore, when ion implantation with high energy and high introduction amount is performed to increase the diffusion depth of the impurity, there is a problem that crystal defects of the silicon substrate become remarkable. As described above, according to the conventional method of manufacturing a semiconductor device, when the thickness of the collector region is increased, a collector contact having a high impurity concentration cannot be formed, and it is difficult to reduce the collector resistance.

The present invention has been made in view of the above problems, and in a vertical bipolar transistor, in particular, a complementary bipolar transistor of a dielectric isolation type, both high transistor breakdown voltage and low collector resistance are compatible. It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same.

[0015]

In order to achieve the above object, a semiconductor device according to the present invention is a semiconductor device that uses a trench to insulate and separate an adjacent first semiconductor circuit and a second semiconductor circuit. A buried insulating film formed on the semiconductor substrate; a first buried layer made of a first conductivity type high concentration impurity diffusion layer formed on the insulating film; A first collector region formed of a low concentration impurity diffusion layer of a first conductivity type formed in the first collector region; a first base region of a second conductivity type formed in the first collector region; A first emitter region formed of a first-conductivity-type high-concentration impurity diffusion layer formed in the base region; and a surface of the first collector region.
A first semiconductor circuit having a first collector contact formed of a first conductive type high-concentration impurity diffusion layer and formed at a predetermined distance from the first base region; and the first semiconductor circuit. A trench formed from the collector contact to the buried insulating film to electrically insulate and isolate the first semiconductor circuit from an adjacent second semiconductor circuit; and at least the collector contact on an inner wall of the trench. An insulating film formed in a portion excluding an interface of the first conductive material, a buried material buried in the trench, containing a first conductivity type impurity at a high concentration, and an interface between the trench in the collector region and the buried material. A collector wall comprising a first conductivity type impurity diffusion layer formed from the buried layer to the collector contact. That.

In the semiconductor device according to the present invention, preferably, the second semiconductor circuit includes a second buried layer made of a second conductivity type high concentration impurity diffusion layer formed on the buried insulating film. A second collector region formed of a second conductivity type low concentration impurity diffusion layer formed on the second conductivity type high concentration impurity diffusion layer; and a first conductivity type of a first conductivity type formed on the collector region. A second base region, a second emitter region formed of a second conductive type high-concentration impurity diffusion layer formed on the base region, and a predetermined distance from the base region on a surface of the collector region; A second collector contact formed of a second conductive type high-concentration impurity diffusion layer, wherein the first and second semiconductor circuits constitute a complementary bipolar transistor having a dielectric isolation structure. Do And wherein the door.

Preferably, in the semiconductor device according to the present invention, the semiconductor substrate, the buried insulating film, and the buried layer are made of silicon on insulator (SOI).
r) It consists of a substrate. The semiconductor device according to the present invention is preferably characterized in that the first and second collector regions are epitaxial layers made of silicon. The semiconductor device of the present invention is preferably characterized in that the buried insulating film and the insulating film are made of a silicon oxide film. The semiconductor device of the present invention is preferably characterized in that the filling material in the trench is made of polysilicon. Alternatively, the semiconductor device of the present invention is preferably characterized in that the filling material in the trench is made of an insulating material. The semiconductor device of the present invention is preferably characterized in that the insulating material is made of a silicon oxide film. Alternatively, the semiconductor device of the present invention is preferably characterized in that the insulating material is made of a silicon nitride film.

According to the above-described semiconductor device of the present invention, since the collector wall in which the impurity in the trench is diffused is formed on the side surface of the collector region, the collector resistance is reduced. This increases the breakdown voltage between the base and the collector, so that even when the collector region is formed thick,
The high speed of the bipolar transistor is not impaired. Further, since the trench using the dielectric isolation technology is formed on the side surface of the bipolar transistor, the occurrence of a parasitic transistor is suppressed, and both high speed and high breakdown voltage of the bipolar transistor can be achieved.

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises the steps of: providing a first semiconductor circuit and a second semiconductor circuit having a conductivity type opposite to that of the first semiconductor circuit on the same semiconductor substrate; And a method of manufacturing a semiconductor device for forming a trench separating the first and second semiconductor circuits, wherein a buried insulating film is formed on a semiconductor substrate;
Forming a first semiconductor substrate on a second semiconductor substrate serving as a support substrate via the buried insulating film;
(Silicon on insulator) forming a substrate; diffusing impurities into the first semiconductor substrate to form buried layers in the first and second semiconductor circuit formation regions, respectively; Forming a collector region on the buried layer in the second semiconductor circuit formation region, respectively;
A step of diffusing impurities on the collector region of the semiconductor circuit forming region to form respective base regions;
Forming an emitter region by diffusing impurities on the base region of the first and second semiconductor circuit formation regions; and forming an emitter region on the collector region surface of the first and second semiconductor circuit formation regions. Forming a collector contact by diffusing impurities at a predetermined distance from the base region, and etching the side surfaces of the first and second semiconductor circuit formation regions until reaching the buried insulating film. Forming a trench for electrically insulating and isolating the first and second semiconductor circuits from each other; forming an insulating film on the inner wall of the trench; and forming an insulating film on the inner wall of the trench. Etching at least the interface with the collector contact to selectively remove the insulating film; and filling a filling material inside the trench. Depositing an impurity into the burying material; and diffusing the impurity through an selectively removed portion of the insulating film at an interface between the collector region and the trench to form the buried layer. Forming a collector wall connecting the collector contact.

In the method of manufacturing a semiconductor device according to the present invention, preferably, the step of forming the SOI substrate includes bonding the second semiconductor substrate to the semiconductor substrate on which the buried insulating film is formed. Therefore, the process is characterized by performing a heat treatment to increase the bonding strength.

In the method of manufacturing a semiconductor device according to the present invention, preferably, the buried insulating film and the insulating film are made of a silicon oxide film. In the method for manufacturing a semiconductor device according to the present invention, preferably, the filling material in the trench is made of polysilicon. Alternatively, the method for manufacturing a semiconductor device according to the present invention is preferably characterized in that the filling material in the trench is made of an insulating material. The method for manufacturing a semiconductor device according to the present invention includes:
Preferably, the insulating material comprises a silicon oxide film. Alternatively, the method of manufacturing a semiconductor device according to the present invention is preferably characterized in that the insulating material is made of a silicon nitride film.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming a buried insulating film on a semiconductor substrate; Are stacked with the buried insulating film interposed therebetween, and SOI (silicon on ins) is formed.
forming a buried layer by diffusing a first conductivity type impurity at a high concentration in the first semiconductor substrate; and forming a first buried layer on the buried layer.
Forming a collector region containing a conductive type impurity at a low concentration, forming a base region by diffusing a second conductive type impurity on the collector region, and forming a first region on the base region. A step of forming an emitter region by diffusing a conductive type impurity at a high concentration; and a step of forming a collector contact by diffusing a first conductive type impurity at a high concentration on the surface of the collector region at a predetermined distance from the base region. Forming a buried layer, the collector region, the base region, the emitter region, and a side surface of the first semiconductor circuit containing the collector contact until the buried insulating film is reached, Forming a trench for electrically insulating and separating one semiconductor circuit from an adjacent second semiconductor circuit; Forming an insulating film on the inner wall of the trench, etching at least an interface with the collector contact, and selectively removing the insulating film; and depositing a filling material inside the trench. Introducing a first conductivity type impurity into the burying material at a high concentration; and selecting the insulating film at the interface between the collector region and the trench by introducing the first conductivity type impurity contained in the burying material. Forming a collector wall connecting the buried layer and the collector contact by diffusing through the part that has been removed.

According to the above-described method for manufacturing a semiconductor device of the present invention, a collector wall for connecting a buried layer having a high impurity concentration and a collector contact is formed on the side surface of a collector region by utilizing a trench in which an insulating film is buried. Form.
Therefore, a small number of steps are added to the conventional method of manufacturing a dielectric isolation bipolar transistor, that is, a step of forming a buried material having a high impurity concentration in a trench and a step of diffusing impurities from the buried material to a collector region. Only by adding, the collector resistance can be reduced. Further, according to the method for manufacturing a semiconductor device of the present invention, it is possible to reduce the occurrence of crystal defects in the substrate as compared with the case where the collector extraction diffusion layer is formed by performing ion implantation on the substrate surface.

[0024]

Embodiments of a semiconductor device and a method of manufacturing the same according to the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view of the semiconductor device of the present embodiment. The semiconductor device of the present embodiment has the trench 16
And a complementary transistor having a dielectric isolation structure in which the elements are separated from each other, and a high breakdown voltage vertical NPN transistor and a high breakdown voltage vertical PNP transistor are formed on the same SOI substrate (1, 2 and 3). I have. A buried oxide film 2 is formed on a support substrate 1, and an n-type buried layer 4 having a high impurity concentration and an n-type collector region 7 having a low impurity concentration are formed in a high breakdown voltage vertical NPN transistor portion thereon. I have. A p-type base region 10, an n-type emitter region 12, and an n-type collector contact 13 are formed on the surface of n-type collector region 7, and each is connected to an upper wiring (not shown) via an electrode 20 made of, for example, aluminum. ing. Further, a collector wall (n-type diffusion layer 18n) having a higher impurity concentration than the n-type collector region 7 is formed between the n-type buried layer 4 having a high impurity concentration and the n-type collector contact 13.

A high impurity concentration p-type buried layer 5 and a low impurity concentration p-type collector region 8 are formed on the high breakdown voltage vertical PNP transistor portion. The p-type emitter region 14 and the p-type collector contact 15 are formed so as to be connected to the electrode 20 respectively. Further, a collector wall (p-type diffusion layer 18p) having a higher impurity concentration than the p-type collector region 8 is formed between the p-type buried layer 5 having a high impurity concentration and the p-type collector contact 15.

According to the semiconductor device of the present embodiment,
By forming the collector wall (the n-type diffusion layer 18n and the p-type diffusion layer 18p), the collector resistance of the collector regions 7, 8 is reduced. Therefore, n-type and p-type collector regions 7 formed from the n-type epitaxial layer,
8 can be made thicker, and the breakdown voltage between the base and the collector can be increased. Further, since the generation of the parasitic transistor is suppressed by adopting the dielectric isolation technology, a high-speed and high-withstand-voltage bipolar transistor can be obtained.

Next, a method of manufacturing the above semiconductor device will be described. First, as shown in FIG. 2, a film having a thickness of 2 μm is formed on the surface of an n-type substrate 3 made of silicon by, for example, a thermal oxidation method.
A buried oxide film 2 of about m is formed. An n-type substrate 3 is bonded on a supporting substrate 1 at room temperature via a buried oxide film 2. The n-type substrate 3 has an active layer of n
The buried layer 4 and the p-type buried layer 5 are formed. As the n-type substrate 3, for example, a silicon substrate having a specific resistance of about 10 Ωcm is used. Thereafter, annealing is performed at, for example, 1100 ° C. for about 2 hours in an oxygen atmosphere to increase the bonding strength between the buried oxide film 2 and the support substrate 1. Subsequently, for example, by mechanical polishing or chemical mechanical polishing (CMP),
The n-type substrate 3 has a predetermined thickness, for example, 2 μm. This results in a structure as shown in FIG.

Next, as shown in FIG. 3, a photoresist 21 is deposited on the entire surface, and an opening is formed in the NPN transistor portion of the photoresist 21 by a known photolithography technique. Using the photoresist 21 as a mask, an n-type impurity, for example, arsenic (As) is ion energy 50 k
Ion is selectively implanted into the n-type substrate 3 in the NPN transistor portion at eV and a dose of 3 × 10 ¹⁵ / cm ² . This results in a structure as shown in FIG. After that, the photoresist 21 is removed.

Next, as shown in FIG. 4, a photoresist 22 is deposited on the entire surface, and an opening is provided in the PNP transistor portion of the photoresist 22 by a known photolithography technique. Using the photoresist 22 as a mask, a p-type impurity such as boron (B) is ion energy 50
The ions are selectively implanted into the n-type substrate 3 at the PNP transistor portion at a keV and a dose of 3 × 10 ¹⁵ / cm ² . Thereby, a structure as shown in FIG. 4 is obtained. After that, the photoresist 22 is removed.

Subsequently, for example, at about 1100 ° C. for about 1 hour,
By annealing in a steam atmosphere, N
Arsenic introduced into the PN transistor part, and PNP
The boron introduced into the transistor portion is thermally diffused to form an n-type buried layer 4 and a p-type buried layer 5. In this annealing step, an oxide film (not shown) is formed on the surface of the active layer. After the annealing, the oxide film is removed by light etching using a hydrofluoric acid solution or the like.

Next, as shown in FIG. 5, the active layer n
An n-type epitaxial layer 6 is grown on the type buried layer 4 and the p-type buried layer 5. For example, the n-type epitaxial layer 6 has a specific resistance of 10 Ωcm and a thickness of 15 μm.
Of silicon. N of n-type epitaxial layer 6
The PN transistor portion becomes an n-type collector region 7 and n
The PNP transistor portion of the type epitaxial layer 6 becomes a p-type collector region 8 in a subsequent step. An oxide film 9 having a thickness of about 50 nm is formed on the n-type epitaxial layer 6 by a thermal oxidation method. This results in a structure as shown in FIG.

Next, as shown in FIG. 6, a photoresist 23 is deposited on the entire surface, and an opening is provided in the PNP transistor portion of the photoresist 23 by a known photolithography technique. Using the photoresist 23 as a mask, a p-type impurity such as boron (B) is ion energy 30
The ions are selectively implanted into the n-type epitaxial layer 6 of the PNP transistor portion at 0 keV and a dose of 8 × 10 ¹² / cm ² . Then, in an inert gas atmosphere, for example, 120
By annealing at 0 ° C. for about 7 hours, a p-type collector region 8 of the PNP transistor is formed. As a result, a structure as shown in FIG. 6 is obtained. After that, the photoresist 23 is removed.

Next, as shown in FIG. 7, a photoresist 24 is deposited on the entire surface, and an opening is provided in the photoresist 24 on the p-type base region 10 of the NPN transistor by a known photolithography technique. Using the photoresist 24 as a mask, a p-type impurity, for example, boron (B)
With the ion energy of 40 keV and the introduced amount of 1 × 10 ¹⁴ / c
At m ² , ions are selectively implanted into the p-type base formation region 10 of the NPN transistor. As a result, a structure as shown in FIG. 7 is obtained. After that, the photoresist 24 is removed.

Subsequently, as shown in FIG. 8, a photoresist 25 is deposited on the entire surface, and an opening is provided in the photoresist 25 on the n-type base region 11 of the PNP transistor by a known photolithography technique. Using the photoresist 25 as a mask, an n-type impurity, for example, phosphorus (P)
With an ion energy of 60 keV and an introduction amount of 1 × 10 ¹⁴ / c
At m ² , ions are selectively implanted into the n-type base formation region 11 of the PNP transistor. As a result, a structure as shown in FIG. 8 is obtained. After removing the photoresist 25, annealing is performed in an inert gas atmosphere at, for example, 900 ° C. for about 30 minutes, whereby the impurities are thermally diffused and the p-type base region 10 of the NPN transistor and the n-type
Mold base regions 11 are respectively formed.

Next, as shown in FIG. 9, a photoresist 26 is deposited on the entire surface, and an opening is formed in the photoresist 26 on the n-type emitter region 12 and the n-type collector contact 13 of the NPN transistor by a known photolithography technique. Is provided. Using the photoresist 26 as a mask, an n-type impurity, for example, arsenic (As) is selectively ionized into the n-type emitter region 12 and the n-type collector contact 13 of the NPN transistor at an ion energy of 110 keV and an introduction amount of 5 × 10 ¹⁵ / cm ^2. inject. As a result, a structure as shown in FIG. 9 is obtained. After that, the photoresist 26 is removed.

Subsequently, as shown in FIG. 10, a photoresist 27 is deposited on the entire surface, and the p-type emitter region 1 of the PNP transistor is formed by a known photolithography technique.
An opening is provided in the photoresist 27 on the layer 4 and the p-type collector contact 15. Using the photoresist 27 as a mask, a P-type impurity, for example, boron (B) is ion-exchanged at an energy of 40 keV and a dose of 3 × 10 ¹⁵ / cm ² for PNP
Ions are selectively implanted into a layer above the p-type emitter region 14 and the p-type collector contact 15 of the transistor. Thereby, a structure as shown in FIG. 10 is obtained.

After the photoresist 27 is removed, the impurities are thermally diffused by annealing in an inert gas atmosphere at, for example, 1000 ° C. for about 30 minutes, so that the n-type emitter region 12 and the n-type collector contact 13 of the NPN transistor, And a p-type emitter region 14 and a p-type collector contact 15 of the PNP transistor, respectively.

Thereafter, as shown in FIG. 11, the oxide film 9, the n-type collector layer 7 and the n-type buried layer 4 in the NPN transistor portion are etched until they reach the buried oxide film 2, thereby forming a trench for element isolation. 16 are formed. At the same time, the oxide film 9 in the PNP transistor portion, p
The type collector layer 8 and the p-type buried layer 5 are etched until the buried oxide film 2 is reached, thereby forming a trench 16 for element isolation. The trench 16 is formed such that the side surfaces of the collector contacts 13 and 15 of the NPN transistor and the PNP transistor are exposed inside the trench 16. As a result, FIG.
The structure shown in FIG.

Next, as shown in FIG. 12, an oxide film 17 having a thickness of about 500 nm is formed on the inner wall of the trench 16 by, for example, a thermal oxidation method. Further, as shown in FIG.
Oxide film 1 in contact with collector contacts 13 and 15 of PN transistor and PNP transistor, respectively
7 is removed by etching.

In the trench 16 in which the side surfaces of the collector contacts 13 and 15 are exposed, a burying material is deposited while being buried by, for example, the CVD method. As the filling material, for example, polysilicon 18 is used. After that, the filling material exposed from the trench 16 is etched back by, for example, RIE to flatten the surface. As a result, a structure as shown in FIG. 14 is obtained.

An n-type impurity is introduced into polysilicon 18 buried in trench 16 in contact with n-type collector contact 13 of the NPN transistor. Using a known photolithography technique, a photoresist (not shown) having an opening only in the above-described trench is formed, and an n-type impurity, for example, phosphorus (P) is ion energy of 180 keV and an introduced amount of 5 × 10 ¹⁵ using the photoresist as a mask. / Cm ² . Next, a p-type impurity is introduced into the polysilicon buried in the trench in contact with the p-type collector contact 15 of the PNP transistor. Using a known photolithography technique, a photoresist (not shown) having an opening only in the above-described trench is formed, and a p-type impurity, for example, boron (B) is ion-energy 1 using the photoresist as a mask.
Ion implantation is performed at 80 keV and a dose of 5 × 10 ¹⁵ / cm ² .

Subsequently, in an inert gas atmosphere, for example, 1
By annealing at 000 ° C. for about 30 minutes, NPN
Phosphorus (P) is thermally diffused from the trench of the transistor to form an n-type diffusion layer 18n connecting the n-type buried layer 4 and the n-type collector contact 13. At the same time, PN
Boron (B) is thermally diffused from the trench of the P transistor, so that the p-type buried layer 5 and the p-type collector contact 15 are formed.
Are connected to form a p-type diffusion layer 18p. Since the diffusion speed of the impurity in the polysilicon is several tens of times higher than the diffusion speed of the impurity in the single crystal silicon, the impurity is quickly transferred from the polysilicon in the trench to the single crystal silicon (epitaxial layer) in the collector region. Spread. The impurity that has moved to the collector region has its impurity diffusion rate in the single crystal silicon limited, and accumulates in a layer at the interface with the trench, so that the n-type diffusion layer 18n and the p-type diffusion layer 18p
(Collector wall) is formed. As a result, FIG.
The structure shown in FIG.

Next, as shown in FIG.
An oxide film 19 is deposited on the entire surface by a method. Further, a photoresist (not shown) is deposited on the entire surface, and an opening is provided in the photoresist on the electrode forming portion by a known photolithography technique. Using the photoresist as a mask, for example, RIE is performed to provide openings in the oxide film 19 and the electrode formation portion of the oxide film 9.

Oxide film 1 having an opening at the electrode formation portion
Aluminum 20 is deposited on the entire surface of the substrate 9 by, for example, a sputtering method. Thereafter, a photoresist (not shown) is deposited on the entire surface, and the photoresist other than the electrode portions is removed by a known photolithography technique. Using the photoresist as a mask, the aluminum 20 is patterned by, for example, the RIE method. After the electrodes are formed, the photoresist is removed to obtain a semiconductor device whose sectional view is shown in FIG.

According to the method of manufacturing the semiconductor device of the present embodiment, the high impurity concentration buried layers 4 and 5 and the collectors are formed on the side surfaces of the collector regions 7 and 8 by utilizing the diffusion of the impurities from the trench 16. A collector wall (n-type diffusion layer 18n, p-type diffusion layer 18p) connecting the contacts 13 and 15 is formed. Therefore, as compared with the case where the impurity is diffused from the surface, it is possible to diffuse the impurity at a high concentration to a deep position by a short heat treatment. That is, the occurrence of lattice defects in the crystal as seen when impurities are introduced by ion implantation is suppressed. Also,
Adding a small number of steps to the conventional method of manufacturing a dielectric isolation bipolar transistor, specifically, a step of forming a high impurity concentration buried material in a trench and a step of diffusing impurities from the buried material into a collector region By merely adding the above, the collector resistance of the semiconductor device can be reduced.

The semiconductor device and the method of manufacturing the same according to the present invention are not limited to the above embodiment. For example, SOI
As the substrate, other than the bonded SOI substrate as described above, an SOI substrate in which an epitaxial layer is grown on a buried insulating film formed on the substrate can also be used. In addition, various changes can be made without departing from the gist of the present invention.

[0047]

According to the semiconductor device of the present invention, the collector region can be formed thick to increase the breakdown voltage of the bipolar transistor and reduce the collector resistance.

Further, according to the method of manufacturing a semiconductor device of the present invention, a small number of steps are added since a collector extraction diffusion layer (collector wall) is formed by diffusing impurities from a trench formed by a dielectric isolation technique. Only by doing so, the collector resistance can be reduced. Further, the generation of crystal defects in the substrate can be reduced as compared with the case where the collector extraction diffusion layer is formed by performing ion implantation on the substrate surface.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a semiconductor device of the present invention.

FIG. 2 is a cross-sectional view illustrating a manufacturing process of a method for manufacturing a semiconductor device according to the present invention.

FIG. 3 is a cross-sectional view illustrating a manufacturing process of a method for manufacturing a semiconductor device according to the present invention.

FIG. 4 is a cross-sectional view showing a manufacturing step of the method for manufacturing a semiconductor device according to the present invention.

FIG. 5 is a cross-sectional view showing a manufacturing step of the method for manufacturing a semiconductor device according to the present invention.

FIG. 6 is a cross-sectional view showing a manufacturing step of the method for manufacturing a semiconductor device according to the present invention.

FIG. 7 is a cross-sectional view showing a manufacturing step of the method for manufacturing a semiconductor device according to the present invention.

FIG. 8 is a cross-sectional view showing a manufacturing step of the method for manufacturing a semiconductor device according to the present invention.

FIG. 9 is a cross-sectional view showing a manufacturing step of the method for manufacturing a semiconductor device according to the present invention.

FIG. 10 is a cross-sectional view showing a manufacturing step of the method for manufacturing a semiconductor device according to the present invention.

FIG. 11 is a cross-sectional view showing a manufacturing step of the method for manufacturing a semiconductor device according to the present invention.

FIG. 12 is a cross-sectional view showing a manufacturing step of the method for manufacturing a semiconductor device according to the present invention.

FIG. 13 is a cross-sectional view showing a manufacturing step of the method for manufacturing a semiconductor device according to the present invention.

FIG. 14 is a cross-sectional view showing a manufacturing step of the method for manufacturing a semiconductor device according to the present invention.

FIG. 15 is a cross-sectional view showing a manufacturing step of the method for manufacturing a semiconductor device according to the present invention.

FIG. 16 is a cross-sectional view showing a manufacturing step of the method for manufacturing a semiconductor device according to the present invention.

FIG. 17 is a cross-sectional view showing a manufacturing step in a conventional method for manufacturing a semiconductor device.

FIG. 18 is a cross-sectional view showing a manufacturing step in a conventional method for manufacturing a semiconductor device.

FIG. 19 is a cross-sectional view showing a manufacturing step in a conventional method for manufacturing a semiconductor device.

FIG. 20 is a cross-sectional view showing a manufacturing step in a conventional method for manufacturing a semiconductor device.

FIG. 21 is a cross-sectional view showing a manufacturing step of a conventional semiconductor device manufacturing method.

FIG. 22 is a cross-sectional view showing a manufacturing step in a conventional method for manufacturing a semiconductor device.

FIG. 23 is a cross-sectional view showing a manufacturing step in a conventional method for manufacturing a semiconductor device.

FIG. 24 is a cross-sectional view of a conventional semiconductor device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Support substrate, 2 ... Buried oxide film, 3 ... N-type substrate, 4
... n-type buried layer, 5 ... p-type buried layer, 6 ... n-type epitaxial layer, 7 ... n-type collector region, 8 ... p-type collector region, 9, 19 ... oxide film, 10 ... p-type base region, 1
1 ... n-type base region, 12 ... n-type emitter region, 13 ...
n-type collector contact, 14 ... p-type emitter region, 1
5 ... p-type collector contact, 16 ... trench, 17,
19 ... oxide film, 18 ... polysilicon, 18n ... n-type diffusion layer, 18p ... p-type diffusion layer, 20 ... aluminum (wiring), 21, 22, 23, 24, 25, 26, 27 ... photoresist.

Claims (17)

[Claims] 1. A semiconductor device for insulating and separating an adjacent first semiconductor circuit and a second semiconductor circuit using a trench, comprising: a buried insulating film formed on a semiconductor substrate; A first buried layer formed of a first conductivity type high-concentration impurity diffusion layer, and a first buried layer formed of a first conductivity type low-concentration impurity diffusion layer formed on the first buried layer. A first conductivity type collector region, a second conductivity type first base region formed in the first collector region,
A first emitter region formed of a first conductivity type high concentration impurity diffusion layer formed in the first base region and a surface of the first collector region are spaced apart from the first base region by a predetermined distance. A first semiconductor circuit having a first collector contact made of a high-concentration impurity diffusion layer of a first conductivity type, and a buried insulating layer formed on a side surface of the first semiconductor circuit from the collector contact; A trench which is formed up to a film and electrically insulates and separates the first semiconductor circuit from an adjacent second semiconductor circuit; and an insulation formed at a portion of an inner wall of the trench except at least an interface with the collector contact. A film, a burying material buried in the trench, containing a first conductivity type impurity at a high concentration, and an interface between the trench in the collector region. And a collector wall comprising a first conductivity type impurity diffusion layer formed from the buried layer to the collector contact. 2. The second semiconductor circuit according to claim 2, wherein the second buried layer is formed of a second conductivity type high concentration impurity diffusion layer formed on the buried insulating film; A second collector region formed of a low-concentration impurity diffusion layer of a second conductivity type formed on the diffusion layer; and a second collector region of the first conductivity type formed on the collector region.
A second emitter region formed of a second conductivity type high-concentration impurity diffusion layer formed on the base region; and formed on the surface of the collector region at a predetermined distance from the base region. And a second collector contact comprising a second conductive type high concentration impurity diffusion layer, wherein the first and second semiconductor circuits constitute a complementary bipolar transistor having a dielectric isolation structure. Item 2. The semiconductor device according to item 1. 3. The method according to claim 1, wherein the semiconductor substrate, the buried insulating film and the buried layer are made of silicon on silicon (SOI).
2. The semiconductor device according to claim 1, wherein the semiconductor device comprises an insulator substrate. 4. The semiconductor device according to claim 1, wherein said first and second collector regions are epitaxial layers made of silicon. 5. The buried insulating film and the insulating film,
2. The semiconductor device according to claim 1, comprising a silicon oxide film. 6. The semiconductor device according to claim 1, wherein said filling material in said trench is made of polysilicon. 7. The semiconductor device according to claim 1, wherein said filling material in said trench is made of an insulating material. 8. The semiconductor device according to claim 7, wherein said insulating material comprises a silicon oxide film. 9. The semiconductor device according to claim 7, wherein said insulating material comprises a silicon nitride film. 10. A first semiconductor circuit, a second semiconductor circuit having a conductivity type opposite to that of the first semiconductor circuit, and a trench separating the first and second semiconductor circuits on the same semiconductor substrate. Forming a buried insulating film on a first semiconductor substrate; and bonding the first semiconductor substrate to the second semiconductor substrate serving as a support substrate with the buried insulating film interposed therebetween. And stack the SOI
(Silicon on insulator) forming a substrate; diffusing impurities into the first semiconductor substrate to form a buried layer in each of the first and second semiconductor circuit formation regions; Forming a collector region on the buried layer in the second semiconductor circuit formation region, and diffusing impurities on the collector region in the first and second semiconductor circuit formation regions to form base regions, respectively. Forming an emitter region by diffusing an impurity on the base region of the first and second semiconductor circuit formation regions, respectively; and forming the first and second semiconductor circuit formation regions. On the surface of the collector region, impurities are diffused at a predetermined interval from the base region to form collector contacts. And etching the side surfaces of the first and second semiconductor circuit formation regions until reaching the buried insulating film to electrically insulate and separate between the first and second semiconductor circuits. A step of forming a trench; a step of forming an insulating film on the inner wall of the trench; and etching at least an interface of the insulating film on the inner wall of the trench with the collector contact to selectively remove the insulating film. A step of depositing a filling material in the trench; a step of introducing an impurity into the filling material; and a step of selectively removing the insulating film at an interface between the collector region and the trench. Forming a collector wall connecting the buried layer and the collector contact with the buried layer and the collector contact. Production method. 11. The step of forming the SOI substrate includes: bonding the first semiconductor substrate to the second semiconductor substrate via the buried insulating film; and performing heat treatment to increase the bonding strength. 11. The method for manufacturing a semiconductor device according to claim 10, which is a step. 12. The method according to claim 10, wherein said buried insulating film and said insulating film are made of a silicon oxide film. 13. The filling material in the trench,
The method for manufacturing a semiconductor device according to claim 10, comprising a polysilicon. 14. The filling material in the trench,
The method for manufacturing a semiconductor device according to claim 10, comprising an insulating material. 15. The method according to claim 14, wherein said insulating material comprises a silicon oxide film. 16. The method according to claim 14, wherein said insulating material comprises a silicon nitride film. 17. A step of forming a buried insulating film on a first semiconductor substrate; and laminating the first semiconductor substrate on a second semiconductor substrate serving as a support substrate with the buried insulating film interposed therebetween.
(Silicon on insulator) forming a substrate, forming a buried layer by diffusing a first conductivity type impurity at a high concentration in the first semiconductor substrate, and forming a first conductive layer on the buried layer. Forming a collector region containing an impurity of a low conductivity type, forming a base region by diffusing impurities of a second conductivity type on the collector region, and forming a first conductive material on the base region. Forming an emitter region by diffusing a high concentration impurity of a first conductivity type, and diffusing a first conductivity type impurity at a high concentration at a predetermined distance from the base region on the surface of the collector region to form a collector contact. Forming a buried layer, the collector region, the base region,
Etching is performed on the side surface of the first semiconductor circuit containing the emitter region and the collector contact until the buried insulating film is reached, so that the first semiconductor circuit is electrically insulated and separated from the adjacent second semiconductor circuit. Forming an insulating film on the inner wall of the trench; performing etching on at least an interface of the insulating film on the inner wall of the trench with the collector contact to selectively form the insulating film. Removing a buried material in the trench; introducing a first conductivity type impurity into the buried material at a high concentration; and removing the first conductivity type impurity contained in the buried material. The collector region is diffused through the selectively removed portion of the insulating film at the interface between the collector region and the trench; The method of manufacturing a semiconductor device having a step of forming a collector wall for connecting the write layer the collector contact.