JP3243071B2 - Dielectric separated type semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dielectric isolation type semiconductor device.

[0002]

2. Description of the Related Art As a method of element isolation used in a semiconductor device, a pn junction isolation method has been conventionally known, and a dielectric isolation method for the purpose of completely isolating insulators of a high withstand voltage integrated circuit has been known. Have been. This dielectric isolation method has less leakage current even at high temperature operation than the pn junction isolation method,
There are advantages in that latch-up by a parasitic thyristor is small, the area required for separation is small even when a high breakdown voltage element is separated, the polarity of an applied voltage does not need to be considered, and the parasitic capacitance is small.

As a dielectric isolation method, SOS (Silicon) in which silicon is vapor-phase grown on a sapphire substrate is used.
On-Sapphire, a method of depositing amorphous silicon on an insulating film and recrystallizing the same, and a method using direct bonding of a silicon wafer are known. Also, by etching a part of the silicon wafer to form an oxide film, depositing polycrystalline silicon thickly thereon and polishing it from the back side, it is held by the thick polycrystalline silicon,
There is also known a method of obtaining island-separated single crystal silicon.

[0004] Among these methods, the method using direct bonding of a silicon wafer can obtain an element forming portion separated by a dielectric as a thick and high quality single crystal silicon layer.

The inventor of the present applicant has obtained a dielectric isolation substrate by a method utilizing direct bonding between a table-side silicon wafer and an element-side silicon wafer, and a horizontal IGBT (insulated gate bipolar transistor) is provided on the element-side silicon wafer. And a semiconductor device formed with a semiconductor element comprising the control circuit. In this semiconductor device, the lateral IGBT is implanted with boron ions in the vicinity of the bonded portion of the element-side silicon wafer with the table-side silicon wafer to reduce the forward voltage and increase the switching characteristics. A high concentration layer was formed.

[0006]

In order to improve the switching characteristics of the lateral IGBT, it is desirable to increase the amount of boron ions implanted. However, in this semiconductor device, the dose of boron due to the ion implantation is reduced by 8%. × 1
0 was ¹⁴ / cm ² or more, crystal defects occur due to the ion implantation amount. Due to the crystal defects, the yield, electrical characteristics, reliability, and the like of the semiconductor device are reduced.

Therefore, when the dose of boron was set to 7 × 10 ¹⁴ / cm ² or less, the resistance of the ion-implanted P-type high-concentration layer increased, and the electrical characteristics also deteriorated.

Accordingly, an object of the present invention is to provide a dielectric isolation type semiconductor device utilizing direct bonding of a silicon wafer.
To provide a semiconductor device in which crystal defects do not occur even when a high dose boron ion is implanted in the vicinity of a bonding portion between an element side silicon wafer and a table side silicon wafer to form a P-type high concentration layer. It is in.

[0009]

In order to solve the above problems, a dielectric isolation type semiconductor device according to the present invention comprises at least one semiconductor device.
One of the first semiconductor substrate having an active region lateral insulated gate bipolar transistor is formed, is formed in a region including a first portion in contact with the semiconductor oxide film in the active region, 1.5 × 10 ¹⁵ and the high concentration layer of a predetermined conductivity type with boron dose ranging from pieces / cm ² of 3 × 10 ¹⁵ pieces / cm ² is ion-implanted, a second semiconductor oxide layer formed on the high concentration layer And a second semiconductor substrate adhered to the second semiconductor oxide film and supporting the first semiconductor substrate.

[0010]

[Action] The ion implantation amount of boron is 1.5 × 10 ¹⁵ / cm
Since it is an appropriate number of ² or more, the resistance value of the high concentration layer becomes low.
On the other hand, since the ion implantation amount is set to 3 × 10 ¹⁵ / cm ² or less, no crystal defects occur.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG.
An embodiment will be described.

[0012] As shown in FIG. 1, a silicon oxide film 2 is formed on the bottom surface of the element side silicon wafer 1, on the silicon oxide film 2 by a known direct bonding method, P for supporting the semiconductor element ^- type The base side silicon wafer 3 is bonded.

The element-side silicon wafer 1 is provided with a high breakdown voltage lateral IGBT 4 having a known structure and a control circuit 5 composed of low breakdown voltage transistors for controlling the high breakdown voltage lateral IGBT 4.

An insulating isolation groove 6 is formed in the center of the element-side silicon wafer 1, and the high breakdown voltage lateral IGBT 4 and its control circuit 5 are insulated and isolated by the insulating isolation groove 6.

The insulating isolation grooves 7 and 8 at both ends of the element-side silicon wafer 1 are provided for insulation isolation from other semiconductor elements on the same wafer.

At the bottom of the lateral IGBT 4 and the control circuit 5, P ⁺ type high concentration layers 9a and 9b are formed respectively. As described later, in the semiconductor device of the present invention, when forming the P ⁺ -type high-concentration layers 9a and 9b, the dose amount is 1 from the surface of the element-side silicon wafer 1 on the high-concentration layers 9a and 9b side. .5 × 10 ¹⁵ pieces / cm ² from 3 × 10 ¹⁵ pieces / cm ² range boron is ion-implanted.

As shown below, the boron ion implantation amount is a value obtained as a result of manufacturing a plurality of semiconductor devices of the present invention by changing the value and examining crystal defects thereof.

The dose (number / cm ²⁾ occurrence of crystal defects 2 × 10 ¹⁴ None 6 × 10 ¹⁴ None 8 × 10 ¹⁴ There 1 × 10 ¹⁵ Yes 1.5 × 10 ¹⁵ No 2 × 10 ¹⁵ No 3 × 10 ¹⁵ no 5 × 10 ¹⁵ Yes 7 × 10 ¹⁵ Yes it should be noted that the experimental results, a semiconductor device of the present invention shown in FIG. 1, and cleaving from the base side silicon wafer 3 side, the element side silicon wafer 1 adhere The surface side is exposed, the exposed adhesive surface is etched for 2 minutes, the silicon oxide film 2 is cut out, and the P ⁺ -type high concentration layers 9a and 9b are exposed.

In order to improve the electrical characteristics of a semiconductor device such as a lateral IGBT, the amount of boron ions implanted must be increased in order to lower the resistance of a P ⁺ -type high concentration layer contained in the active region. It is desirable that the ion implantation amount of boron is 1.5 × 10
^It can be seen that the range of ¹⁵ ions / cm ² to 3 × 10 ¹⁵ ions / cm ^{2 is} an appropriate ion implantation amount that improves the electrical characteristics of the semiconductor device and does not generate crystal defects.

Next, a method of manufacturing a semiconductor substrate for the dielectric isolation type semiconductor device shown in FIG. 1 will be described with reference to FIGS. 2 (a) to 2 (k). 2 (a) to 2 (k)
1, the same members as those in FIG. 1 are denoted by the same reference numerals.

As shown in FIG. 2A, the surface of the device-side silicon wafer 1 for forming the semiconductor device has a thickness of 80 mm.
Silicon oxide films 2 and 11 each having a thickness of 0 Å are formed by a thermal oxidation method.

Next, as shown in FIG. 2B, a dose of 1.5 × 10 ¹⁵ / cm ² to 3 × 10 ¹⁵ / cm ² is applied from the surface of the silicon oxide film 2 to the silicon wafer 1 on the element side. Is implanted in the range of boron. Temperature 11 in nitrogen atmosphere
Anneal at 00 ° C for 1 hour to activate boron,
Oxidation is performed at 100 ° C. for 3 hours to form a P ⁺ type high concentration layer 9. The silicon oxide films 2 and 11 are further oxidized to a thickness of 1 μm. Then, a table-side silicon wafer 3 that supports semiconductor elements formed on the element-side silicon wafer 1 is prepared.

Next, as shown in FIG. 2C, the silicon oxide film 2 and the table-side silicon wafer 3 are bonded by a known direct bonding method. Then, heat treatment is performed at a temperature of 1100 ° C. for 2 hours to integrate the element-side silicon wafer 1 and the table-side silicon wafer 3.

Next, as shown in FIG. 2D, the device-side silicon wafer 1 of the integrated wafer is polished from the silicon oxide film 11 side to a thickness of 50 μm.

Next, as shown in FIG. 2E, silicon oxide films 12 and 13 are formed on the surfaces of the table-side silicon wafer 3 and the element-side silicon wafer 1, respectively, by a thermal oxidation method.

Next, as shown in FIG. 2F, the separation groove forming portions 14, 15, and 16 are opened by photolithography.

Next, as shown in FIG. 2 (g), the insulating separation grooves for the horizontal insulation separation reaching the silicon oxide film 2 from the surfaces of the separation groove forming parts 14, 15, 16 by anisotropic etching. 6, 7, and 8 are formed. The element-side silicon wafer 1 is vertically separated from the table-side silicon wafer 3 by the silicon oxide film 2.

Next, as shown in FIG. 2H, boron (CVD) is applied to the side walls of the separation grooves 6, 7, and 8 at a temperature of 700 to 800 ° C. for 30 minutes by CVD (chemical vapor deposition). comprising an oxide film is formed but, further heat-treated for 2 hours at a temperature 1100 ° C., to form a P ⁺ -type highly-doped layer 17 contiguous to the P ⁺ -type highly-doped layer 9.

Next, as shown in FIG. 2 (i), a silicon oxide film 18 is further formed on the side walls of the isolation trenches 6, 7, 8 in which the P ⁺ type high concentration layer 17 is formed by thermal oxidation.

Next, as shown in FIG.
D, polycrystalline silicon 19 is deposited on the silicon oxide films 13 and 18 to fill the isolation trenches 6, 7, and 8.

Then, as shown in FIG. 2K, excess polycrystalline silicon on the surface of the element-side substrate 1 is polished to flatten the surface.

The dielectric isolation type semiconductor substrate formed as described above is provided with a high breakdown voltage lateral IGB by a known method.
By forming T4 and the control circuit 5, the semiconductor device of the present invention shown in FIG. 1 is obtained.

[0033]

As described above in detail, according to the present invention, even if the ion implantation amount of boron is increased, no crystal defect occurs in the dielectric isolation substrate, and the resistance value of the P ⁺ -type high concentration layer is reduced. A low semiconductor element can be obtained. As a result, a high breakdown voltage horizontal IG
The electrical characteristics and reliability of a semiconductor device such as BT can be improved, and the yield can be improved and the cost can be reduced.

[Brief description of the drawings]

FIG. 1 is an element sectional view showing one embodiment of a semiconductor device of the present invention.

FIG. 2 is an element cross-sectional view illustrating steps of the method for manufacturing the semiconductor device illustrated in FIG. 1;

[Explanation of symbols]

REFERENCE SIGNS LIST 1 element side silicon wafer 2 silicon oxide film 3 table side silicon wafer 4 high breakdown voltage lateral IGBT 5 control circuit 6 separation groove 7 separation groove 8 separation groove 9 P ⁺ type high concentration layer 9 a P ⁺ type high concentration layer 9 b P ⁺ type height Concentration layer 11 Silicon oxide film 12 Silicon oxide film 13 Silicon oxide film 14 Separation groove forming part 15 Separation groove forming part 16 Separation groove forming part 17 P ⁺ type high concentration layer 18 Silicon oxide film 19 Polycrystalline silicon

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/762 H01L 27/12 H01L 29/78

Claims (1)

(57) [Claims] A first semiconductor substrate having an active region in which at least one lateral insulated gate bipolar transistor is formed; and a region in the active region including a portion in contact with the first semiconductor oxide film. , 1.5 × 10 ¹⁵ / cm ² to 3 × 1
A predetermined conductivity type high-concentration layer into which boron having a dose amount in the range of 0 ¹⁵ / cm ² is ion-implanted; a second semiconductor oxide film formed on the high-concentration layer; A second semiconductor substrate that is bonded to the oxide film and supports the first semiconductor substrate.