JP2001230392A - Manufacturing method of silicon-on-insulator wafer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To offer a manufacturing method of N Silicon-on-Insulator(SOI) wafer comprising a shallow heavily doped layer of N-type impurities while restraining diffusion of the heavily doped layer of N-type impurities caused by the heat treatments during a device processing step and a step of manufacturing the N+SOI wafers. SOLUTION: In this manufacturing method of silicon-on-insulator(SOI) wafer, a silicon wafer 11 on an active layer side and a silicon wafer 12 on a supporting substrate side as a base supporting the silicon wafer 11 are bonded into one body by a direct bonding method. A heavily doped of layer N-type impurity 13 is formed on a surface of the bonding side of the wafer 12 on the supporting substrate side. After that, oxide films 14 and 15 are formed on a mirror surface of the bonding side of at least one of the two wafers. The two wafers are bonded through the oxide films 14 and 15, thereby manufacturing the SOI wafers.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to SOI (Silicon).
On Insulator) The method of manufacturing a wafer, especially N
The present invention relates to a method for manufacturing an SOI wafer on which a high-concentration buried layer of a type impurity is formed.

[0002]

2. Description of the Related Art Conventionally, there is an SOI wafer (hereinafter, referred to as an N ⁺ SOI wafer) in which a high concentration layer of an N-type impurity is buried. A process for manufacturing an N ⁺ SOI wafer according to this conventional technique will be described with reference to a cross-sectional view of FIG. First, an active layer-side silicon wafer 1 on which devices are to be formed and a support substrate-side silicon wafer 2 that supports the active layer-side silicon wafer 2
Is prepared, and a high-concentration layer 3 of an N-type impurity is formed on the bonding-side surface of the active-layer-side silicon wafer 1 by ion implantation of phosphorus or arsenic (FIG. 4A). The silicon wafer used is, for example, both the active layer and the support substrate side,
6 inch, N type, resistivity 5-10Ω · cm, thickness 625μ
m is used. Then, this active layer side silicon wafer 1
And the supporting substrate-side silicon wafer 2 that supports it and serves as a base is thermally oxidized at 1100 ° C. to 1200 ° C. for 2 to 3 hours, so that silicon oxide films 4 and 5 ( Hereinafter, an oxide film is formed (FIG. 4B). Next, both silicon wafers are bonded by a direct bonding method,
A heat treatment (bonding annealing) is performed for more than an hour to complete a bonded wafer in which both the active wafer 1 and the support substrate wafer 2 are integrated (FIG. 4C).

The above-mentioned heat treatment is performed in an oxidizing atmosphere to form an isolation oxide film 6 in which the oxide films 4 and 5 are adhered to each other. Oxide films 4 and 5 are formed respectively. Finally, the active layer side wafer 1 of the bonded wafer is removed from the active layer side oxide film 4 by grinding and mirror polishing, and the active layer is formed to a desired thickness, for example, in the range of 5 to 20 μm (including the high concentration layer 3), and the N-type impurity high-concentration layer 3 is formed.
^{+ The} SOI wafer is completed (FIG. 4D). FIG.
A semiconductor device (horizontal diode) in which various devices are formed in an active layer using the completed N ⁺ SOI wafer
1 shows a cross-sectional structure of FIG. As the configuration of this lateral diode, an N ⁺ SOI wafer on which an active layer is formed via an isolation oxide film 106 on a supporting substrate 102 is used.
Low concentration N ⁻ type base layer 101 as an active layer (concentration:
5 × 10 ¹³ atoms / cm ³ ) P-type base region 1 on the surface
10 (concentration: 5 × 10 ¹⁷ atoms / cm ³ ) and an N-type buffer region 111 (concentration: up to 5 × 10 ¹⁷ atoms / cm ³ ) are selectively formed. Further, these P-type base regions 110 have a high-concentration P ⁺ -type region 112 (concentration: 5 × 10
¹⁹ atoms / cm ³ ), and a high concentration N ⁺ type region 113 (concentration: 1 × 10 ¹⁹ atoms / cm 3)
³ ) are formed, and an aluminum (Al) anode electrode 115 or a cathode electrode 116 is connected to the P-type base region through a contact hole formed by a silicon oxide film (insulating film) 114 for each of these regions. 110, P ⁺ type region 112 and N ⁺ type region 113 are in contact with each other.

A P ⁺ type region 112 and an N ⁺ type region 11
LOCOS (Local O) that separates each element
xidation of Silicon) films 117 and 118 are selectively formed, and a trench 119 in which polysilicon is buried is formed between the LOCOS film 118 and the isolation oxide film 106.

[0005]

[SUMMARY OF THE INVENTION However, N ⁺ SOI wafer according to the conventional method, the active layer side wafer bonding surface to become on the relationship between form a high concentration layer of N-type impurities to a mirror, N + ^SOI wafer Formed on the active layer side by adhesive annealing in the manufacturing process of the above, and heat treatments such as well diffusion and base diffusion in the device manufacturing process.
The thickness of the high-concentration layer of the mold impurity is increased by diffusion. For this reason, the electrical characteristics (withstand voltage) of a semiconductor element in which various semiconductor devices are manufactured using an N ⁺ SOI wafer
Has been greatly reduced. The present invention has been made in view of the above problems, and has been made in consideration of N ⁺ SO
The diffusion of the high concentration layer of the N-type impurity in each heat treatment in the manufacturing process of the I-wafer and the device process is suppressed, and the N-type impurity having a shallow N-type impurity high-concentration layer on the bottom surface of the SOI layer of the SOI wafer.
⁺ To provide a method for manufacturing an SOI wafer.

[0006]

In order to achieve the above-mentioned object, a method of manufacturing an SOI wafer according to the present invention comprises directly forming an active-layer-side silicon wafer and a supporting-substrate-side silicon wafer that supports the active-layer-side silicon wafer. In the method for manufacturing a bonded SOI wafer which is bonded and integrated by a bonding method, a high concentration layer of N-type impurities is formed on a surface to be a bonding surface side of a support substrate side wafer, and then an oxide film is formed on at least one of the wafer bonding surfaces. Is formed, and both wafers are bonded to each other via the oxide film. When an oxide film is formed on each of the bonding surfaces of the two wafers, the oxide film formed on the active-layer-side silicon wafer is thinner than the oxide film formed on the support-substrate-side silicon wafer.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a method for manufacturing an SOI wafer according to the present invention will be described with reference to the drawings. The silicon wafer used in each of the embodiments is, for example, 6 inches, N-type, having a resistivity of 5 to 10 Ω · cm and a thickness of 6
25 μm is used. (First Embodiment) FIG. 1 is a sectional view of each of the steps (a) to (d) according to a first embodiment of the present invention. First, an active layer-side silicon wafer 11 for forming devices and a support substrate-side silicon wafer 12 that supports the active layer-side silicon wafer 12 are prepared. Injection (dose amount 1.
After 3 × 10 ¹² / cm ² , 50 KeV, an annealing process (800 ° C., 30 minutes) is performed to form a high concentration layer 13 of N-type impurities (FIG. 1A). Next, a silicon oxide film having a thickness of 0.05 to 0.1 μm is formed on the mirror surface on the bonding surface side of the silicon wafer 11 on the active layer side by a thermal oxidation method. Similarly, a 1 μm silicon oxide film is formed on the bonding-side mirror surface of the support substrate side silicon wafer 12 by a thermal oxidation method, so that the silicon oxide film 1 is formed on both wafers.
4 and 15 are formed (FIG. 1B).

Next, the silicon oxide films 14 and 15 of these two wafers are brought into close contact with each other,
Heat treatment (bonding annealing) is performed for 2 to 5 hours, and a bonded wafer in which both the active layer side wafer 11 and the support substrate side wafer 12 are directly bonded to each other is obtained (FIG. 1C). The heat treatment by the direct bonding method is performed in an oxidizing atmosphere, and oxide films 17 and 18 are formed on the upper side (back side) of the active layer side silicon wafer 11 and the lower side (back side) of the support substrate side silicon wafer 12, respectively. At the same time, an isolation oxide film 16 in which the oxide films 14 and 15 are bonded to each other is formed on the bonding surface. At this time,
The oxide film 18 formed below the supporting substrate side silicon wafer 12 has a function of correcting the warpage of the N ⁺ SOI wafer. Further, as shown in FIG. 1C, the high-concentration layer 13 of the N-type impurity is diffused and spread by the adhesion annealing, and is also diffused above the isolation oxide film 16 (on the side of the active layer), thereby increasing the concentration of the N-type impurity. A concentration layer 19 is newly formed. Lastly, the active layer side silicon wafer 11 of the bonded wafer is removed by grinding, and mirror polishing is further performed to finish the active layer 11 'to a thickness of 15 μm.
N ⁺ S in which the thickness of the isolation oxide film 16 is 1.05 to 1.1 μm and the thickness of the high concentration layer 19 of N-type impurity is 1.4 μm.
The OI wafer is completed.

Next, when a semiconductor device (horizontal diode) shown in FIG. 5 was manufactured on the completed N ⁺ SOI wafer, as shown in an embodiment (1) of FIG. The thickness was 3.3 μm, and the withstand voltage was 510 V, and good withstand voltage characteristics were obtained. Also,
Using the conventional method, the same specifications as the first embodiment (impurity: phosphorus, dose of ion implantation: 1.3 × 10 ¹² /
When an N ⁺ SOI wafer was manufactured at a pressure of 50 cm2 (cm ² , 50 KeV), the thickness of the high-concentration layer of the impurity was 4.5 μm, as shown in Comparative Example (1) in FIG. The concentration layer thickness increased to 9.8 μm. As a result, the breakdown voltage of the device was also reduced to 360V. Further, in the first embodiment, the impurity for forming the high concentration layer is replaced with phosphorus, and arsenic ion implantation (dose amount: 1.3 × 10 ¹² / cm ² , 50 KeV) is used, and the same specification of N is used. ⁺ SOI wafer (SOI thickness 15 μm /
In the case where an isolation oxide film thickness of 1.05 to 1.1 μm) is formed, as shown in a modification of the embodiment (1) in FIG. showed that. Further, the thickness of the high concentration layer when the semiconductor element (device) was completed was 1.4 μm, and a good withstand voltage result of 590 V was obtained. Therefore, no decrease in the breakdown voltage due to the change of the impurity from phosphorus to arsenic was observed.

The conventional method (impurity: arsenic, ion implantation dose: 1.3 × 10 ¹² / c)
When an N ⁺ SOI wafer (m ² , 50 KeV) was produced, the thickness of the high-concentration layer of the impurity was 2.4 μm as shown in a comparative example (1) modification of FIG. Further, the thickness of the high concentration layer at the time of completion of the semiconductor element (device) is 3.7 μm.
And the withstand voltage of the element also dropped to 420 V, and a sufficient withstand voltage could not be obtained. (Second Embodiment) FIGS. 2A to 2D show steps (a) to (d) according to a second embodiment, and the separation oxide film formed on the bonding surface is only the silicon wafer on the support substrate side. Then, both wafers are directly bonded by a bonding method to be integrated. First, an active layer-side silicon wafer 11 for forming devices and a support substrate-side silicon wafer 12 that supports the active layer-side silicon wafer 12 are prepared. Implantation (dose amount: 1.3 × 10 ¹² / cm ² , 5
(0 KeV) and post-treatment (800 ° C., 30 minutes) to form a high concentration layer 13 of N-type impurities (FIG. 2A). Next, an oxide film of 1 μm is formed on the mirror surface on the bonding surface side of the silicon wafer 12 on the support substrate side by a thermal oxidation method, and an isolation oxide film 14 is formed (FIG. 2B). This isolation oxide film 14 contains a large amount of phosphorus.

Next, these two wafers 11, 12
And a heat treatment (adhesion annealing) at 1000 to 1100 ° C. for 1 to 2 hours is performed to form a bonded wafer in which both the active layer side wafer 11 and the support substrate side wafer 12 are bonded directly by a bonding method, and separation oxidation is performed. Phosphorus in the film diffuses into the wafer on the active layer side, and an N-type high concentration layer 19 is newly formed (FIG. 2C). The heat treatment by the direct bonding method is performed in an oxidizing atmosphere, and an oxide film 17, an upper surface (back surface) of the active layer side silicon wafer 11 and a lower surface (back surface) of the support substrate side silicon wafer 12 are respectively provided.
18 are formed. Finally, the silicon wafer 11 on the active layer side of the bonded wafer is removed by grinding, and mirror polishing is performed to reduce the thickness of the active layer 11 ′ to 15 μm.
m, and the thickness of the isolation oxide film 14 is 1 μm.
m, the thickness of the N-type impurity high concentration layer 19 is 0.8 to 1.0.
An N ⁺ SOI wafer of μm is completed. Then
Using the completed N ⁺ SOI wafer, a semiconductor device (horizontal diode) shown in FIG. 5 was manufactured. As shown in the embodiment (2) of FIG. 6, the thickness of the N-type impurity was 3.3.
μm, and the withstand voltage at this time was 510 V, and good withstand voltage characteristics could be obtained.

(Third Embodiment) FIG. 3 shows a third embodiment of the present invention.
4A to 4D show the steps (a) to (d) according to the embodiment.
In each of the embodiments described above, the high-concentration layer of the N-type impurity formed on the silicon wafer on the support substrate side uses an ion implantation method. In the third embodiment, a solid phase diffusion method is used. . First, an active-layer-side silicon wafer 11 for forming a device and a support-substrate-side silicon wafer 12 that supports the active-substrate-side silicon wafer are prepared. Diffusion (Tokyo Oka antimony coating material: 1180 ° C, 60
) To form an N-type impurity high concentration layer 13 (FIG. 3A). Next, 1 μm was applied to the mirror surface on the bonding surface side of the support substrate side silicon wafer 22 by the combustion oxidation method of oxygen and hydrogen.
An oxide film 25 of m is formed. On the mirror surface on the bonding surface side of the active layer side silicon wafer 21, 0.01 μm is also applied by a thermal oxidation method.
An oxide film 24 having a thickness of m is formed (FIG. 3B). Next, both of these wafers are brought into close contact with the silicon oxide films 24 and 25, and heat treatment (adhesion annealing) is performed at 1150 to 1250 ° C. for 2 to 5 hours. Is obtained by directly bonding the wafers by the bonding method (FIG. 3C).

The heat treatment by the direct bonding method is performed in an oxidizing atmosphere, and is performed on the upper side (back side) of the silicon wafer 21 on the active layer side.
And the lower side (back side) of the silicon wafer 22 on the support substrate side
, Silicon oxide films 27 and 28 are respectively formed, and an isolation oxide film 26 in which the silicon oxide films 24 and 25 are integrated with each other is formed on the bonding surface. This isolation oxide film 26 contains a large amount of antimony.
As shown in FIG. 3C, the high-concentration layer 29 of the N-type impurity is newly formed by diffusing into the active layer side wafer by adhesion annealing. Finally, the active layer-side silicon wafer 21 of the bonded wafer is removed by grinding, and furthermore, mirror polishing is performed to finish the active layer 21 ′ to a thickness of 15 μm, and the thickness of the isolation oxide film 16 is reduced. 1.01μ
An N ⁺ SOI wafer in which the thickness of the high concentration layer 19 of m and N type impurities is 0.9 μm is completed. Next, when the semiconductor device (horizontal diode) shown in FIG. 5 was manufactured using the completed N ⁺ SOI wafer, the thickness of the N-type impurity high-concentration layer 19 was reduced as shown in the embodiment (3) of FIG. 2.8 μm, the withstand voltage was 540 V, and good results were obtained. Also, using the conventional method, this third
Of the same specifications (solid phase diffusion of antimony (antimony coating material manufactured by Tokyo Ohka: 1180 ° C., 60 minutes)), as shown in Comparative Example (3), the thickness of the high-concentration layer of the N-type impurity Was increased to 6.2 μm, and as a result, the withstand voltage of the element was also reduced to 360 V.

[0014]

As described above, the SO according to the present invention can be used.
According to the method of manufacturing the I wafer, the thickness of the high concentration layer of the N-type impurity formed on the active layer side can be reduced. As a result, the electrical characteristics (withstand voltage) of the semiconductor element manufactured using this SOI wafer can be greatly improved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a manufacturing process of an SOI wafer according to a first embodiment of the present invention.

FIG. 2 is a sectional view illustrating a manufacturing process of an SOI wafer according to a second embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating a manufacturing process of an SOI wafer according to a third embodiment of the present invention.

FIG. 4 is a sectional view showing a manufacturing process of an SOI wafer according to a conventional method.

FIG. 5 is a cross-sectional view illustrating a structure of a semiconductor element (horizontal diode) manufactured using an SOI wafer.

FIG. 6 is a diagram showing a measurement result of an N ⁺ layer thickness and an electric characteristic (breakdown voltage) result of an SOI wafer according to an embodiment of the present invention and a conventional method (comparative example).

[Explanation of symbols]

1, 11, 21 ... Active layer side silicon wafer 2, 12, 22 ... Support substrate side silicon wafer 3, 13, 19, 23, 29 ... N-type impurity high concentration layer 4, 5, 14, 15, 16, 17 , 18, 24, 25,
27, 29 ... oxide film

Claims (2)

[Claims] An SOI wafer manufacturing method in which an active layer-side silicon wafer and a support substrate-side silicon wafer that supports the active layer and serve as a base are bonded and integrated by a direct bonding method. N on the surface side
A method for manufacturing an SOI wafer, comprising forming an oxide film on at least one wafer bonding surface after forming a high-concentration layer of a mold impurity, and bonding both wafers together via the oxide film. 2. An oxide film formed on an active layer side silicon wafer having a smaller thickness than an oxide film formed on a support substrate side silicon wafer when an oxide film is formed on each of the bonding surfaces of both wafers. 2. The method according to claim 1, wherein
The manufacturing method of the SOI wafer described in the above.