JP3237277B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which bipolar transistors are integrated.

[0002]

2. Description of the Related Art Conventionally, in a bipolar IC in which bipolar transistors are integrated, as shown in FIG.
It is common practice to insulate and separate a bipolar transistor (NPN transistor) by bonding. However, there is a disadvantage that the element size of the bipolar transistor is large in order to prevent a decrease in breakdown voltage. That is, FIG.
As shown in the plan view of FIG. 1, in order to reduce the element size, it is necessary to reduce the distance W from the separation part.
As shown in FIG. 2, when the distance W to the separation portion is reduced, there is a disadvantage that the withstand voltage is reduced.

[0003] Therefore, as shown in FIG.
A silicon substrate 32 is disposed thereon, the silicon substrate 32 is formed in an island shape, an insulating film 33 is formed around the island, and a bipolar transistor (NPN transistor) is formed in the island. By doing so, as shown in the plan view of FIG. 14, the element size can be reduced while maintaining the breakdown voltage.

[0004]

However, when a bipolar transistor is insulated and separated as shown in FIG. 13, the switching time of the transistor is reduced.

It is an object of the present invention to provide a semiconductor device which does not degrade the switching speed of the transistor while reducing the size of the high breakdown voltage bipolar transistor.

[0006]

According to the present invention, there is provided a silicon substrate, wherein the silicon substrate is disposed on the silicon substrate via an insulating film,
An island in which a first-conductivity-type low-concentration silicon layer is formed on a first-conductivity-type high-concentration silicon layer; an insulating layer formed in an outer peripheral portion of the island; A base region of a second conductivity type formed in the low concentration silicon layer, a first conductivity type emitter region formed in the low concentration silicon layer of the first conductivity type of the island, and a low conductivity type of the first conductivity type of the island. a collector region of a first conductivity type formed in concentration silicon layer, the sidewalls of the trench isolation unit in contact with Oite said insulating layer on said island <br/>
A diffusion region for carrier recombination of the second conductivity type formed for the carrier recombination formed on the second conductive type;
The diffusion region for coupling is formed so as to face the insulating layer.
The gist of the present invention is a semiconductor device including the formed potential variable section .

[0007]

The excess carriers quickly recombine with the carriers in the carrier recombination diffusion region when the transistor is switched.

[0008]

EXAMPLES (First Embodiment) will be described below with reference to the drawings an embodiment which embodies the relevant aspect of the present invention.

FIG. 1 is a sectional view of a semiconductor device according to this embodiment. 2 to 4 show the manufacturing steps. To explain the manufacturing process, as shown in FIG. 2, it is mirror-polished N ^-
A silicon substrate 1 is prepared, and antimony is diffused 3 μm into the surface of the silicon substrate 1 using a vapor phase diffusion method to form an N ⁺ layer 2. Further, a diffusion region 3 for P ⁺ carrier recombination shallower than the N ⁺ layer 2 is formed on the surface of the N ^- silicon substrate 1 by using a vapor phase diffusion method.
To form Separately, one principal surface of the P ^- silicon substrate 4 is mirror-polished and then thermally oxidized to form a silicon oxide film 5 having a thickness of 1 μm. Then, the two substrates 1 and 4 are bonded together in a clean atmosphere, and heated to about 1100 ° C. for bonding.

Further, the N ^- silicon substrate 1 is polished by polishing.
Is polished to make the N ^- silicon substrate 1 thinner. As a result, a so-called SOI substrate is formed in which the P ⁺ carrier recombination diffusion region 3 is provided on the silicon oxide film 5, the N ⁺ layer 2 is provided thereon, and the N ⁻ layer 6 is provided thereon. .

Next, as shown in FIG.
, A field oxide film 8, a silicon nitride film, and a silicon oxide film as a mask are sequentially formed. Then, in the thin region of the field oxide film 8, the field oxide film 8, the silicon nitride film and the silicon oxide film are selectively etched to form openings, and then the silicon substrate 1 is separated from the openings by etching. A groove (trench) is formed. Then, after an insulating film (silicon oxide film 9) is formed on the inner wall surface of the separation groove, polycrystalline silicon 10 is filled in the separation groove. Furthermore, the polycrystalline silicon 10 deposited on the oxidation film upon the filling of the polycrystalline silicon 10 is etched back. Subsequently, the silicon oxide film as a mask is removed by etching, and finally, the silicon nitride film is removed by etching.
The silicon substrate 1 is completely electrically separated by the isolation groove and the insulating film (silicon oxide film 9) by forming an oxide film on the upper surface of the substrate.

Here, the silicon oxide film 9 is formed on the outer periphery of the island 7 formed by such a trench. Next, as shown in FIG. 4, each diffusion region is formed in the island 7. In other words, the P ⁺ base region 1 is formed by a photolithography process, an ion implantation process, and a diffusion process that are often used in the related art.
1 and an N ⁺ emitter region 12 and N ⁺
An N ⁺ collector region 13 reaching the layer 2 is formed.

Finally, a contact hole is formed in the oxide film 8 to form an electrode wiring made of aluminum or the like, whereby the bipolar integrated circuit of FIG. 1 is manufactured. Here, a silicon oxide film 5 (buried insulating film) is formed on the silicon substrate 4, and the silicon oxide film 9 insulates the element portion from the substrate 4 in a trench state from the substrate surface. In this example, the cavity formed in the trench is filled with polycrystalline silicon 10 for protection.

In the figure, E, B and C are emitters, respectively.
Abbreviation for base and collector. A metal electrode of aluminum or the like is disposed on the outermost surface, and the electrode is formed on a contact hole provided in an electrode forming portion of the oxide film 9 which is a protective insulating layer on the substrate surface.

Next, the operation will be described. Transistor when switched on → off, significant improvement in switching speed is achieved because the excess carriers that were in the collector perform rapidly carrier and carrier recombination re binding diffusion region 3.

Although the embodiment has been described with reference to an NPN transistor, a PNP transistor may be embodied. Thus, in this embodiment, the silicon substrate 4
It is disposed on a silicon substrate 4 with a silicon oxide film 5 (insulating film) interposed therebetween, and an N ⁻ layer 6 (a first-conductivity-type low-concentration silicon) is formed on an N ⁺ layer 2 (a first-conductivity-type high-concentration silicon layer). layer)
, A silicon oxide film 9 (insulating layer) formed on the outer periphery of the island 7, and a P ⁺ base region 11 (base of the second conductivity type) formed on the N ⁻ layer 6 of the island 7. a region), the island 7 N ^- the layer 6 N ⁺ emitter region 12 formed in the (emitter region of the first conductivity type), N island 7 ^- N are formed in the layer 6 ⁺ collector region 13 (first Conductive collector area)
When, and a P ⁺ carrier recombination diffusion region 3 for carrier recombination formed in the island 7 (carrier recombination diffusion region of the second conductivity type). Therefore, during switching of the transistor, excess carriers quickly recombine with carriers in the P ⁺ carrier recombination diffusion region 3. As a result, the switching speed of the high breakdown voltage bipolar transistor is not deteriorated while the transistor is downsized. Second Embodiment Next, an embodiment of the present invention will be described with reference to an embodiment (the
The following description focuses on differences from the first embodiment .

FIG. 5 is a sectional view of the semiconductor device of this embodiment. The manufacturing process will be described with reference to FIGS.
The manufacturing process will be described. As shown in FIG. 6, an N ^- silicon substrate 14 having a mirror-polished surface is prepared, and N ⁺ layer 15 is formed by diffusing antimony by 3 μm using a gas phase diffusion method. Separately, one principal surface of the P ^- silicon substrate 16 is mirror-polished, and then thermally oxidized to form a silicon oxide film 17 (insulating film) having a thickness of 1 μm. Then, the two substrates 14 and 16 are bonded together in a clean atmosphere,
Heat to 0 ° C to join.

Further, N ^- silicon substrate 1 is polished.
4 is polished to make the N ^- silicon substrate 14 thinner. As a result, there is an N ⁺ layer 15 on the silicon oxide film 17 and an N ⁻ layer 18 on the N ⁺ layer 15.
An I substrate is formed.

Next, as shown in FIG.
Island 6 formed by a trench over silicon oxide film 17 via silicon oxide film 17
9 is formed. That is, a field oxide film 20 of about 0.5 μm is formed on the surface by thermal oxidation. LPCVD on it
A nitride film is formed to a thickness of about 0.1 μm by the method. A resist is applied to the nitride film. Further, a silicon oxide film 17 (buried insulating layer) is formed at a location to be an insulating portion around the element (island 19) by plasma etching using a fluorine-based etching gas, hydrofluoric acid etching, and reactive ion etching using a fluorine-based etching gas. ) Is formed.

P-type impurities (for example, boron) are diffused from the side walls of the trench 21 to form a P ⁺ carrier recombination diffusion region 22. Then, as shown in FIG. 8, sheet to form a silicon oxide film 23 (insulating layer) by oxidizing the surface of the trench 21, the remaining hollow portion LPCVD
Is filled with polycrystalline silicon 24 (potential variable portion) by a method. After forming an oxide film also on the polycrystalline silicon 24, the nitride film is removed by dry etching.

Here, the silicon oxide film 23 is formed on the outer periphery of the island 19. Next, as shown in FIG. 9, each diffusion region is formed in the island 19. That is, the P ⁺ base region 25 is formed by a photolithography process, an ion implantation process, and a diffusion process that are often used in the past, and the N ⁺ emitter region 26 and the N ⁺ connector region 27
To form

Finally, a contact hole is formed in the oxide film 20 and an electrode wiring is formed, thereby manufacturing the bipolar integrated circuit shown in FIG. Next, the operation will be described.

The diffusion region 22 for P ⁺ carrier recombination is P ⁺
In order to prevent the switching speed (particularly, turn-off time) from being reduced by electrons excessively injected into the base region 25,
It is formed on the side wall of the trench element isolation part. By supplying the holes which are majority carriers in the P ⁺ carrier recombination diffusion region 22 to the P ⁺ base region 25, to neutralize the excess electrons in the P ⁺ base region 25.

Also, by changing the potential of the polycrystalline silicon 24, the potential of the P ⁺ carrier recombination diffusion region 22 can be changed by the effect of the capacitor via the element isolation silicon oxide film 23. When the polycrystalline silicon 24 to a positive potential P ⁺ carrier recombination diffusion region 22 becomes a negative potential, the same effect can be obtained as that a ground potential, temporarily P ⁺ carrier recombination diffusion region 22
More effectively the P ⁺ base region the accumulated halls in
25 can also be injected.

The P ⁺ carrier recombination diffusion region 22 may be formed by ion implantation and annealing from the silicon surface after forming the trench.

[0026]

As described in detail above, according to the present invention,
An excellent effect of reducing the switching speed of the transistor while reducing the size of the high breakdown voltage bipolar transistor is exhibited.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device according to a first embodiment.

FIG. 2 is a cross-sectional view illustrating a manufacturing process of the semiconductor device.

FIG. 3 is a sectional view illustrating a manufacturing process of the semiconductor device.

FIG. 4 is a cross-sectional view illustrating a manufacturing process of the semiconductor device.

FIG. 5 is a sectional view of a semiconductor device according to a second embodiment.

FIG. 6 is a cross-sectional view showing a manufacturing step of the semiconductor device.

FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device.

FIG. 8 is a sectional view illustrating a manufacturing process of the semiconductor device.

FIG. 9 is a cross-sectional view illustrating a manufacturing step of the semiconductor device.

FIG. 10 is a cross-sectional view of a conventional semiconductor device.

FIG. 11 is a plan view of a conventional semiconductor device.

FIG. 12 is a characteristic diagram showing a withstand voltage and a distance between a separation unit.

FIG. 13 is a sectional view of a conventional semiconductor device.

FIG. 14 is a plan view of a conventional semiconductor device.

[Description of Signs] 15 N ⁺ layer (first-conductivity-type high-concentration silicon layer) 22 P ⁺ diffusion region for carrier recombination (diffusion region for carrier recombination of second conductivity type) 14 silicon substrate 17 silicon oxide film ( 18 N ⁻ layer (low-concentration silicon layer of first conductivity type) 19 island 23 silicon oxide film (insulation layer) 25 P ⁺ base region (base region of second conductivity type) 26 N ⁺ emitter region (first Conductive emitter region) 27 N ⁺ collector region (first conductive collector region) 24 Polycrystalline silicon (variable potential portion)

Continuation of the front page (72) Inventor Yoshihiko Isobe 1-1, Showa-cho, Kariya-shi, Aichi Japan Denso Co., Ltd. (56) References JP-A-3-284872 (JP, A) JP-A-4-506588 (JP) , A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 29/73-29/735 H01L 21/331

Claims (1)

(57) [Claims] A silicon substrate, an island having a first conductivity type low-concentration silicon layer formed on a first conductivity type high-concentration silicon layer, and an island disposed on the silicon substrate via an insulating film; An insulating layer formed on an outer peripheral portion of the island; a second conductivity type base region formed on a first conductivity type low concentration silicon layer of the island; and a first conductivity type low concentration silicon layer of the island an emitter region of the first conductivity type formed in the collector region of the first conductivity type formed in the low concentration silicon layer of a first conductivity type of the island, trench in contact with Oite said insulating layer on said island Separation
A second conductivity type carrier recombination diffusion region for carrier recombination formed on the side wall parts, the insulation and the second conductive type carrier recombination diffusion region
A semiconductor device, comprising: a potential variable portion formed to face each other with a layer interposed therebetween .