JPS61172346A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the parasitic capacity to be formed between the semiconductor substrate and the semiconductor layer in a semiconductor integrated circuit device and to contrive to enhance the operating speed of the device to a higher speed by a method wherein an isolation structure is constituted by the cavity part, which is provided in the interposing part between the semiconductor substrate and the semiconductor layer. CONSTITUTION:A semiconductor layer 6 is provided on the upper part of a semiconduc tor substrate 5 making a cavity part 7 and an insulating film 8 interpose between the semiconductor layer 6 and the semiconductor substrate 5. The semiconductor layer 6 constitutes an npn type bipolar transistor, for example. Moreover, the semicon ductor layer 6 is provided on the upper part of the semiconductor substrate 5 making the cavity part 7 having gas (air, inactive gas and so forth) with a smaller specific inductivity compared to the semiconductor substrate 5 and the insulating film 8 inter pose between the semiconductor layer 6 and the semiconductor substrate 5 and is constituted in such a way that the parasitic capacity to be added becomes smaller. By providing the cavity part 7 in such a way, the parasitic capacity to be formed between the semiconductor substrate 5 and the semiconductor layer 6 can be reduced, thereby enabling to contrive to enhance the operating speed of the semiconductor integrated circuit device to a higher speed.

Description

Detailed Description of the Invention [Technical Field] The present invention relates to a semiconductor integrated circuit device, and in particular, a technique that is effective when applied to a semiconductor integrated circuit device having an isolation structure that electrically isolates semiconductor elements. It is related to.

[Background Art] For example, the isolation structure of a semiconductor integrated circuit device having a bipolar transistor uses a pn junction isolation technique as shown in FIG. That is, an epitaxially grown n-type semiconductor layer 2 constituting a semiconductor element is provided on the top of a p-type semiconductor substrate l, and the semiconductor layer 2 is separated by the semiconductor substrate 1 and the p-type semiconductor region 3. ing.

In such an isolation structure, a large parasitic capacitance is formed at the pn junction between the semiconductor layer 2, the semiconductor substrate 1, and the semiconductor region 3, so that it is impossible to increase the operating speed. Further, since a reverse bias is applied between the semiconductor layer 2 and the semiconductor region 3 to ensure electrical isolation, the depletion layer formed at the pn junction portion between them increases.

Therefore, a margin is required to prevent short-circuiting between semiconductor elements due to punch-through, which increases the area occupied by the isolation structure and reduces the degree of integration of the semiconductor integrated circuit device.

Therefore, as shown in FIG. 8, an isolation structure is used which is composed of an insulating film 4 formed by selective oxidation of silicon and a semiconductor substrate 1. In this isolation structure, since the dielectric constant of the insulating film 4 is smaller than that of the semiconductor region 3, the parasitic capacitance added to the semiconductor layer 2 can be reduced and the operating speed can be increased. Further, since no depletion layer is formed in the insulating film 4, the area occupied by the isolation structure can be reduced, and a decrease in the degree of integration of the semiconductor integrated circuit device can be suppressed.

However, in such a separation structure, the semiconductor substrate 1
Since a parasitic capacitance is formed at the pn junction between the semiconductor layer 2 and the semiconductor layer 2, there is a problem that the operating speed of the semiconductor integrated circuit device cannot be sufficiently increased.

[Object of the Invention] An object of the present invention is to provide a technique that can reduce the parasitic capacitance due to the isolation structure and increase the operating speed in a semiconductor integrated circuit device having an isolation structure.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] Among the inventions disclosed in this application, a brief outline of typical inventions is as follows.

That is, in a semiconductor integrated circuit device in which a semiconductor layer constituting a semiconductor element is provided on an upper part of a semiconductor substrate, a part where the semiconductor element is constituted is separated by a cavity provided in an intervening part between the semiconductor substrate and the semiconductor layer. Configure the structure.

This makes it possible to reduce the parasitic capacitance formed between the semiconductor substrate and the semiconductor layer, thereby increasing the operating speed of the semiconductor integrated circuit device.

Hereinafter, the configuration of the present invention will be explained along with one embodiment.

[Embodiment] FIG. 1 is a plan view of a main part of a semiconductor integrated circuit device having an isolation structure for explaining an embodiment of the present invention, and FIG.
FIG. 2 is a sectional view taken along the section line -■ in FIG. 1;

In addition, in all the figures of the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

In FIGS. 1 and 2, 5 is an n-type semiconductor substrate made of single crystal silicon.

A semiconductor layer 6 is provided on the semiconductor substrate 5 with a cavity 7 and an insulating film 8 interposed therebetween. The semiconductor layer 6 constitutes, for example, an npn type bipolar transistor. The semiconductor layer 6 is
A cavity 7 containing a gas (air, inert gas, etc.) whose dielectric constant is smaller than that of the semiconductor substrate 5, an insulating film, etc. is provided above the semiconductor substrate 5 to reduce the added parasitic capacitance. It is composed of: For example, the semiconductor layer 6 is 1.

A single crystal silicon film formed by epitaxial growth.

A polycrystalline silicon film formed by CVD technology or a single crystallized film of the polycrystalline silicon film is used.

Reference numeral 9 indicates an embedded member, and an insulating WA is provided on the upper part of the semiconductor substrate 5.
10 interposed therebetween. The buried layer 9 is made of a conductive film that constitutes a semiconductor element, a conductive film that electrically connects semiconductor elements, or an insulating film that electrically isolates semiconductor elements.

Reference numeral 11 denotes a groove portion, which is provided at a predetermined portion of the embedded member 9. Reference numeral 12 denotes an insulating film, which is provided so as to bury the upper part of the embedded member 9 and the groove 11 .

The isolation structure electrically isolates the semiconductor layers 6.

Primarily, the cavity 7. Embedded member (in the case of insulating film) 9,
It is composed of a groove portion 11 and an insulating film 12. Note that the separation structure may be configured without providing the embedded member 9.

Next, a specific manufacturing method of this example will be explained.

3 to 6 are sectional views of essential parts of a semiconductor integrated circuit device having a separation structure in each manufacturing process for explaining a manufacturing method according to an embodiment of the present invention.

First, an n-type impurity (for example, P, As) and an n-type impurity (for example, B
) and are introduced respectively. Then, a semiconductor layer 6 formed by epitaxial growth is formed on the semiconductor substrate 5.

By forming the semiconductor layer 6, the impurities are diffused respectively, and a W-type buried layer 10A and a P''-type buried layer 10B are formed in the intervening portion between the semiconductor substrate 5 and the semiconductor layer 6.

After that, as shown in FIG. 3, mask members 13, 14, 1
5 and 16 are formed in sequence.

The mask members 14 and 16 are made of, for example, a silicon oxide film formed by CVD technology so as to serve as an etching mask. For the mask members 13 and 15, silicon nitride films formed by CVD technology are used, for example, so as to serve as masks for heat treatment.

After the step of forming the mask members 13, 14, 15, and 16 shown in FIG. 3, an anisotropic etching technique is applied using the mask member 16 to form a convex shape (rod shape) in which a semiconductor element will be formed.
A semiconductor layer 6 is formed.

This etching step can be performed using, for example, CBrF, CCQ.
Using an etching gas such as No. 4, the buried layer 10A, IOH
It is sufficient to etch it to a depth that reaches . Using this anisotropic etching technique, it is possible to obtain an etching rate difference of about 5:1 to 10:1 between the semiconductor layer 6 and the mask member 16.

After this, the mask member 1 is etched using an isotropic etching technique or the like.
Remove 6.

Then, as shown in FIG. 4, a mask member 17 for heat treatment is formed to cover the sides of the semiconductor layer 6. The mask member 17 is formed by, for example, forming a silicon nitride film with good coverage using a CVD technique, and then applying an anisotropic etching technique to remove the silicon nitride film formed on the flat portion.

After the step of forming the mask member 17 shown in FIG. 4, heat treatment is performed using the mask member 15.
The 0A and IOB portions are oxidized to form an insulating film (for example, boron glass, phosphorus glass) 10 on the upper part of the semiconductor substrate 5 and in the interposed part between the semiconductor substrate 5 and the semiconductor layer 6. Since the buried layers 10A and 10B are formed with a higher impurity concentration than other regions, a faster oxidation rate can be obtained. This processing step is performed by, for example, high-pressure oxidation technology.

Then, using the mask member 14 as an etching stopper,
Remove mask member 15.17.

After this, as shown in FIG. 5, the insulating film 1 between the semiconductor layers 6 is
0, an embedded member 9 is formed on the top. The embedded member 9 is
For example, it is formed by using an anisotropic etching technique using a polycrystalline silicon film formed by CVD technology and a resist film that fills the recesses formed on the polycrystalline silicon film and has approximately the same etching rate. The polycrystalline silicon film may be doped with impurities as necessary and used as a semiconductor element formation region or a wiring formation region.

After the step of forming the embedded member 9 shown in FIG. 5, the mask member 14 is removed.

Then, a mask member 18 for etching is formed on the mask member 13 and the embedded member 9 in order to form the groove portion. For example, a silicon oxide film formed by CVD technology is used as the mask member 1B.

Thereafter, an anisotropic etching technique is applied using a mask member 18 to form a groove 11 that exposes a portion of the insulating film 10 formed by the n-type buried layer 10A, as shown in FIG. . At this time, the groove part 11 is formed so that a part thereof is connected to the embedded member 9 and the semiconductor layer 6 is supported even if a cavity part is formed (see FIG. 1).

After the step of forming the groove portion 11 shown in FIG. 6, the insulating film 10 and the mask member 18 formed of the n-type buried layer 10A are removed to form the cavity portion 7.

The insulating film 10 is etched using an isotropic etching technique using, for example, a hydrofluoric acid aqueous solution so that the etching rate of an N-type impurity is faster than that of a P-type impurity. Remove with .

After that, heat treatment is performed using the mask member 13 to form an insulating film 8 on the exposed semiconductor layer 6 and the semiconductor substrate 5 in the cavity 7, and fill the upper part of the buried member 9 and the groove 11 with the insulating film 8. form 12. Insulating film 12 and insulating film 8
is formed by, for example, a thermal oxidation technique using an H202 atmosphere so that the former film is thicker than the latter.

Then, by removing the mask member 13, the separation structure of this embodiment is almost completed as shown in FIGS. 1 and 2.

Thereafter, a semiconductor element is formed on the semiconductor layer 6, thereby completing the semiconductor integrated circuit device of this embodiment.

Note that the present invention is not limited to the above-mentioned embodiments, but only within the scope of the invention.

Of course, various changes can be made.

For example, in the embodiment described above, the present invention was applied to an example in which the insulating film 10 formed of the n'' type buried layer 10A was formed under the semiconductor layer 6, and the insulating film 10 was removed. Alternatively, an insulating film 10 made of a buried layer 10B may be formed, and then the insulating film 10 may be removed.

Further, in the above embodiments, the present invention can be applied to the n-type buried layer 10.
Although this embodiment has been applied to an example in which A and a p'' type buried layer 10B are formed, any of the buried layers may be formed under the semiconductor layer 6, and the buried layer may be formed in an insulating film.

Further, in the embodiment described above, the present invention is applied to an example in which a bipolar transistor is formed in the semiconductor layer 6, but a semiconductor element such as a resistor element may also be formed.

[Effect] As explained above, according to the present invention, in a semiconductor integrated circuit device in which a semiconductor layer constituting a semiconductor element is provided on an upper part of a semiconductor substrate, the semiconductor substrate and the semiconductor layer in the portion where the semiconductor element is constituted are By providing a cavity between the layers, it is possible to reduce the parasitic capacitance formed between the semiconductor substrate and the semiconductor layer, thereby increasing the operating speed of the semiconductor integrated circuit device. I can do it.

[Brief explanation of the drawing]

1 is a plan view of a main part of a semiconductor integrated circuit device having an isolation structure for explaining one embodiment of the present invention; FIG. 2 is a cross-sectional view taken along the line ■-■ in FIG. 1; 6 to 6 are cross-sectional views of main parts of a semiconductor integrated circuit device having a separation structure in each manufacturing process for explaining a manufacturing method according to an embodiment of the present invention, and FIGS. 7 and 8 are cross-sectional views of a conventional semiconductor integrated circuit device. 1 is a sectional view of a main part of a semiconductor integrated circuit device having a separation structure. In the figure, 5... semiconductor substrate, 6... semiconductor layer, 7...
・Cavity part, 9... Embedded member, 10.12... Insulating film, 1 Figure 1 Figure 2 Figure 3 Figure 5 b(n)! U Figure 6 5(n) 10

Claims (1)

[Claims] 1. In a semiconductor integrated circuit device in which a semiconductor layer constituting a semiconductor element is provided on an upper part of a semiconductor substrate, an intervening portion between the semiconductor substrate and the semiconductor layer where the semiconductor element is constituted, A semiconductor integrated circuit device characterized by having a cavity. 2. The semiconductor integrated circuit device according to claim 1, wherein a plurality of the semiconductor layers are provided spaced apart from each other, and a buried member is provided between the semiconductor layers. 3. The semiconductor integrated circuit device according to claim 2, wherein an insulating film is provided at an intervening portion between the semiconductor substrate and the embedded member. 4. The semiconductor integrated circuit device according to claim 2 or 3, wherein the embedded member is composed of an insulating film or a combination of a conductive layer and an insulating film.