JPS639150A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To manufacture a bipolar type semiconductor device in high integration while shortening the distance between an outer base layer and an outer collector layer by a method wherein a silicon substrate is selectively etching- removed until reacing a barrier collector layer forming insulating layers on the sidewalls of etching-removed part to be filled with silicon. CONSTITUTION:In order to manufacture a semiconductor device including a bipolar type transistor, a silicon substrate is selectively etched until reaching at least a barrier collector layer 23 forming insulating layers 33 on the sidewalls of etching-removed part to be filled with silicon 34. For example, an N type buried layer 23, a P type epitaxial layer 22, an N type well layer 24, oxide films 32, 25, a P type base layer 26, a polycrystalline silicon layer 27, an N type emitter layer 28 and an outer base layer 30 are formed on a P type silicon substrate 21. Next, the silicon substrate 21 is selectively etched until reaching the N type buried layer 23 to form the sidewall oxide films 33. Furthermore, the N type silicon layer 34 is grown by selective epitaxial process etc. and finally interlayer film.interconnection is performed to form a bipolar element.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and is particularly used for a method for manufacturing a bipolar type semiconductor device.

(Prior Art) A conventional method for manufacturing an NPN type bipolar transistor will be explained with reference to FIG. First, a heavily doped N-type buried layer 3 is formed on a P-type (100) substrate 1, a P-plate epitaxial layer 2 with a thickness of about 2Rn is formed, and an N-type well layer 4 is formed by a conventional method. (FIG. 2(a)) Next, an oxide film 12 is formed in the non-element region using a selective oxidation method, an oxide film 5 is formed in the element region, and a P-type base is selectively formed using an ion implantation method. Form layer 6. (FIG. 1(b)) Furthermore, the oxide film 5
A part of the hole is opened and a polycrystalline silicon layer 7 is formed on the entire surface.
Introducing N-type impurities such as arsenic by ion implantation, etc.
A heat treatment is performed to form an N-emitter layer 8. (Figure 1 (
c) ) The polycrystalline silicon layer 7 is formed by photolithography or the like.
is partially etched using the photoresist as a mask, and using the photoresist 9 and the oxide film 12 as masks, a heavily doped P-type external base layer 10 is formed by ion implantation or the like. Furthermore, an N-type high concentration external collector layer 11 is formed by diffusion, ion implantation, or the like. (Figure 1(e)) Furthermore,
A wiring layer is formed using a conventional method.

(Problem to be Solved by the Invention) However, in order to remove the external collector 11, in the conventional technology, methods such as performing N-type impurity diffusion or N-type impurity ion implantation such as POC5 and then performing diffusion are used. use However, since the depth from the silicon surface to the buried collector layer 3 is approximately 1 μm, horizontal diffusion occurs simultaneously with vertical diffusion, so the distance between the external collector layer 1 and the external base layer 10 should be 1 μm or more. I had to. This is extremely disadvantageous for high integration.

The present invention has been made in view of the above-mentioned circumstances, and in particular, in a bipolar 5m semiconductor integrated circuit, by reducing the distance between the external base layer and the external collector layer, a highly integrated bipolar semiconductor device can be manufactured. It is intended to provide a method.

[Structure of the Invention] (Means and Effects for Solving Problems) When forming an external collector, the present invention selectively etches and removes the silicon substrate in the external collector region at least until it reaches the buried collector layer. Next, an insulating film (CVT) Si02 film is applied to the entire surface of the silicon substrate and etched back.
to2 film) is formed, and the etched removed portion of the silicon substrate is filled with, for example, N-type silicon, or after silicon is embedded, it is made into N-type, for example. This enables the external collector layer to contact the external base layer via the insulating film, so that the connection between the external collector layer and the external paste layer is
It can be downsized and has a great effect on higher integration.

(Example) An example of the present invention will be described below with reference to the drawings. 1st
The figure is an explanatory diagram of the process of the same example. Correspondence) above,
N-type buried layer 23 (corresponding to 3 in FIG. 2), P-type epitaxial layer 22 (corresponding to 2), N-type well layer 24 (corresponding to 4), oxide film 32.25 (corresponding to 12.5V?1) , P
Mold base layer 26 (corresponding to 6), polycrystalline silicon layer 27 (
7), N type emitter, 121j (compatible with II),
An external base layer 3o (corresponding to 1o) is formed. Next, the first
As shown in Figure (b), the silicon substrate is selectively etched using photolithography until it reaches at least the N-type buried layer 23, and the entire surface is oxidized using a thermal oxide film or vapor phase growth method. After forming the film, it is etched by anisotropic etching.
Then, a sidewall oxide film 33 is formed. Furthermore, Figure 1 (e
), an N-type silicon 7 layer 34 is grown using a selective epitaxial method or the like. Finally, interlayer films and wiring are formed using normal steps to form a bipolar element.

However, in the prior art shown in FIG. 2, since diffusion was used for the external collector 11, the external collector and the external base layer 1
Since it was necessary to provide a sufficient distance from zero in consideration of lateral diffusion, this was an impediment to high integration. On the other hand, in the present invention shown in FIG. 1, the external collector layer 34 can be brought into contact with the external base layer 30 via the insulating film 33, so that the distance between the external base layer 30 and the external collector layer 34 is reduced. This has a significant effect on high integration.

Note that the present invention is not limited to the above-mentioned embodiments, and can be applied in various ways. For example, in this embodiment, an NPN W ) transistor is taken as an example, but even in the case of a PNP type transistor, the effect remains the same if Nff1 of this embodiment is changed to P type and P type is changed to N type. Further, if the sidewall oxide film 33 is made of a material such as nitride, which has electrical insulating properties and acts as a barrier to impurities, the effect remains unchanged. Furthermore, N-type silicon 3
4 can be formed by etching after depositing polycrystalline silicon without using the selective epitaxial technique, and if it is not only silicon but also a substance that makes ohmic contact with the N-type buried layer 23, the effect will be good. does not change. The Nu silicon layer 34 of this embodiment is made of N
Even if type impurities are added, the effect remains the same.

[Effects of the Invention] As explained above, according to the present invention, the external collector layer can come into contact with the external base layer via the insulating film, so it is possible to reduce the distance between the external base layer and the external collector layer. This has a great effect on high integration.

[Brief explanation of the drawing]

FIG. 1 is a process explanatory diagram of an embodiment of the present invention, and FIG. 2 is a process explanatory diagram of a conventional method for manufacturing a semiconductor device. 21...P type silicon substrate, 22...PM epitaxial layer, 23...N13 buried layer, 24...N
type well layer, 25.32... oxide film, 26... P type base layer, 27... polycrystalline silicon layer, 28... H
1i emitter layer, 30...external base layer, 33...
Sidewall oxide film, 34...N-type silicon layer.

Claims (6)

[Claims] (1) When manufacturing a semiconductor device including at least one bipolar transistor, the silicon substrate is selectively etched until at least the buried collector layer is reached, and an insulating film is formed on the sidewall of the etched portion. . A method of manufacturing a semiconductor device, comprising the step of embedding silicon in the etched portion. (2) The method of manufacturing a semiconductor device according to claim 1, wherein the insulating film is made of silicon oxide or nitride. (3) The method for manufacturing a semiconductor device according to claim 1, wherein the step of embedding silicon is a selective epitaxial method. (4) The method of manufacturing a semiconductor device according to claim 1, wherein in the step of embedding silicon, silicon or polycrystalline silicon is formed on the entire surface and then selectively embedded by etching back. (5) The method of manufacturing a semiconductor device according to claim 1, wherein the selectively buried silicon already contains impurities. (6) The method of manufacturing a semiconductor device according to claim 1, wherein after the silicon embedding step, impurities are selectively given to the selectively embedded silicon.