JP2836393B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a bipolar transistor for ultra-high-speed operation and a method of manufacturing the same.

[0002]

2. Description of the Related Art A conventional semiconductor device will be described with reference to the drawings.

FIGS. 6A and 6B are cross-sectional views showing a conventional method of manufacturing a semiconductor device in the order of steps for explaining the method.

First, as shown in FIG. 6A, arsenic is selectively introduced into one main surface of a P-type silicon substrate 101 to form an N-type buried layer 102, and the N-type buried layer 102 is included. After growing an N-type epitaxial layer 103 having a thickness of 0.7 μm on the surface, an element isolation region 122 and a P-type silicon region 123 are formed.
To form Next, phosphorus is selectively diffused from the upper surface of the N-type epitaxial layer 103 to form a collector extraction region 104.
To form Next, a silicon oxide film 105 having a thickness of 50 to 200 nm is deposited on the entire surface, and the silicon oxide film 105 is selectively etched and removed over the collector lead-out region 104 and the transistor formation region to form an opening.
Next, a polycrystalline silicon film having a thickness of 50 to 200 nm is deposited on the entire surface and patterned, and a collector lead region 104 is formed.
Phosphorus is selectively introduced into the upper polycrystalline silicon film to form an N-type polycrystalline silicon film 106, and similarly, boron is selectively introduced into the polycrystalline silicon film above the transistor formation region to form a P-type polycrystalline silicon film. A film 107 is formed. Next, thickness 1
A 00 nm silicon nitride film 100 is deposited on the entire surface. Next, using the photoresist film as a mask, the silicon nitride film 10
The 0 and P-type polycrystalline silicon films 107 are sequentially anisotropically etched to form an emitter opening 108.

[0005] Next, as shown in FIG. 6B (however, a partially enlarged view of FIG. 6A), the surface of the N-type epitaxial layer 103 exposed at the emitter opening 108 is thermally oxidized to a thickness of 10 nm. A silicon oxide film 111 having a thickness of about 40 nm is formed. At the same time, boron of the P-type polycrystalline silicon film 107 is diffused into the surface of the N-type epitaxial layer 103 in a portion in contact with the P-type polycrystalline silicon film 107 to form an external base region 112. Next, using the silicon nitride film 100 as a mask, boron ions are implanted at an acceleration energy of 10 keV and a dose of 3 × 10 ¹³ cm ⁻² to form a base region 113. Next, thickness 10
A silicon nitride film 109 of 0 nm is deposited on the entire surface and etched back by anisotropic etching to form an emitter opening 108.
The silicon nitride film 109 is left only on the side wall of.

Next, a polycrystalline silicon film 117 containing arsenic is used.
Is deposited on the entire surface and patterned to form an emitter electrode. Next, arsenic in the polycrystalline silicon film 117 is diffused by rapid thermal annealing (RTA) to the surface of the base region 113 in contact with the polycrystalline silicon film 117 to form an N-type emitter region 1.
18 are formed. Next, a silicon oxide film 119 is deposited on the entire surface, and then selectively etched to form a contact hole. Next, an aluminum wiring 121 electrically connected to the polycrystalline silicon film 117 in the contact hole is selectively formed to form a semiconductor device.

[0007]

Reducing the emitter width of a bipolar transistor is effective in reducing the emitter-base parasitic capacitance, the base-collector parasitic capacitance, and the base resistance, which are effective in increasing the speed. .
Therefore, an emitter region having a width smaller than that of the minimum processing by lithography is formed.

In the conventional semiconductor device, the emitter region has a silicon nitride film 109 formed on the side wall of the emitter opening 108 to reduce the effective width of the emitter region 118. The effective of the emitter width W _E, the width W _EO of emitter opening 108, the width of the silicon nitride sidewall films 109 and W _S, the _{W E = W EO -2 × W} S.

In this case, when it is desired to make the emitter width smaller than the lithography minimum processing size, processing accuracy becomes particularly important. For example, when a transistor having an emitter width W _E of 0.1 μm is formed by a stepper apparatus having a minimum processing accuracy of 0.5 μm in lithography, W _EO = 0.
5 μm, W _S = 0.2 μm. At this time, since the processing accuracy is usually about ± 10% of W _EO and W _S , the dimensional error of W _E is W _EO × 0.1 + W _S × 0.1 × 2 = 0.09 μm.
m, and W _E is 0.01 to 0.19, that is, the error 9
It changes greatly to 0%. This has the disadvantage that the transistor characteristics change significantly.

[0010] Polycrystalline silicon film 117 on the emitter region
If the film thickness of the polysilicon film is reduced to a certain degree or more, the amplification factor of the transistor decreases. Therefore, the film thickness of the polycrystalline silicon film 117 must be at least 100 nm. However, when the emitter width is reduced to near the film thickness of the polysilicon film 117, the emitter opening is buried by the polysilicon film 117, the effective film thickness of the polysilicon film 117 increases, and the aluminum wiring 121 However, there has been a problem that the extraction resistance of the emitter until the resistance reaches a large value.

[0011]

According to the present invention, there is provided a semiconductor device comprising:
A base extraction electrode and a first insulating film, which are sequentially stacked on the one conductivity type semiconductor layer serving as a collector region;
A first opening formed by selectively etching the insulating film and the base extraction electrode sequentially, an external base region of a reverse conductivity type provided to be connected to the lower surface of the base extraction electrode, A reverse conductivity type base region provided on the surface of the conductivity type semiconductor layer and connected to the external base region; a second insulating film provided on a side wall of the opening; and a center portion of the base region of the opening. A third insulating film, an annular second opening provided along the inner periphery of the second insulating film, and an emitter of one conductivity type provided in the base region of the second opening. Region.

A method of manufacturing a semiconductor device according to the present invention includes the steps of sequentially depositing a first polycrystalline silicon film containing an impurity of the opposite conductivity type and a first insulating film on a semiconductor layer of one conductivity type serving as a collector region. Selectively etching the first insulating film and the first polycrystalline silicon film sequentially to form a first opening, and heat treating the one-conductivity type semiconductor from the first polycrystalline silicon film. Forming a reverse conductivity type external base region by diffusing impurities into the layer, and applying a reverse conductivity type impurity to the surface of the one conductivity type semiconductor layer in the first opening using the first insulating film as a mask. Forming a base region connected to the external base region by ion implantation, depositing a second insulating film on a surface including the first opening and etching back to form a second insulating film on a side wall of the first opening; Only the step of leaving the second insulating film, and Depositing and etching back a second polycrystalline silicon film to leave a second polycrystalline silicon film only on the side wall of the second insulating film in the first opening; Forming a third insulating film only on the bottom surface, and forming an annular second opening along the inner periphery of the second insulating film by removing the second polycrystalline silicon film by etching; Depositing and patterning a third polycrystalline silicon film containing an impurity of one conductivity type on a surface including the second opening, and performing a heat treatment to reduce the thickness of the second opening from the third polycrystalline silicon film. Forming an emitter region of one conductivity type by diffusing impurities of one conductivity type into the base region.

[0013]

Next, the present invention will be described with reference to the drawings.

FIGS. 1 (a) and 1 (b) and FIGS.
(B) and FIG. 3 are sectional views shown in the order of steps for explaining the manufacturing method of the first embodiment of the present invention.

First, as shown in FIG. 1A, up to the emitter opening 108 is formed by the same process as in the conventional example. Next, the surface of the N-type epitaxial layer 103 exposed at the emitter opening 108 is thermally oxidized to a thickness of 10 to 40 n.
An m-th silicon oxide film 111 is formed. At the same time, boron in the P-type polycrystalline silicon film 107 is diffused into the N-type epitaxial layer 103 to form an external base region 112. Next, using the silicon nitride film 100 as a mask, boron ions are accelerated at an energy of 10 keV and a dose of 3 × 10
Ion implantation is performed at ¹³ cm ⁻² to form a base region 113 connected to the external base region 112. The base region 113
May be formed by forming a BSG film in place of the silicon oxide film 111 and thermally diffusing boron therefrom. Next, a silicon nitride film 109 having a thickness of 100 nm is deposited on the entire surface and then etched back by anisotropic etching to leave the silicon nitride film 109 only on the side wall of the emitter opening 108.

Next, as shown in FIG.
A polycrystalline silicon film of about 200 nm is deposited on the entire surface and then etched back by anisotropic etching to form an emitter opening 1.
The polycrystalline silicon film 114 is left only on the side wall of the 08 silicon nitride film 109. Next, a thickness of, for example, 50 nm to 2 nm is formed on the exposed portion of the silicon oxide film 111 by a selective oxide film growth method.
A 00 nm silicon oxide film 115 is deposited.

Next, as shown in FIG. 2A, the polycrystalline silicon film 114 is removed by etching, and then the silicon oxide film 111 is removed by etching using the silicon nitride films 100 and 109 and the silicon oxide film 115 as a mask. I do.

Next, as shown in FIG. 2B, a thickness of 50 to 100 containing arsenic, an N-type impurity, at a concentration of 2 × 10 ²⁰ cm ^-3.
A polycrystalline silicon film 117 of nm is deposited on the entire surface and patterned to form an emitter electrode. Next, the polycrystalline silicon film 11 is formed by a rapid thermal annealing (RTA) method.
Base region 1 at the portion where N-type impurities in FIG.
13 to form an N-type emitter region 118.

The polycrystalline silicon film 117 may be formed by depositing a non-doped polycrystalline silicon film and then ion-implanting an N-type impurity. The polycrystalline silicon film 117 is grown only on the silicon exposed portion by a selective growth method. May be performed. Further, instead of the N-type polycrystalline silicon film 117, a semiconductor film having a wide band gap, such as a silicon carbide film or a microcrystalline silicon film, or a conductive film may be used. Further, the N-type impurity is introduced into the emitter region 118 by a direct ion implantation method without using the polycrystalline silicon film 117.
It may be performed by a diffusion method.

Next, as shown in FIG. 3, a silicon oxide film 119 is deposited on the entire surface and patterned to form a contact hole. Next, an aluminum film is deposited and patterned on the surface including the contact hole to form a wiring 121, thereby forming a semiconductor device.

The semiconductor device of the first embodiment described above has the following features. That is, the width of the emitter region 116 is determined by the thickness of the polycrystalline silicon film 114 provided on the side wall of the emitter opening 108. The dimensional error of the polycrystalline silicon film 114 is the sum of the thickness error of the deposited polycrystalline silicon film 114 and the lateral etching amount during anisotropic etching, and this dimensional error can be reduced to 10% as in the conventional example. Therefore, even when the emitter width is 0.1 μm, the error is ± 1.
Transistors can be manufactured with a much higher accuracy of 0% as compared with the prior art. As a result, the characteristic variation of a transistor having a particularly small emitter width is greatly reduced.

FIG. 4 is a sectional view showing a second embodiment of the present invention.

As shown in FIG. 4, the first region except that an embedded collector region 116 having an N-type impurity concentration higher than that of the epitaxial region 103 is provided on the lower surface of the base region 113 immediately below the emitter region 117. 1B, a polycrystalline silicon film 114 is provided on the side wall of the opening 108, and then a silicon oxide film 115 is formed to a thickness of 150 to 200 nm, as shown in FIG. After selective growth and removal of the polycrystalline silicon film 114, phosphorus is ion-implanted into the N-type epitaxial layer 103 through the exposed portion of the silicon oxide film 111 at an acceleration energy of 200 keV and a dose of 3 × 10 ¹² cm ^−2. A buried collector region 116 is formed.

In the present embodiment, N
Since the buried collector region 116 having an N-type high impurity concentration can be formed in the epitaxial layer 103, the Kirk effect is suppressed and the maximum cutoff frequency f _T is improved without increasing the concentration of the other epitaxial layer 103.

FIG. 5 is a sectional view for explaining a third embodiment of the present invention.

As shown in FIG. 5, after forming up to the base region 113 by the same process as in the first embodiment,
A silicon nitride film 109 of 00 nm is deposited on the entire surface and etched back by anisotropic etching to form an emitter opening 1
The silicon nitride film 109 is left only on the side wall of the substrate 08. next,
Thickness 50 containing arsenic, an N-type impurity, at a concentration of 2 × 10 ²⁰ cm ^-3
A polycrystalline silicon film 117 of about 100 nm is deposited on the entire surface and etched back by anisotropic etching to leave the polycrystalline silicon film 117 only on the side wall of the emitter opening 108. Next, thermal oxidation or HTO (High Tempe)
Silicon Oxide Film 1 by a Rate Oxide Method
26 is formed to a thickness of 10 nm, and then a silica glass film 125 is formed on the entire surface by coating or flattening by CVD and heat treatment. At this time, the inside of the emitter opening 108 is thick,
In other portions, a thin silica glass film 125 is formed. Next, the silica glass film 125 is removed by etch-back, leaving only the inside of the emitter opening 108. next,
An N-type impurity in the polycrystalline silicon film 117 is diffused into the base region 113 in a portion in contact with the N-type impurity by a rapid thermal annealing (RTA) method to form an N-type emitter region 118. The emitter region 118 is a polycrystalline silicon film 11
7 only below. Next, the silicon oxide film 119
Is deposited on the entire surface and patterned to form a contact hole. Next, an aluminum film is deposited and patterned on the surface including the contact hole, and the wiring 121 is formed to configure a semiconductor device.

The third embodiment has the advantage that the emitter resistance can be reduced because the length of the polycrystalline silicon film 117 between the emitter region 118 and the wiring 121 is short.

Further, by selectively growing the polycrystalline silicon film on the emitter region and embedding it with a tungsten film, it is possible to prevent an increase in emitter resistance when the emitter width is reduced.

[0029]

As described above, according to the present invention, 20 to 200 times smaller than the minimum processing accuracy of lithography.
This has the effect that a bipolar transistor having an emitter width of about nm can be realized with high accuracy. That is,
There is an advantage that the relative error in the emitter width does not increase even if the emitter is miniaturized using the same processing technology as before.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a manufacturing method according to a first embodiment of the present invention in the order of steps for explaining the manufacturing method.

FIG. 2 is a cross-sectional view illustrating a manufacturing method according to the first embodiment of the present invention in the order of steps for explaining the manufacturing method.

FIG. 3 is a cross-sectional view illustrating a manufacturing method according to the first embodiment of the present invention in the order of steps for explaining the manufacturing method.

FIG. 4 is a sectional view for explaining a second embodiment of the present invention.

FIG. 5 is a sectional view for explaining a third embodiment of the present invention.

FIG. 6 is a cross-sectional view illustrating a conventional method of manufacturing a semiconductor device in the order of steps for explaining the method.

[Explanation of symbols]

100, 109 Silicon nitride film 101 P-type silicon substrate 102 N-type buried layer 103 N-type epitaxial layer 104 Collector lead-out region 105, 111, 115, 119, 126 Silicon oxide film 106 N-type polycrystalline silicon film 107 P-type polycrystalline Silicon film 108 Emitter opening 112 External base region 113 Base region 114,117 Polycrystalline silicon film 116 Embedded collector region 118 Emitter region 120 Contact hole 121 Wiring 122 Element isolation region 123 P-type silicon region 125 Silica glass film

Claims (2)

(57) [Claims] 1. A base extraction electrode and a first insulating film, which are sequentially laminated on one conductivity type semiconductor layer serving as a collector region, and the first insulating film and the base extraction electrode are selectively and sequentially etched. A first opening provided as described above, an external base region of a reverse conductivity type provided in connection with the lower surface of the base extraction electrode, and an external base region provided on the surface of the one conductivity type semiconductor layer of the opening. A second insulating film provided on a side wall of the opening, a third insulating film provided on a central portion of the base region of the opening, and a second insulating film provided on a side wall of the opening. A semiconductor device comprising: a second annular opening provided along an inner periphery of a film; and an emitter region of one conductivity type provided in the base region of the second opening. 2. a step of sequentially depositing a first polycrystalline silicon film and a first insulating film containing an impurity of the opposite conductivity type on a semiconductor layer of one conductivity type serving as a collector region; Forming a first opening by selectively etching the first polycrystalline silicon film sequentially and diffusing impurities from the first polycrystalline silicon film into the one-conductivity-type semiconductor layer by heat treatment; Forming a conductive type external base region; and ion-implanting a reverse conductive type impurity into a surface of the one conductive type semiconductor layer of the first opening using the first insulating film as a mask. Forming a base region connected to the first opening, depositing a second insulating film on the surface including the first opening, and etching back to leave the second insulating film only on the side wall of the first opening Process and similarly deposit a second polycrystalline silicon film Etching back to leave the second polycrystalline silicon film only on the side wall of the second insulating film in the first opening, and forming a third insulating film only on the bottom surface of the first opening Forming the second polycrystalline silicon film by etching to form an annular second opening along the inner periphery of the second insulating film; and forming the second opening. A third polycrystalline silicon film containing one conductivity type impurity is deposited and patterned on the surface, and the third
Forming a one conductivity type emitter region by diffusing one conductivity type impurity from the polycrystalline silicon film into the base region of the second opening.