JPH04245438A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent plasma damage and sputtering damage from being caused at a base region and an emitter region and to enhance the characteristic of a transistor by a method wherein a laminated-film pattern is formed on an element-formation region. CONSTITUTION:A laminated film where a silicon oxide film 13 and a silicon nitride film 14 have been laminated and patterned is formed on an element- formation region; a polycrystalline silicon film 19 for base extraction electrode use and a silicon oxide film 20 are laminated sequentially on the surface including the laminated film. Then, the silicon oxide film 20, the polycrystalline silicon film 19 and the silicon nitride film 14 are selectively etched sequentially by a reactive ion etching operation; the silicon oxide film 13 is wet-etched; an opening part is formed. Since an N<-> type epitaxial layer 12 does not come into contact with the polycrystalline silicon film at this time, a sufficient selective ratio can be obtained, and the silicon oxide film 13 can be wet-etched and removed.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having a bipolar transistor.

0002

[Prior Art] Bipolar transistors, which are suitable for high-speed logic operation, have a shallow vertical junction depth and an element isolation layer such as a buried oxide film or a trench structure to create a connection between the substrate and the collector. Performance has been improved using various methods such as reducing parasitic capacitance, and reducing base-collector and base-emitter parasitic capacitance using fine lithography technology and self-alignment technology, as well as reducing base resistance. We are making improvements.

One method for miniaturizing and increasing the speed of bipolar transistors is a self-alignment technique using polycrystalline silicon.

FIGS. 6A to 6D are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a conventional method of manufacturing a semiconductor device.

First, as shown in FIG. 6A, an n+ type buried layer 11 is formed on a p type silicon substrate 10, and then an n- type epitaxial layer 12 is grown thereon. Next, a field oxide film 17 for element isolation is formed to define an element formation region. Next, the n-type epitaxial layer 1
A p+ type polycrystalline silicon film 31 for base extraction is formed on 2.

Next, as shown in FIG. 6(b), a silicon oxide film 32 is deposited on the p+ type polycrystalline silicon film 31, and the silicon oxide film 32 and the p+ type polycrystalline silicon film 31
Apertures are provided by selectively and sequentially etching the holes.

Next, as shown in FIG. 6C, a silicon oxide film 33 is formed on the side surfaces of the p + -type polycrystalline silicon film 31 and the surface of the n - -type epitaxial layer 12 within the opening by thermal oxidation. At this time, p-type impurities are simultaneously transferred from the polycrystalline silicon film 31 to the n-type epitaxial layer 12.
to form a graft base region 22. Next, using the silicon oxide film 32 and the p+ type polycrystalline silicon film 31 as masks, boron ions are implanted to form the intrinsic base region 23.

Next, as shown in FIG. 6(d), a silicon nitride film 26 is deposited on the surface including the opening and etched back, leaving the silicon nitride film 26 only on the sides of the opening. Next, the silicon oxide film 33 is etched using the silicon nitride film 26 as a mask to open an emitter diffusion window, and a polycrystalline silicon film 28 containing n-type impurities is selectively deposited on the surface including the emitter diffusion window. The emitter region 27 is formed by diffusing impurities from the polycrystalline silicon film 28 into the surface of the intrinsic base region 23 .

[0009]

[Problems to be Solved by the Invention] In the conventional semiconductor device manufacturing method described above, if a reactive ion etching method with good processing accuracy is used to etch the p+ type polycrystalline silicon film 31 for the base lead-out electrode, it is possible to prevent future activation. N- type epitaxial layer 1 forming base region and emitter region
There is a problem in that plasma damage and sputter damage occur on the surface of 2.

[0010] Furthermore, when wet etching is used, although plasma damage and sputter damage can be prevented, there is a problem in that dimensional processing accuracy is reduced.

[0011]

[Means for Solving the Problems] A method for manufacturing a semiconductor device of the present invention includes forming a buried layer of an opposite conductivity type on a semiconductor substrate of one conductivity type and an epitaxial layer of an opposite conductivity type on a surface including the buried layer. and a first step on the surface of the epitaxial layer.
a step of sequentially depositing and patterning an insulating film, a first oxidation-resistant insulating film, a first polycrystalline silicon film, and a second oxidation-resistant insulating film to form a laminated film, and using the laminated film as a mask. a step of oxidizing the epitaxial layer to form a field oxide film for element isolation reaching the buried layer and simultaneously oxidizing the side surface of the first polycrystalline silicon film to form a silicon oxide film; removing the oxidation-resistant insulating film and the silicon oxide film and sequentially etching and removing the first oxidation-resistant insulating film and the first insulating film using the first polycrystalline silicon film as a mask; a step of sequentially depositing a second polycrystalline silicon film containing impurities of one conductivity type and a second insulating film on the surface including the first oxidation-resistant insulating film after removing the crystalline silicon film; a step of selectively sequentially etching the insulating film, the second polycrystalline silicon film, the first oxidation-resistant insulating film, and the first insulating film to form an opening, and forming an epitaxial layer in the opening. Oxidizing the surface and side surfaces of the second polycrystalline silicon film to form a silicon oxide film, and at the same time diffusing impurities from the second polycrystalline silicon film to the surface of the epitaxial layer to provide a graft base region of one conductivity type. and a step of forming an intrinsic base region connected to the graft base region in the epitaxial layer of the opening using the second insulating film and the second polycrystalline silicon film as a mask.

0012

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1(a) to (d) and FIGS. 2(a) to (d)
) and FIGS. 3(a) and 3(b) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining the first embodiment of the present invention.

First, as shown in FIG. 1(a), an n+ type buried layer 11 is formed on one main surface of a p type silicon substrate 10,
An n - type epitaxial layer 12 is grown to a thickness of 1 to 3 μm on the surface including the n + type buried layer 11 . Next, n-
The surface of the mold epitaxial layer 12 is thermally oxidized to form a silicon oxide film 13 to a thickness of 50 to 100 nm, and a silicon nitride film 14 is deposited to a thickness of 100 to 200 nm as an oxidation-resistant film on the silicon oxide film 13. , silicon nitride film 1
A polycrystalline silicon film 15 is deposited to a thickness of 50 to 100 nm on the polycrystalline silicon film 15, and a silicon nitride film 16 is further deposited to a thickness of 100 to 200 nm as an oxidation-resistant film on the polycrystalline silicon film 15.

Next, as shown in FIG. 1B, the silicon nitride film 16, polycrystalline silicon film 15, silicon nitride film 14, and silicon oxide film 13 are selectively and sequentially etched using a reactive ion etching method. A laminated film pattern is formed on the element formation region. Here, the silicon nitride film 16
, 14 and the silicon oxide film 13, a CF4-based reactive gas is used, and for etching the polycrystalline silicon film 15, an SF6-based gas is used.

Next, as shown in FIG. 1(c), the n- type epitaxial layer 12 is thermally oxidized using the four-layer laminated film pattern as a mask to form a field oxide film 17 and define an element formation region. . At this time, the polycrystalline silicon film 13
Also, a 0.5 to 1.0 μm wide area from the side is oxidized,
A silicon oxide film 18 is formed.

Next, as shown in FIG. 1D, the silicon nitride film 16 and the silicon oxide film 18 are sequentially etched and removed using a wet etching method, and then the silicon nitride film 18 is removed using the polycrystalline silicon film 15 as a mask. 14 is etched and removed. Next, polycrystalline silicon film 15 is removed, and silicon oxide film 13 is etched and removed using silicon nitride film 14 as a mask. Here, a phosphoric acid (H3 PO4) based solution is used to remove the silicon nitride films 16 and 14, and a hydrofluoric acid (H3 PO4) solution is used to remove the silicon oxide films 18 and 13.
F) type solution is used, and a fluoro-nitric acid (HNO3 +HF) type solution is used to remove the polycrystalline silicon film 15, respectively.

Next, as shown in FIG. 2A, a polycrystalline silicon film 19 is deposited on the surface including the silicon nitride film 14 at a thickness of 0.2
Deposit to a thickness of ~0.3 μm and dope the entire surface with boron ions.

Next, as shown in FIG. 2B, a silicon oxide film 20 is deposited to a thickness of 300 to 500 nm on the polycrystalline silicon film 19 by chemical vapor deposition. A photoresist film 21 is applied on top of the photoresist film 20 and patterned.

Next, as shown in FIG. 2C, using the photoresist film 21 as a mask, the silicon oxide film 20, polycrystalline silicon film 19, silicon nitride film 14, and silicon oxide film 13 are sequentially etched to form holes. A section will be established. here,
For etching the silicon oxide film 20 and the silicon nitride film 14, a CF4-H2-based gas is applied to the polycrystalline silicon film 1.
For etching 9, CF4-O2, CF3Cl,
A reactive ion etching method using a C2 F6 gas or the like is used, and a wet etching method is used to etch the silicon oxide film 13. Here, since the n- type epitaxial layer 12 and the polycrystalline silicon film 19 are not in contact with each other, a sufficient selectivity can be obtained, so the silicon oxide film 13 can be removed by wet etching, and the n- type epitaxial layer No damage to the surface of the 12.

Next, as shown in FIG. 2(d), from 900 to
Heat treated in N2 atmosphere at 950°C for 30-60 minutes,
From polycrystalline silicon film 19 to n- type epitaxial layer 1
2, a p-type impurity is diffused into the graft base region 22.
form. Next, the surfaces of the n- type epitaxial layer 12 and the polycrystalline silicon film 19 in the opening are thermally oxidized to form silicon oxide films 24 and 25. Next, using the silicon oxide film 20 and the polycrystalline silicon film 19 as masks, boron ions are implanted into the n- type epitaxial layer 12 in the opening to form an intrinsic base region 23.

Next, as shown in FIG. 3(a), a silicon nitride film 26 is deposited to a thickness of 200 to 300 nm on the surface including the openings by low pressure chemical vapor deposition.
Anisotropic etching is performed using a reactive ion etching method using a gas such as -O2 or CF4 -H2,
The silicon nitride film 26 is left only on the side surfaces of the opening.

Next, as shown in FIG. 3B, using the silicon nitride film 26 as a mask, the silicon oxide film 25 is removed to expose the silicon substrate. Next, a polycrystalline silicon film 28 is deposited to a thickness of 300 to 500 nm over the entire surface, and after doping with n-type impurities such as arsenic by ion implantation, the polycrystalline silicon film 28 is selectively etched to form an intrinsic base region. An emitter electrode is formed on 23. Next, 900-9
A polycrystalline silicon film 28 is formed on the surface of the intrinsic base region 23 by heat treatment for 10 to 30 minutes in a N2 atmosphere at 50°C.
An emitter region 27 is formed by doping n-type impurities.

FIGS. 4(a) to (d) and FIGS. 5(a) and (b)
) are cross-sectional views of a semiconductor chip shown in order of steps for explaining a second embodiment of the present invention.

As shown in FIG. 4(a), FIG.
A laminated film pattern of the silicon oxide film 13 and the silicon nitride film 14 provided on the element formation region is formed by the same process as in the first embodiment described in d).

Next, as shown in FIG. 4(b), using the silicon oxide film 13 and the silicon nitride film 14 as masks,
- Boron ions are implanted into the surface of the type epitaxial layer 12 to form an impurity implantation layer, and a polycrystalline silicon film 19 is deposited to a thickness of 300 to 500 nm on the entire surface. Next, heat treatment is performed for 30 to 60 minutes in a N2 atmosphere at 900 to 950 DEG C. to diffuse p-type impurities into the polycrystalline silicon film 19 from the impurity injection layer. At this time, p-type impurities are simultaneously diffused into the polycrystalline silicon film 19 from the surface of the field oxide film 17. When heat treatment is performed at 900°C for 30 minutes, 0.6% of boron is present in the polycrystalline silicon film.
Diffuses about 5 μm. Therefore, the graft base region 22 is formed at the same time that boron is diffused to the extent that it covers the edge portion of the silicon nitride film 14 by heat treatment.

Next, as shown in FIG. 4(c), a KO film having selectivity to the polycrystalline silicon film containing p-type impurities was prepared.
The polycrystalline silicon film 19 is wet-etched using an H-based solution to selectively remove only the polycrystalline silicon film 19 on the silicon nitride film 14, leaving the polycrystalline silicon film in which p-type impurities are diffused.

Next, as shown in FIG. 4(d), the surface of the p-type polycrystalline silicon film 19 is thermally oxidized to form a silicon oxide film 29.
form.

Next, as shown in FIG. 5A, the silicon nitride film 14 and silicon oxide film 13 are wet-etched using the silicon oxide film 29 as a mask, and then the surface of the n- epitaxial layer 12 is oxidized by thermal oxidation. A silicon film 30 is formed to a thickness of 50 nm, and a silicon oxide film 29 is formed.
Using the mask as a mask, p-type impurity ions are implanted into the surface of the n- type epitaxial layer 12 to form an intrinsic base region 22.

Next, as shown in FIG. 5B, a silicon nitride film 26 is provided on the side wall of the opening by the same process as in the first embodiment, and a polycrystalline silicon film 26 is formed as an emitter electrode.
8 and an emitter region 27 are formed.

[0031]

[Effects of the Invention] As explained above, the present invention prevents plasma damage and sputter damage from occurring in the base region and emitter region by providing a laminated film pattern on the element formation region, and improves the characteristics of the transistor. It has the effect of causing

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a semiconductor chip shown in order of steps for explaining a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of a semiconductor chip shown in order of steps for explaining a first embodiment of the present invention.

FIG. 3 is a cross-sectional view of a semiconductor chip shown in order of steps for explaining the first embodiment of the present invention.

FIG. 4 is a cross-sectional view of a semiconductor chip shown in order of steps for explaining a second embodiment of the present invention.

FIG. 5 is a cross-sectional view of a semiconductor chip shown in order of steps for explaining a second embodiment of the present invention.

FIG. 6 is a cross-sectional view of a semiconductor chip shown in order of steps for explaining a conventional method of manufacturing a semiconductor device.

[Explanation of symbols]

10 p-type silicon substrate 11 n+ type buried layer 12 n- type epitaxial layer 13, 18, 2
0, 24, 25, 29, 30, 32, 33 Silicon oxide film 14, 16, 26 Silicon nitride film 15, 19,
28 Polycrystalline silicon film 17 Field oxide film 21 Photoresist film 22 Graft base region 23 Intrinsic base region 27 Emitter region

Claims (1)

[Claims] 1. A step of forming a buried layer of an opposite conductivity type on a semiconductor substrate of one conductivity type and an epitaxial layer of an opposite conductivity type on a surface including the buried layer, and a step of forming a first insulating layer on a surface of the epitaxial layer. a first oxidation-resistant insulating film, a first polycrystalline silicon film, and a second oxidation-resistant insulating film to form a laminated film by sequentially depositing and patterning the epitaxial layer using the laminated film as a mask; oxidizing the layer to form a field oxide film for element isolation reaching the buried layer and simultaneously oxidizing the side surface of the first polycrystalline silicon film to form a silicon oxide film; removing the oxidation-resistant insulating film and the silicon oxide film and sequentially etching and removing the first oxidation-resistant insulating film and the first insulating film using the first polycrystalline silicon film as a mask; a step of sequentially depositing a second polycrystalline silicon film containing impurities of one conductivity type and a second insulating film on the surface including the first oxidation-resistant insulating film after removing the film; a step of selectively sequentially etching the film, the second polycrystalline silicon film, the first oxidation-resistant insulating film, and the first insulating film to form an opening, and etching the surface of the epitaxial layer in the opening and oxidizing the side surface of the second polycrystalline silicon film to form a silicon oxide film, and simultaneously diffusing impurities from the second polycrystalline silicon film to the surface of the epitaxial layer to provide a graft base region of one conductivity type; , forming an intrinsic base region connected to the graft base region in the epitaxial layer of the opening using the second insulating film and the second polycrystalline silicon film as a mask. Production method.