JPH0240921A - Manufacture of bipolar transistor - Google Patents

Abstract

PURPOSE:To obtain a dimension finner than a dimension, which is restricted by a lithography technique, and to reduce a junction capacitance by a method wherein an eroded part is formed utilizing a first sidewall provided on the inner side of an opening in an insulating film and with graft base regions provided by diffusing an impurity through this eroded part, a base region and an emitter region are formed utilizing a second sidewall. CONSTITUTION:An n<+> buried layer 2, is formed in a P-type Si substrate 1, an n-type layer 3 is epitaxially grown on the whole surface including this layer 2 and the layer 3 is partitioned by an SiO2 film 4 to use here as an element formation region. Then, an insulating film 5, a poly Si film 6, an n<+> collector lead-out layer 7 and insulating layers 8 and 9 are laminated on the whole surface of this element formation region, an opening is pored to expose the element formation region and here is covered with an insulating film 11. After that, an etching is performed to remove both end parts of the film 11 and at the same time, an eroded part 8a is made to generate in the sidewall of the opening and an impurity is diffused through this part 8a to form graft base regions 12 under the end parts of the lower surface of the film 11. Then, a treatment identical with the above treatment is performed, a P-type emitter region 19 is formed between the regions 12 and an n<+> active base region 16, which is positioned on the surface layer part of this region 19, is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a bipolar transistor, and particularly to a method for manufacturing a bipolar transistor with improved high frequency characteristics.

[Conventional technology]

Conventionally, in order to realize a high-speed transistor by reducing base resistance and its junction capacitance, a structure in which a graft base is formed in a self-aligned manner using a polycrystalline silicon film of a base electrode as a diffusion source has been known. For example, FIG. 2 is a cross-sectional view of a conventional bipolar transistor of this type.

In order to manufacture this structure, first, an n-type buried layer 32 is formed on a semiconductor substrate 31 made of p-type silicon, an n-type epitaxial layer 33 is grown on this, and then a Si
The element forming region is insulated and isolated by a thick insulating region 34 consisting of , and a thin insulating film 35 is formed in the element forming region.

Then, a polycrystalline silicon film 36 containing p-type impurities
After sequentially forming the insulating film 37 and the insulating film 37, a window is opened in the insulating film 37, and using the insulating film 37 as a mask, the polycrystalline silicon film 36 and the insulating film 35 are etched to open a wider window.

Furthermore, a polycrystalline silicon film 38 containing p-type impurities is formed under the eaves of the insulating film 37.
A graft base region 39 is formed on the surface of the epitaxial layer 33 in a self-aligned manner using 8 as a diffusion source.

Subsequently, an insulating film 40 for separating the emitter and base electrodes is formed in the opening, and a p-type impurity is introduced into the surface of the opening of the epitaxial layer 330 by ion implantation or the like to form a base region 41. Also, polycrystalline silicon 42 is placed over the opening.
is grown, and an n-type impurity is introduced by ion implantation to form an emitter region 43.

[Problem to be solved by the invention]

The conventional method for manufacturing the bipolar transistor described above is as follows:
Since the graft base region 39 is formed in a self-aligned manner, the base resistance and collector junction capacitance can be reduced, but the polycrystalline silicon film 38 for forming the graft base region 39 is Since the area of the entire base region including the graft base region 39 is larger than the minimum dimension of the opening possible with lithography technology. For this reason, there is a limit to further reducing the resistance of the base region to reduce junction capacitance and improve high frequency characteristics such as cutoff frequency.

Furthermore, when removing the polycrystalline silicon 42 grown on the opening to form the emitter region 43, the etching must be controlled taking into account the selectivity with respect to the underlying epitaxial layer 33. There is also the problem of difficulty.

An object of the present invention is to provide a method for manufacturing a bipolar transistor that can easily obtain a bipolar transistor with reduced junction capacitance and excellent high frequency characteristics.

[Means to solve the problem]

In the method for manufacturing a bipolar transistor of the present invention, an eroded portion is formed using a first side wall provided inside an opening in an insulating film, a graft base region is formed through this eroded portion, and a graft base region is formed inside the opening. A base region and an emitter region are sequentially formed using the second sidewall.

[Effect]

In the above-mentioned manufacturing method, a graft base region is formed within the opening by utilizing the eroded portion within the opening, and a base region and an emitter region are further formed inside this region, and these regions are made to be free from the constraints of lithography technology. It is also formed into minute dimensions.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) to 1(i) are vertical sectional views showing an embodiment of the present invention in the order of steps.

First, as shown in FIG. 1(a), a p
An n-type buried layer 2 is formed on the surface of a type semiconductor substrate 1, and an n-type epitaxial layer 3 is formed thereon to a thickness of 0.5 to 1.0 μm. Further, an insulating region 4 made of SiO□ and a pn junction (not shown) define an element formation region insulated and isolated. Then, a first insulating film 5 made of SiO□ and a first polycrystalline silicon film 6 containing p-type impurities are sequentially deposited on the element formation region, and are left in predetermined regions including over the element formation region. The first polycrystalline silicon film 6 is selectively removed as shown in FIG. Note that a part of the epitaxial layer 3 is doped with n-type impurities at a high concentration to form an n-type collector extraction diffusion layer 7.
Form it.

Subsequently, a silicon nitride film, which is an oxidation-resistant film, is deposited as the second insulating film 8, and a silicon oxide film is deposited as the third insulating film 9, in order. Second
Insulating film 8. First polycrystalline silicon film 6. Then, the first insulating film 5 is sequentially and selectively anisotropically etched to form an opening.

Next, as shown in FIG. 1(b), a silicon nitride film, which is the same as the second insulating film 8, is deposited to a thickness of 1,500 to 3,000 layers, and the vertical side walls are etched by reactive ion etching (hereinafter referred to as RIE). The first side wall 10 is formed by etching excluding the portion. Such RIE techniques are known and are disclosed, for example, in US Pat. No. 4,234,362. After that, the surface of the exposed n-type epitaxial layer 3 is
A fourth insulating film 11 made of a silicon oxide film is formed by oxidizing the silicon oxide film for 000 to 2000 times. At this time, the side surface of the opening in the emitter formation region is protected by the first sidewall 10, which serves to prevent the first polycrystalline silicon film 6 inside from being oxidized.

Next, as shown in FIG. 1(C), the first side wall 10 is removed by etching with hot phosphoric acid.

At this time, the second insulating film 8 in the vicinity is
A zero-person side etching is performed to form the eroded portion 8a.

Then, a p-type impurity is introduced into the n-type epitaxial layer 3 by thermal diffusion or ion implantation through the opening of the sidewall trace exposed by the formation of the eroded portion 8a, thereby forming a p-type graft base region 12.

Next, as shown in FIG. 1(d), a second polycrystalline silicon film 13 having a thickness of <2,000 to 4,000 thick is formed over the entire surface so as to cover at least the side wall traces. This second polycrystalline silicon film 13 is doped with p-type impurities, and by diffusing the p-type impurities from there into the graft base region 12, the concentration of the graft base region 12 is further increased. In this case, even if the second polycrystalline silicon film 13 does not contain p-type impurities, since the first polycrystalline silicon film 6 contains p-type impurities, this impurity
The graft base region 1 is passed through the polycrystalline silicon film 13 of
It is also possible to spread to 2.

Next, as shown in FIG. 1(e), an insulating film such as a silicon nitride film or an alumina film, which is an oxidation-resistant film, is
A second sidewall 14 is formed on the inner surface of the second polycrystalline silicon film 13 by growing a layer of 0 to 2,000 layers and etching it by RIE.

Next, as shown in FIG. 1(f), the second polycrystalline silicon film 13 is etched using RIE. The amount of etching is 30 to 100% over-etching, but at this time, a part of the second polycrystalline silicon film 13 at a position outside the second side wall 14 is etched by 2,000 to 2,500 percent of the second side wall 14. Make sure that a hollow is formed at the depth of the hole. Thereafter, the exposed surface of the second polycrystalline silicon film 13 is oxidized for approximately 500 minutes at a temperature of 900'C to form a silicon oxide film 15. This silicon oxide film 15
A recess 15a is formed in. After this, p
A type impurity is ion-implanted to form an active base region 16.

Next, as shown in FIG. 1(g), a fifth insulating film 17 made of the same silicon nitride film or alumina film as the second sidewall 14 is grown by low pressure CVD with good step coverage.

The film thickness at this time is the film thickness 20 of the second polycrystalline silicon film 13.
The recess 15a is backfilled by growing the film to a thickness of at least 1/2 or more of that of 00 to 4000.

Next, as shown in FIG. 1(h), the fifth insulating film 17 is anisotropically etched by RIE, and subsequently the fourth insulating film 11 is also anisotropically etched, and the active base region 16 is anisotropically etched. to expose.

Next, as shown in FIG. 1(i), a third polycrystalline silicon film 18 is grown, and arsenic ions are implanted and
Arsenic is diffused into active base region 16 by heat treatment at 50''C to form emitter region 19.

Thereafter, the third polycrystalline silicon film 18 is selectively etched to form a collector contact opening 20, a base contact opening 21, and the like.

Although the following steps are not shown, the bipolar transistor is completed by performing normal electrode formation such as electrode wiring formation using an aluminum film or the like.

〔Effect of the invention〕

As explained above, the present invention forms an eroded part using the first side wall provided inside the opening of the insulating film, forms a graft base region through this eroded part, and forms the first side wall provided inside the opening. Since the base region and emitter region are sequentially formed using the sidewalls of 2, the base region and emitter region can be formed with finer dimensions than are limited by lithography technology, reducing junction capacitance and base resistance. In addition, it is possible to manufacture a bipolar transistor with improved high frequency characteristics such as cut-off frequency.

[Brief explanation of the drawing]

FIGS. 1(a) to 1(i) are cross-sectional views showing an embodiment of the present invention in the order of steps, and FIG. 2 is a cross-sectional view of a conventional structure. DESCRIPTION OF SYMBOLS 1...p-type semiconductor substrate, 2...n-type buried layer, 3...
... n-type epitaxial layer, 4... insulating region, 5...
・First insulating film, 6... First polycrystalline silicon film, 7
. . . n-type collector extraction diffusion layer, 8 . . . second insulating film, 8a . . . eroded portion, 9 . . . third insulating film, 1
0... First side wall, 11... Fourth insulating film, 12...
... Graft base region, 13... Second polycrystalline silicon film, 14... Second sidewall, 15... Oxide film, 1
5a... recess, 16... active base region, 17...
・Fifth insulating film, 18... third polycrystalline silicon film,
19... Emitter region, 20.21... Contact opening, 31... Semiconductor substrate, 32... N° type buried layer, 33... N type epitaxial layer, 34... Insulating region, 35... Thin insulating film, 36... Polycrystalline silicon film, 37... Insulating film, 38... Polycrystalline silicon film,
39... Graft base region, 40... Insulating film, 4
1... Base region, 42... Polycrystalline silicon, 43
...Emitter area. Diagram

Claims (1)

[Claims] 1. A first insulating film, a first polycrystalline silicon film containing an opposite conductivity type impurity, a second insulating film, and a third insulating film on a semiconductor layer of one conductivity type in an element formation region insulated from the surroundings. a step of sequentially stacking films, a step of anisotropically etching each of the films to expose the surface of the one conductivity type semiconductor layer, a step of forming a first sidewall inside the opening, and a step of stacking the first sidewall inside the opening. forming a fourth insulating film on the surface of the conductivity type semiconductor layer, removing at least the first sidewall to form an eroded part, and introducing an opposite conductivity type impurity into the one conductivity type semiconductor layer through the eroded part; forming a graft base region, embedding a second polycrystalline silicon film in the eroded portion to connect it to the graft base region, and forming a second sidewall inside the second polycrystalline silicon film. At the same time, a process of surface oxidizing the second polycrystalline silicon film and forming a fifth insulating film, and introducing an opposite conductivity type impurity into the one conductivity type semiconductor layer within this second sidewall to form an active base. a step of forming a region;
exposing the one conductivity type semiconductor layer inside the second sidewall and forming a third polycrystalline silicon film thereon; 1. A method for manufacturing a bipolar transistor, comprising the step of introducing an impurity to form an emitter region.