JPH0691101B2 - Bipolar transistor manufacturing method - Google Patents

Description

The present invention relates to a method for manufacturing a bipolar transistor, and more particularly to a method for manufacturing a bipolar transistor having improved high frequency characteristics.

[Conventional technology]

Conventionally, there is known a structure in which a graft base is formed in a self-aligned manner using a polycrystalline silicon film of a base electrode as a diffusion source in order to realize a high-speed transistor by reducing the base resistance and its junction capacitance. For example, FIG. 2 is a sectional view of a conventional bipolar transistor of this type.

In order to manufacture this structure, first, an n ⁺ type buried layer 32 is formed on a semiconductor substrate 31 made of p type silicon, an n type epitaxial layer 33 is grown on this, and then an SiO ₂ layer is made of SiO _2. The thick insulating region 34 insulates and separates the element forming region, and the thin insulating film 35 is formed in the element forming region.

Then, a polycrystalline silicon film 36 containing a p-type impurity and an insulating film 37 are sequentially formed, and then a window is opened in the insulating film 37.
Using this insulating film 37 as a mask, the polycrystalline silicon film 36 and the insulating film 35 are etched to open a wider window.

Further, a polycrystalline silicon film 38 containing a p-type impurity is formed under the eaves of the insulating film 37, and the polycrystalline silicon film 38 is used as a diffusion source in a self-aligned manner on the surface of the epitaxial layer 33 to form a graft base region 39. To form.

Subsequently, an insulating film 40 for separating the emitter / base electrode is formed in the opening, and p-type impurities are introduced into the surface of the opening of the epitaxial layer 33 by an ion implantation method or the like to form the base region 41.
To form. Further, polycrystalline silicon 42 is grown on the opening and an n-type impurity is introduced by an ion implantation method to form an emitter region 43.

[Problems to be Solved by the Invention]

The conventional bipolar transistor manufacturing method described above is
Since the graft base region 39 is formed in a self-aligned manner, the base resistance and collector matching capacitance can be reduced. However, the polycrystalline silicon film 38 for forming the graft base region 39 has an opening in the insulating film 37. Since it is formed outside, the area of the entire base region including the graft base region 39 is larger than the minimum lithographically possible opening. Therefore, there is a limit in further reducing the resistance of the base region to reduce the junction capacitance and improve the high frequency characteristics such as the cutoff frequency.

Further, when removing the polycrystalline silicon 42 grown on the opening to form the emitter region 43, the etching must be controlled in consideration of the selection ratio with the underlying epitaxial layer 33, and this control is performed. There is also the problem of difficulty.

An object of the present invention is to provide a method for manufacturing a bipolar transistor, which can reduce a junction capacitance and can easily obtain a bipolar transistor excellent in high frequency characteristics.

[Means for Solving the Problems]

According to the method of manufacturing a bipolar transistor of the present invention, the erosion portion is formed by using the first side wall provided inside the opening of the insulating film, the graft base region is formed through the erosion portion, and the bipolar transistor is provided inside the opening. A base region and an emitter region are sequentially formed using the second side wall.

[Action]

In the above-mentioned manufacturing method, the graft base region is formed in the opening by utilizing the eroded portion in the opening, and the base region and the emitter region are further formed inside the graft base region. Is also formed in a fine dimension.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

1 (a) to 1 (i) are longitudinal sectional views showing an embodiment of the present invention in the order of steps.

First, as shown in FIG. 1 (a), p made of silicon is used.
An n ⁺ type buried layer 2 is formed on the surface of the type semiconductor substrate 1, and an n type epitaxial layer 3 is formed thereon with a thickness of 0.5 to 1.0 μm. Further, the element forming region which is insulated and separated is divided by the insulating region 4 made of SiO ₂ and the pn junction (not shown). Then, a first insulating film 5 made of SiO ₂ and a first polycrystalline silicon film 6 containing a p-type impurity are sequentially deposited in the element formation region and left in a predetermined region including the element formation region. Then, the first polycrystalline silicon film 6 is selectively removed. An n-type impurity is introduced at a high concentration into a part of the epitaxial layer 3 to form an n-type collector extraction diffusion layer 7.

Subsequently, a silicon nitride film which is an oxidation resistant film is sequentially deposited as the second insulating film 8 and a silicon oxide film is sequentially deposited as the third insulating film 9, and the third insulating film 9 and the second insulating film 9 in the emitter formation region are sequentially deposited. Insulating film 8, first polycrystalline silicon film 6, and first insulating film 5
Are sequentially and selectively anisotropically etched to form openings.

Next, as shown in FIG. 1B, the same silicon nitride film as the second insulating film 8 is deposited to a thickness of 1500 to 3000 Å, and the vertical sidewalls are formed by reactive ion etching (hereinafter referred to as RIE). The first side wall 10 is formed by etching except. Such RIE technology is known and disclosed in, for example, US Pat. No. 4,243,362. Then, the exposed surface of the n-type epitaxial layer 3 is oxidized by 1000 to 2000 Å to form a fourth insulating film 11 made of a silicon oxide film. At this time, the side surface of the opening in the emitter formation region is protected by the first side wall 10 and serves to prevent the oxidation of the first polycrystalline silicon film 6 inside.

Then, as shown in FIG. 1C, the first side wall 10 is removed by etching with hot phosphoric acid. At this time, the second insulating film 8 in the vicinity thereof is side-etched by 2000 to 3000 Å to form the eroded portion 8a. Then, p-type impurities are introduced into the n-type epitaxial layer 3 by thermal diffusion or ion implantation from the opening of the side wall trace exposed by the formation of the eroded portion 8a to form the p-type graft base region 12.

Next, as shown in FIG. 1 (d), a second polycrystalline silicon film having a thickness of 2000 to 4000 Å so as to cover at least the side wall traces.
13 is formed on the entire surface. A p-type impurity is added to the second polycrystalline silicon film 13, and the concentration of the graft base region 12 is further increased by diffusing the p-type impurity into the graft base region 12. In this case, even if the second polycrystalline silicon film 13 does not include the p-type impurity, the p-type impurity is present in the first polycrystalline silicon film 6, and therefore, the impurity is not included in the second polycrystalline silicon film 6. Membrane 13
It is also possible to diffuse through to the graft base region 12.

Next, as shown in FIG. 1 (e), an insulating film such as a silicon nitride film or an alumina film, which is an oxidation resistant film, is applied to 1000
The second side wall 14 is formed on the inner side surface of the second polycrystalline silicon film 13 by growing 2000 Å and etching it by the RIE method.

Next, as shown in FIG. 1F, the second polycrystalline silicon film 13 is etched by using RIE. The etching amount is 30% to 100% overetching. At this time, a part of the second polycrystalline silicon film 13 at the position outside the second sidewall 14 has a thickness of 2000 to 2500Å with respect to the second sidewall 14. Make it possible to engrave in the depth to form a depression. After that, the exposed surface of the second polycrystalline silicon film 13 is heated to 900 ° C.
The silicon oxide film 15 is formed by oxidizing about 500Å at the temperature. A recess 15a is formed in the silicon oxide film 15. After that, p-type impurities are ion-implanted through the opening to form the active base region 16.

Next, as shown in FIG. 1G, a fifth insulating film 17 made of the same silicon nitride film or alumina film as the second side wall 14 is grown by the low pressure CVD method with good step coverage. At this time, the thickness of the second polycrystalline silicon film 13 is 2000 to 4000Å
To grow the film thickness of at least 1/2 or more to fill back the recess 15a.

Next, as shown in FIG. 1 (h), the fifth insulating film 17 is removed by RI.
Anisotropically etched with E, and then the fourth insulating film 1
Similarly, 1 is anisotropically etched to expose the active base region 16.

Next, as shown in FIG. 1 (i), a third polycrystalline silicon film 18 is grown, and arsenic is ion-implanted and heat-treated at 900 to 950 ° C. to diffuse arsenic into the active base region 16 so that the emitter region is formed. Forming 19. After that, the third polycrystalline silicon film 18
Are selectively etched to form a collector contact opening 20 and a base contact opening 21.

Although not shown in the following steps, the bipolar transistor is completed by performing normal electrode formation such as electrode wiring formation using an aluminum film or the like.

〔The invention's effect〕

As described above, according to the present invention, the erosion portion is formed by using the first side wall provided inside the opening of the insulating film, the graft base region is formed through the erosion portion, and the first sidewall provided inside the opening is formed. Since the base region and the emitter region are sequentially formed by using the sidewalls of 2, the base region and the emitter region can be formed in a finer dimension than that limited by the lithography technique, and the junction capacitance and the base resistance can be reduced. In addition, it is possible to manufacture a bipolar transistor having improved high frequency characteristics such as cutoff frequency.

[Brief description of drawings]

1 (a) to 1 (i) are sectional views showing an embodiment of the present invention in the order of steps, and FIG. 2 is a sectional view of a conventional structure. 1 ... p-type semiconductor substrate, 2 ... n ⁺ type buried layer, 3 ... n-type epitaxial layer, 4 ... insulating region, 5 ... first insulating film, 6 ... first polycrystalline silicon Membrane, 7 ... N ⁺ type collector extraction diffusion layer, 8 ... Second insulation film, 8a ... Erosion part, 9 ... Third insulation film, 10 ... First side wall, 11 ... Fourth Insulating film, 12 ... Graft base region, 13 ... Second polycrystalline silicon film, 14 ... Second side wall, 15 ... Oxide film,
15a ... recess, 16 ... active base region, 17 ... fifth insulating film, 18 ... third polycrystalline silicon film, 19 ... emitter region, 20,21 ... contact opening, 31 ... semiconductor Board, 3
2 …… n ⁺ type buried layer, 33 …… n type epitaxial layer, 34…
Insulating region, 35 ... Thin insulating film, 36 ... Polycrystalline silicon film, 37 ... Insulating film, 38 ... Polycrystalline silicon film, 39 ... Graft base region, 40 ... Insulating film, 41 ... Base region,
42 ... Polycrystalline silicon, 43 ... Emitter region.

Claims (1)

[Claims] 1. A first insulating film, a first polycrystalline silicon film containing impurities of opposite conductivity type, a second insulating film, and a second insulating film on a semiconductor layer of one conductivity type which is isolated from the surroundings and isolated from the surroundings. 3 sequentially stacking insulating films, and anisotropically etching each film to expose the surface of the one conductivity type semiconductor layer.
Forming a first side wall inside the opening; forming a fourth insulating film on the surface of the one conductivity type semiconductor layer in the opening; and removing at least the first side wall to form an erosion part. A step of introducing an opposite conductivity type impurity into the one conductivity type semiconductor layer through the erosion portion to form a graft base region, and a step of burying a second polycrystalline silicon film in the erosion portion and connecting to the graft base region. And forming a second side wall inside the second polycrystalline silicon film,
A step of surface-oxidizing the second polycrystalline silicon film and forming a fifth insulating film, and introducing an impurity of opposite conductivity type into the semiconductor layer of one conductivity type in the second sidewall to form an active base region. A step of exposing the one-conductivity-type semiconductor layer inside the second sidewall, and forming a third polycrystalline silicon film on the semiconductor layer, and forming a third polycrystalline silicon film on the base region through the third polycrystalline silicon film. And a step of introducing an impurity of one conductivity type to form an emitter region.