JPH0722431A - Manufacture of bipolar transistor - Google Patents

Abstract

PURPOSE:To lower the temperature of a bipolar transistor manufacturing process, and to form thin base layers. CONSTITUTION:When an emitter region 8 is formed after the formation of a base region 7, a thin second insulating film 12 and amorphous silicon 15 containing impurities of a conductivity type the same as that of the collector are laminated on the sidewall of an opening 7a, and the amorphous silicon 15 in the opening is removed and opened by dry etching and the insulating film 12 is exposed. Furthermore, the insulating film is removed and opened with an etching solution, and the base region 8 is exposed. Finally, an emitter electrode 11 is formed with polycrystalline silicon along with the formation of the emitter region 8 by the injection of impurities of a conductivity type the same as that of the collector. Consequently, high speed operation of the device becomes feasible since it becomes possible to thin the base layer. Besides, it becomes possible to reduce the emitter resistance approximately to 70% of the former value. Furthermore, it becomes possible to prevent the emitter and the collector from being short-circuited electrically, since the emitter electrode on the opening hem is removed in a contact-hole-forming process.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a bipolar transistor, and more particularly to a method for manufacturing a thin base layer.

[0002]

2. Description of the Related Art As a conventional technique relating to a method of manufacturing a high performance bipolar transistor, for example, a method of manufacturing a bipolar transistor structure shown in FIG. 6 has been proposed. In the figure, 1 is a silicon substrate having one conductivity type, 2 is an epitaxial growth layer having an opposite conductivity type, 3 is an insulating isolation region, 4 is an active region, 5 is a high conductivity buried diffusion layer of one conductivity type,
6 is a low concentration layer of one conductivity type, 7 is a base region having an opposite conductivity type, 8 is an emitter region having one conductivity type, 9 is a polycrystalline silicon layer containing a high concentration of impurities of the opposite conductivity type, and 10 is A silicon oxide film, 11 is an emitter electrode, and 12 is a side wall made of a silicon oxide film.

The bipolar transistor of FIG. 6 is formed by the manufacturing method described below. First, a polycrystalline silicon layer 9 containing a high concentration of impurities of opposite conductivity type and a silicon oxide film 10 are deposited on the surface of the active region 4, and the silicon oxide film 1 is selectively formed using a mask made of a photoresist film.
0 and the polycrystalline silicon layer 9 are removed to form an opening, and a side wall 12 made of a silicon oxide film is formed by thermal oxidation, and at the same time, an external base 17 is formed by thermal diffusion.

Next, the emitter portion is opened using the silicon oxide film 10 and the polycrystalline silicon layer 9 as a mask, and an impurity of opposite conductivity type and then an impurity of one conductivity type are introduced by ion implantation. Then, heat treatment is performed to form the base region 7 and the emitter region 8. Then, an emitter electrode 11, a base wiring 13 that contacts the polycrystalline silicon layer 9 and a collector electrode 14 are formed on the emitter region 8.

Note that, as a technique related to this kind of technique, for example, I.D.M., Technical Digest, 1986, pp. 420-423 [Te
ch. Dig. IEDM (1986), pp420-4
23].

[0006]

In the above conventional manufacturing method, the silicon oxide film 12 for separating the polycrystalline silicon layer 9 and the emitter electrode 11 is formed by thermal oxidation at about 1000 ° C. for 30 minutes. As a result, the junction in the base region becomes deep, and high-speed operation of the device cannot be expected. Therefore, a method of forming the silicon oxide film 12 on the extremely thin thermal oxide film underlayer by a chemical vapor deposition method (CVD method) has been devised for forming a shallow junction of the element. It is hard to say that a shallow junction was achieved because an equivalent anneal of 900 ° C. for 10 minutes was applied.

Therefore, a main object of the present invention is to solve the above-mentioned conventional problems, and to provide a method for manufacturing a bipolar transistor in which the base layer is thinned by lowering the temperature of the manufacturing process. Especially.

In addition, the miniaturization of the emitter size is required for higher performance and higher integration, but in the above conventional structure, the emitter resistance increases with the miniaturization of the emitter size. Therefore, another object of the present invention is to provide a method of manufacturing an emitter electrode in which the emitter resistance does not increase even if the emitter size is reduced.

In addition, in the conventional manufacturing method, anisotropic etching using the reactive ion etching method is required for the final opening step of the emitter portion, but the reactive ion etching method does not damage the surface of the silicon substrate. Performance is degraded due to Therefore, another object of the present invention is to provide a manufacturing method in which the last opening of the emitter section is performed with an aqueous solution of hydrofluoric acid so as not to give damage to the surface of the silicon substrate.

In addition, in the conventional manufacturing method, the insulating film is selectively removed by using the reactive ion etching method to form the contact hole for the wiring. At this time, the emitter electrode on the edge of the opening is removed. Of the polycrystalline silicon is removed, and a short circuit occurs between the emitter and the base due to the wiring. Therefore, another object of the present invention is to manufacture the emitter electrode on the edge of the opening with a thick film of polycrystalline silicon in order to prevent the polycrystalline silicon of the emitter electrode on the edge of the opening from being removed by forming a contact hole. To provide a method.

Further, in the above conventional manufacturing method, since the base layer is formed by the ion implantation method, it is necessary to anneal at 900 ° C. or higher in order to recover the defects caused by the ion implantation. -There is a limit to how thin the layer can be made. Therefore, another object of the present invention is to provide a method for manufacturing a bipolar transistor which forms a defect-free thin base layer.

[0012]

The above object is to provide a base on a semiconductor substrate on which a collector layer having one conductivity type is formed.
A step of depositing polycrystalline silicon containing impurities of opposite conductivity type to serve as a gate electrode, and then stacking a first insulating film on the polycrystalline silicon, and selectively using a mask made of a photoresist film to form the first insulating film. A step of removing the insulating film and the polycrystalline silicon to form an opening in a region for forming a base;
A step of introducing an impurity of opposite conductivity type to form a base region using the insulating film as a mask, and depositing a second insulating film,
Next, a step of forming amorphous or polycrystalline silicon containing one conductivity type impurity formed from a gas mixed with impurities of one conductivity type on the sidewall of the opening, and exposing the base region in the opening And a step of introducing an impurity of one conductivity type through the opening with the use of the first insulating film as a mask to form an emitter region.

A typical manufacturing process example will be described in more detail with reference to FIG. 5. On the semiconductor substrate 16 on which a collector layer having one conductivity type is formed as shown in the figure, an impurity of opposite conductivity type serving as a base electrode is formed. A step of depositing a polycrystalline silicon film 9 containing silicon, and then laminating a silicon oxide film 10 as a first insulating film on the polycrystalline silicon film 9, and using the photoresist film as a mask to selectively form the silicon oxide film 10 and the polycrystalline silicon film. A step of removing the silicon 9 to form an opening in a region where the intrinsic base 7 is formed, and a step of introducing an impurity of opposite conductivity type with the silicon oxide film 10 as a mask to form the base region 7. , A thin silicon oxide film 12 is deposited in the opening as a second insulating film, and then amorphous silicon (or polycrystalline silicon) 15 formed from a gas mixed with impurities of one conductivity type is formed in the opening. A step of forming on the sidewall, a step of forming an opening in the base region 7 again using the amorphous silicon 15 as a mask, and an impurity of one conductivity type being introduced through the opening to form the emitter region 8 are formed. And forming the emitter electrode 11 of crystalline silicon.

Another object is to deposit polycrystalline silicon containing impurities of opposite conductivity type to serve as a base electrode on a semiconductor substrate on which a collector layer having one conductivity type is formed, and then deposit polycrystalline silicon. A step of laminating a first insulating film on silicon, and a step of forming a shallow base region by thermally diffusing the opposite conductivity type impurities in the semiconductor substrate by using the polycrystalline silicon as an impurity source of the opposite conductivity type. And a step of selectively removing the first insulating film and the polycrystalline silicon using a mask made of a photoresist film to form an opening in a region where an emitter is formed, and depositing a second insulating film. Then, a step of forming amorphous or polycrystalline silicon containing one conductivity type impurities formed from a gas mixed with one conductivity type impurities on the sidewall of the opening, and a base in the opening.
This is accomplished by a method of manufacturing a bipolar transistor, which includes a step of exposing the drain region and a step of introducing an impurity of one conductivity type through the opening to form an emitter region.

An example of a typical manufacturing process will be described in more detail with reference to FIG. 13. On the semiconductor substrate 16 on which a collector layer having one conductivity type is formed as shown in the figure, impurities of opposite conductivity type serving as a base electrode are formed. Depositing polycrystalline silicon 9 containing
Next, a step of laminating a silicon oxide film 10 as a first insulating film on the polycrystalline silicon 9 and a thermal diffusion of impurities of opposite conductivity type into the semiconductor substrate 16 using the polycrystalline silicon 9 as an impurity source of opposite conductivity type are performed. A step of forming a shallow base region 7, a step of selectively removing the silicon oxide film 10 and the polycrystalline silicon 9 using a photoresist film as a mask to form an opening in a region where an emitter is formed, and an opening Then, a thin silicon oxide film 12 is deposited as a second insulating film, and then amorphous silicon (or polycrystalline silicon) 15 formed from a gas mixed with impurities of one conductivity type is formed on the sidewall of the opening. A step of forming an opening in the base region 7 again using the amorphous silicon 15 as a mask and exposing the base region 7 in the opening; and impurities of one conductivity type through the opening. Baipo and forming an emitter region 8 by entering - is achieved by the method for producing a la transistor.

Still another object is to provide a base on a semiconductor substrate having a collector layer having one conductivity type formed thereon.
A step of depositing polycrystalline silicon containing impurities of opposite conductivity type to serve as a gate electrode, and then stacking a first insulating film on the polycrystalline silicon, and selectively using a mask made of a photoresist film to form the first insulating film. A step of removing the insulating film and the polycrystalline silicon to form an opening in a region for forming a base;
A step of forming a base region containing impurities of opposite conductivity type by using an epitaxial growth method, a step of burying a photoresist film in the opening region in a self-aligned manner, and a step of depositing a part other than the opening region during the epitaxial growth step. Two
Of the epitaxial growth layer using a photoresist film as a mask, a step of removing the photoresist film, a second insulating film is deposited, and then a one-conductivity-type film formed from a gas mixed with one-conductivity-type impurities is formed. Amorphous or polycrystalline silicon containing impurities is formed on the sidewall of the opening, a base region formed by an epitaxial growth method is exposed in the opening, and an impurity of one conductivity type is introduced through the opening. And forming an emitter region by means of a method of manufacturing a bipolar transistor.

A typical manufacturing process example will be described in more detail with reference to FIG. 18. On the semiconductor substrate 16 on which a collector layer having one conductivity type is formed as shown in the figure, an impurity of opposite conductivity type serving as a base electrode is formed. Depositing polycrystalline silicon 9 containing
Then, a step of laminating a silicon oxide film 10 as a first insulating film on the polycrystalline silicon 9 and an intrinsic base by selectively removing the silicon oxide film 10 and the polycrystalline silicon 9 using a photoresist film as a mask A step of forming an opening in a region for forming a trench, a step of forming a base region 7 containing an impurity of an opposite conductivity type by epitaxial growth, a step of burying a resist film 19 in a self-aligning manner in the opening region, and the epitaxial growth. The epitaxial growth layer other than the opening region deposited in the step is removed using the resist film 19 as a mask, then the resist film 19 is removed, and a thin silicon oxide film 12 is deposited in the opening as a second insulating film. Next, a process of forming amorphous silicon (or polycrystalline silicon) 15 formed from a gas mixed with impurities of one conductivity type on the sidewall of the opening And a step of forming an opening in the base region 7 again using the amorphous silicon 15 as a mask and exposing the base region 7 formed by epitaxial growth in the opening, and introducing an impurity of one conductivity type through the opening. And a step of forming the emitter region 8 to form a bipolar transistor.

In any of the above manufacturing methods, polycrystalline silicon 9, a silicon oxide film 10 as a first insulating film,
The silicon oxide film 12, the amorphous silicon 15 and the emitter electrode 11 as the second insulating film are formed by the CVD method. The amorphous silicon 15 is formed by the low pressure CVD method because it can be processed at a low temperature. Is desirable.

The total film thickness of the thin silicon oxide film 12 as the second insulating film formed on the side wall of the opening and the amorphous or polycrystalline silicon 15 containing impurities of one conductivity type is It is necessary to be as thin as possible and to be able to sufficiently compensate the withstand voltage.
0.3 μm is preferable, and the thickness of the amorphous or polycrystalline silicon is preferably 0.05 to 0.15 μm.

The semiconductor substrate and the epitaxial growth layer are generally made of silicon semiconductor, but it goes without saying that other compound semiconductors such as GaAs may be used.

[0021]

The thin CVD oxide film 1 serving as the second insulating film is formed in the region separating the polycrystalline silicon 9 and the emitter electrode 11.
2 and amorphous silicon 15 containing impurities of opposite conductivity type deposited at about 500 ° C. by using low pressure chemical vapor deposition (low pressure CVD method) to lower the temperature of the process. By this manufacturing method, the base layer 7 can be thinned, and the device can be speeded up.

A thin CVD oxide film 1 serving as a second insulating film in a region separating the polycrystalline silicon 9 and the emitter electrode 11.
2 and amorphous silicon 15 containing an impurity of one conductivity type, and the opening of the emitter section is performed with an aqueous solution of hydrofluoric acid using the amorphous silicon 15 as a mask. With this manufacturing method, it is possible to form an emitter electrode in which the emitter resistance does not increase even if the emitter size is reduced.

The silicon oxide film 12 is removed with an aqueous solution of hydrofluoric acid by using the amorphous silicon 15 containing an impurity of one conductivity type as a mask in the emitter opening. By this manufacturing method, the silicon oxide film 12 can be selectively removed without damaging the surface of the silicon substrate.

The polycrystalline silicon emitter electrode on the edge of the opening is thickened. By this manufacturing method, it is possible to prevent the emitter electrode 11 on the edge of the opening from being thinned by forming the contact hole.

The shallow base region 7 is formed by thermally diffusing the opposite conductivity type impurities into the semiconductor substrate 16 using the polycrystalline silicon 9 as an impurity source of the opposite conductivity type. With this manufacturing method, the ion implantation step of the base and the defects due to the ion implantation can be eliminated, so that the process can be simplified and the temperature can be reduced, and the element can be speeded up by thinning the base layer.

The base layer 7 is formed by the epitaxial growth method.
By forming the, it is possible to realize a thin base layer,
The speed of the device can be increased.

[0027]

An embodiment of the present invention will be described in detail below with reference to the drawings. <Embodiment 1> FIGS. 1 to 5 are sectional views of a manufacturing process showing a state of an active region 4 which is a main part of a bipolar transistor according to the present invention. Hereinafter, description will be sequentially made according to these process drawings. To do.

First, as shown in FIG. 1, on a silicon semiconductor substrate 16 on which a collector layer having one conductivity type is formed,
Polycrystalline silicon 9 containing impurities of opposite conductivity type, which will serve as a base electrode, is deposited according to a well-known CVD method. In addition,
An insulating isolation region 3 is formed around the active region 4.

Next, as shown in FIG. 2, polycrystalline silicon 9
A silicon oxide film 10 serving as a first insulating film is formed on the well-known C
The layers are stacked according to the VD method, and the silicon oxide film 10 and the polycrystalline silicon 9 are selectively removed by the reactive ion etching method using the photoresist film as a mask to remove the intrinsic base.
The opening 7a is formed in the region where the spacer 7 is formed.

Next, as shown in FIG. 3, after heat treatment is performed to form the outer base 17, impurities of opposite conductivity type are introduced by ion implantation using the silicon oxide film 10 as a mask and heating. By processing, impurities of opposite conductivity type are activated to form the intrinsic base region 7. Then, a thin silicon oxide film 12 to be the second insulating film is deposited in a short time using the CVD method. In this case, the silicon oxide film 12 having a thickness of 0.05 μm was deposited at 800 ° C. for 30 minutes.

Next, as shown in FIG. 4, low pressure CVD is performed using a reaction gas mixed with one conductivity type impurities (phosphorus or arsenic), for example, a mixed gas of disilane (Si ₂ H ₆ ) and phosphine (PH ₃ ). By the method at 500 ° C. to deposit the amorphous silicon 15 containing a one-conductive type impurity having a film thickness of 0.1 μm. Normal CVD may be used instead of the low pressure CVD method, but the low pressure CVD method is preferable because low temperature treatment is possible. Then, using the reactive ion etching method, the amorphous silicon 15 is left on the side wall of the opening 7a as shown in the drawing, and the other portions are selectively removed. This etching amount is set to about the film thickness of the amorphous silicon 15 deposited by the above method.

During the reactive ion etching process at this time, the underlying silicon oxide film 12 effectively acts as a stopper to protect the surface of the base 7. Therefore, there is no problem that a crystal defect is generated on the surface of the base 7 due to overetching, or the base 7 is seriously etched unlike the conventional case, and highly reliable etching can be realized.

Next, as shown in FIG. 5, amorphous silicon 1
5, the thin silicon oxide film 12 in the opening 7a is removed by etching with a hydrofluoric acid-based aqueous solution, and the base region 7 is formed.
Expose. In the step of exposing the base region 7 by this etching, wet etching as described above is preferable, and dry etching is not preferable because it may cause crystal defects in the base region 7. Then, an impurity of one conductivity type is introduced through the opening to form the emitter region 8. In this example, as shown in the figure, the second amorphous silicon containing one conductivity type impurity was formed, and the emitter region 8 and the polycrystalline silicon emitter electrode 11 were simultaneously formed by heat treatment.

The bipolar transistor of Example 1 was formed by the above steps. After this, as shown in the conventional example of FIG.
3, the collector electrode 14 was formed.

According to the present embodiment, the thin CVD oxide film 1 is formed in the region separating the polycrystalline silicon 9 and the emitter electrode 11.
2 and about 5 by low pressure chemical vapor deposition (low pressure CVD method)
Since it is formed of amorphous silicon 15 containing an impurity of one conductivity type deposited at 00 ° C., the process temperature can be lowered. As a result, diffusion of impurities of the opposite conductivity type in the base region 7 is reduced and the base layer 7 is thinned, so that the device can be sped up. In addition, since the current density in the polycrystalline silicon emitter electrode is reduced by this structure, the emitter resistance is about 3
It decreased by 0%. Furthermore, when exposing the base region 7 in the opening for forming the emitter, the amorphous silicon 15 is subjected to a dry etching process, and the underlying CVD oxide film 12 is subjected to a wet etching process. It was possible to realize extremely reliable selective etching without causing crystal defects in No. 7.

<Embodiment 2> FIG. 7 shows SICOS (sidewa
(ll base contact structure) The manufacturing method of the present invention is applied to the formation of the emitter electrode 11 of the transistor. The step of forming the emitter electrode 11 is the same as in the first embodiment.
The description is omitted because it is the same as.

<Third Embodiment> FIG. 8 shows the fabrication of the present invention for forming an emitter electrode 11 of a transistor (commonly referred to as SST) capable of separating the emitter 8 and the base extraction electrode 9 in a self-aligned manner. The method is applied. In addition,
The process of forming the emitter electrode 11 is the same as that of the first embodiment, and therefore its explanation is omitted.

<Embodiment 4> FIGS. 9 to 13 are sectional views showing the state of the active region 4, which is the main part, in the order of manufacturing steps as in the case of the embodiment 1. First, as shown in FIG. 9, polycrystalline silicon 9 containing impurities of opposite conductivity type to serve as a base electrode is deposited on semiconductor substrate 16 on which a collector layer having one conductivity type is formed.

Then, as shown in FIG. 10, a silicon oxide film 10 serving as a first insulating film is laminated on the polycrystalline silicon 9, and the polycrystalline silicon 9 is used as an impurity source of opposite conductivity type.
The shallow base region 7 is formed by thermally diffusing the impurities of the opposite conductivity type into the semiconductor substrate 16. When impurities of opposite conductivity type are introduced into the polycrystalline silicon 9 by the ion implantation method, heat treatment is required to recover the defects caused by the ion implantation. However, this heat treatment and the heat treatment for forming the base region can be combined.

In order to form the shallow base region 7, a reaction gas mixed with impurities of opposite conductivity type, for example, a mixed gas of monosilane (SiH ₄ ) and diborane (B ₂ H ₆ ) is reacted at 500 ° C. It is also possible to form the polycrystalline silicon 9 by heat treatment at about 700 ° C. from amorphous silicon containing impurities of the opposite conductivity type formed as described above. Since the grain size of the polycrystalline silicon 9 formed by this method grows to a large grain size of several μm, the specific resistance becomes about half that of the polycrystalline silicon formed by the ion implantation method. When a circuit is composed of the elements manufactured according to this example, the circuit performance is improved by about 10%.

Next, as shown in FIG. 11, using the photoresist film as a mask, the silicon oxide film 10 and the polycrystalline silicon 9 are selectively removed by reactive ion etching to form an opening 7a in a region where an emitter is formed. And a thin silicon oxide film 12 to be a second insulating film as shown in FIG.
Are deposited in a short time using the CVD method. The method for forming the opening and the method for forming the silicon oxide film 12 are the same as those in the first embodiment shown in FIGS.

Next, as shown in FIG. 12, an outer base 17 is formed by heat treatment. After that, following the same steps as in Example 1, after forming amorphous silicon 15 containing an impurity of one conductivity type on the sidewall of the opening 7a, the emitter electrode 11 is formed as shown in FIG. A bipolar transistor was formed.

According to the present embodiment, since the intrinsic base region 7 is formed by thermal diffusion, there is no need for heat treatment for recovering the defects caused by the ion implantation, and the thin base layer 7 is defect-free. The obtained device can operate at high speed.

<Embodiment 5> FIGS. 14 to 18 are sectional views showing the state of the active region 4, which is the main part, in the order of manufacturing steps, as in the case of the embodiment 1. First, as shown in FIG. 14, a semiconductor substrate 16 on which a collector layer having one conductivity type is formed.
After depositing polycrystalline silicon 9 containing impurities of opposite conductivity type to serve as a base electrode, a first electrode is formed on the polycrystalline silicon 9.
A silicon oxide film 10 to be an insulating film is laminated.

Next, as shown in FIG. 15, the region where the intrinsic base 7 is formed by selectively removing the silicon oxide film 10 and the polycrystalline silicon 9 by the reactive ion etching method using the photoresist film as a mask. The opening 7a is formed in the. Thereafter, as shown in the figure, an intrinsic base region 7 containing impurities of opposite conductivity type is formed by epitaxial growth. In this embodiment, the polycrystalline silicon film is deposited on the portion where the surface is not single crystal silicon, but when the selective epitaxial growth method is used, the single crystal silicon film grows only on the active region of the opening portion.

Next, as shown in FIG. 16, a photoresist is applied and a resist film 19 is embedded in the opening region in a self-aligning manner by a reactive ion etching method. Then, after removing the polycrystalline silicon film other than the opening region deposited in the epitaxial growth step using the resist film 19 as a mask,
Then, the resist film 19 is also removed. This figure shows a stage before the resist film 19 buried in the opening region is removed.

After that, a thin silicon oxide film 12 to be the second insulating film is deposited according to the same steps as in Embodiment 1, and then the side wall of the opening contains impurities of one conductivity type as shown in FIG. Amorphous silicon 15 is formed.

Next, as shown in FIG. 18, the thin silicon oxide film 12 in the opening is removed with a hydrofluoric acid-based aqueous solution using the amorphous silicon 15 as a mask, and the base region 7 is formed by epitaxial growth. Was exposed, the emitter electrode 11 was formed on the exposed portion, and the desired bipolar transistor was formed.

According to this embodiment, since the intrinsic base region 7 is formed by the epitaxial growth method, the thin base layer 7 can be obtained and the device can operate at high speed. In addition, the intrinsic base region 7 is formed by the epitaxial growth method.
It is also possible to form with Si (1-x) Ge (x).

<Embodiment 6> FIGS. 19 to 23 are sectional views showing the state of the active region 4, which is the main part, in the order of manufacturing steps, similarly to the process drawing of Embodiment 1. However, in the present embodiment, although the structure is slightly different, SICOS (si
The technology of the fifth embodiment is applied to a transistor.

First, as shown in FIG. 19, the surface of the semiconductor substrate 16 on which the collector layer having one conductivity type is formed is oxidized to form a silicon oxide film 18. Next, on the silicon oxide film 18, a polycrystalline silicon 9 containing an impurity of opposite conductivity type which serves as a base electrode and a silicon oxide film 10 which serves as a first insulating film are sequentially laminated. Then, as shown in the figure, the opening 7a is formed in the region where the intrinsic base 7 is formed by selectively removing the silicon oxide film 10 and the polycrystalline silicon 9 by the reactive ion etching method using the photoresist film as a mask. And the silicon oxide film 18 is exposed.

Next, as shown in FIG. 20, the silicon oxide film 18 in the opening is removed by using a hydrofluoric acid-based aqueous solution, and the intrinsic base 7 is removed.
The region for forming the base is exposed, and an intrinsic base region 7 containing impurities of the opposite conductivity type is formed by the epitaxial growth method as shown in the figure.

In subsequent steps, as shown in FIGS. 21 to 23, elements are formed by the same steps as those in FIGS. 16 to 18 of the fifth embodiment. In the structure of this embodiment, the capacitance between the base and the collector can be reduced so that the speed of the device can be increased.

<Embodiment 7> FIGS. 24 to 27 are sectional views showing the state of the active region 4, which is a main part, in the order of manufacturing steps, as in the case of the embodiment 1. First, as shown in FIG. 24, a semiconductor substrate 16 on which a collector layer having one conductivity type is formed.
Polycrystalline silicon 9 containing impurities of opposite conductivity type, which will serve as a base electrode, is deposited on top. Then, a silicon oxide film 10 serving as a first insulating film is laminated on the polycrystalline silicon 9.

Then, as shown in FIG. 25, the silicon oxide film 10 and the polycrystalline silicon 9 are selectively removed by reactive ion etching using the photoresist film as a mask to form an intrinsic base 7. The opening 7a is formed in the area to be formed. Then, heat treatment is performed to form the outer base 17. Next, using the silicon oxide film 10 as a mask, the opposite conductivity type impurities are introduced into the opening by diffusion from a mixed gas of the opposite conductivity type impurities, and the opposite conductivity type impurities are activated by heat treatment as shown in the figure. To form the base region 7.

The subsequent steps are shown in FIG. 3 to FIG.
26. First, as shown in FIG. 26, a thin silicon oxide film 12 serving as a second insulating film is deposited in a short time by using the CVD method, and subsequently, one conductivity type impurity is deposited on the side wall of the opening. Amorphous silicon 15 containing is formed.

Next, as shown in FIG. 27, the thin silicon oxide film 12 at the opening is removed by using an aqueous solution of hydrofluoric acid with the amorphous silicon 15 as a mask to expose the base region 7. Subsequently, as shown in the drawing, a second amorphous silicon containing one conductivity type impurity is formed and heat-treated to simultaneously form the emitter region 8 and the polycrystalline silicon emitter electrode 11.

The desired bipolar transistor was formed by the above steps. After that, the base wiring 13 and the collector electrode 14 are formed according to the usual manufacturing process. Also in this embodiment, the diffusion of impurities of the opposite conductivity type in the base region 7 is reduced by lowering the temperature of the process, and the thin base layer 7 is formed, so that the speed of the device can be increased.

<Embodiment 8> FIG. 28 shows an emitter width of 0.
Example 1 for a bipolar transistor narrowed to 1 μm
FIG. 6 is a cross-sectional view of a main part when the emitter electrode forming technique of 1 is applied. In the conventional manufacturing method, the emitter 8
Since it is formed by the ion implantation method, it is difficult for impurities to diffuse in the peripheral portion of the opening (plug effect), and it is difficult to obtain a uniform impurity profile. In recent years, there is a tendency to reduce the size of the emitter for the purpose of high performance and high integration of the element, but the conventional manufacturing method causes a remarkable plug effect, which causes a reduction in the current gain and cutoff frequency and an increase in the emitter resistance. Higher element performance cannot be expected. However, according to the same manufacturing method as in Example 1, even if the emitter width was reduced to 0.1 μm, there was no plug effect, high performance, and an emitter resistance comparable to that of the conventional one was obtained.

Further, similar to the first embodiment, the reactive ion etching method is used to form the amorphous silicon 15 containing an impurity of one conductivity type on the side wall of the opening, but the second insulating film in the opening is formed. Silicon oxide film 12 and amorphous silicon 15
That is, since the selection ratio for reactive ion etching can be increased, the silicon oxide film 12 is not etched. That is, the silicon oxide film 12 plays an effective role as a stopper during dry etching of the amorphous silicon 15. After that, if the silicon oxide film 12 at the opening is removed with a hydrofluoric acid-based solution, a defect-free silicon surface can be obtained.

<Embodiment 9> FIG. 29 is a sectional view showing the main part of a bipolar transistor according to the final embodiment. The manufacturing method is basically the same as in Example 1, but
A characteristic feature is that as shown in the figure, the amorphous silicon 15 containing impurities of one conductivity type and the polycrystalline silicon emitter electrode 11 are included.
And a good conductor layer 20 such as a metal layer is formed between the and. Hereinafter, the above characteristic part will be described.

After the amorphous silicon 15 containing an impurity of one conductivity type is formed on the side wall of the opening, a good conductor layer 20 such as metal or a silicide layer is formed thereon. In this example, titanium nitride (TiN) was used for the good conductor layer 20. The good conductor layer is not limited to titanium nitride, and various metals, silicides, etc. can be selected and used. Then, as shown in FIG.
The amorphous silicon is formed and heated to form the emitter region 8 and the polycrystalline silicon emitter electrode 11 at the same time. This embodiment can further reduce the emitter resistance as compared with the first embodiment.

The present invention is not limited to the above embodiment, but can be modified in various ways. For example, if the impurity of one conductivity type is n-type and the impurity of opposite conductivity type is p-type, the bipolar transistor of any of the above embodiments is np.
It becomes an n-type semiconductor device, and the n-type and p
A pnp-type semiconductor device can be manufactured if all the molds are reversed. Furthermore, it goes without saying that the semiconductor substrate is not limited to the silicon semiconductor and can be similarly realized with a compound semiconductor.

[0064]

As described above, according to the present invention, the intended purpose can be achieved. That is, since the base layer can be thinned, the device can operate at high speed. Further, according to the present invention, the emitter resistance can be reduced to about 70% of the conventional value. Further, according to the present invention, it is possible to prevent the emitter electrode on the edge of the opening portion from being removed in the step of forming the contact hole and electrically short-circuiting between the emitter and the base.

[Brief description of drawings]

FIG. 1 is a sectional view of the essential part showing the manufacturing process of a bipolar transistor according to an embodiment (embodiment 1) of the present invention.

FIG. 2 is a sectional view of the same.

FIG. 3 is a sectional view of the same.

FIG. 4 is a sectional view of the same.

FIG. 5 is a sectional view of the same.

FIG. 6 is a cross-sectional view showing a manufacturing process of a conventional bipolar transistor.

FIG. 7 is a sectional view of the essential part showing the manufacturing process of another embodiment (Embodiment 2).

FIG. 8 is a cross-sectional view of an essential part showing a manufacturing process which is another different embodiment (third embodiment).

FIG. 9 is a sectional view of a key portion showing the manufacturing process according to another embodiment (Example 4) which is also different.

FIG. 10 is a sectional view of the same.

FIG. 11 is a sectional view of the same.

FIG. 12 is a sectional view of the same.

FIG. 13 is a sectional view of the same.

FIG. 14 is a main-portion cross-sectional view showing a manufacturing process which is another different embodiment (Fifth Embodiment).

FIG. 15 is a sectional view of the same.

FIG. 16 is a sectional view of the same.

FIG. 17 is a sectional view of the same.

FIG. 18 is a sectional view of the same.

FIG. 19 is a main-portion cross-sectional view showing the manufacturing process according to another different embodiment (Embodiment 6).

FIG. 20 is a sectional view of the same.

FIG. 21 is a sectional view of the same.

FIG. 22 is a sectional view of the same.

FIG. 23 is a sectional view of the same.

FIG. 24 is a fragmentary sectional view showing the manufacturing process of another embodiment (Embodiment 7) which is also different.

FIG. 25 is a sectional view of the same.

FIG. 26 is a sectional view of the same.

FIG. 27 is a sectional view of the same.

FIG. 28 is a sectional view of a key portion showing the manufacturing process according to another different embodiment (eighth embodiment).

FIG. 29 is a sectional view of a key portion showing the manufacturing process according to another embodiment (Example 9) which is also different.

[Explanation of symbols]

1 ... Silicon substrate having one conductivity type, 2 ... Epitaxial growth layer having reverse conductivity type, 3 ... Insulation isolation region,
4 ... Active region, 5 ... One conductivity type high concentration buried diffusion layer, 6 ... One conductivity type low concentration layer, 7 ... Base region having reverse conductivity type, 7a ... Opening portion, 8 ... One conductivity type Emitter region, 9 ... Polycrystalline silicon layer containing reverse conductivity type impurities at a high concentration, 10 ... First insulating film,
12 ... Second insulating film, 11 ... Emitter electrode,
DESCRIPTION OF SYMBOLS 13 ... Base wiring, 14 ... Collector electrode, 15 ... One conductivity type polycrystalline silicon layer formed from amorphous silicon, 16 ... Semiconductor substrate in which a collector layer having one conductivity type is formed, 17 ... Reverse conductivity type An external base region having: 18 ... Silicon oxide film, 19 ... Resist film, 20 ... Good conductor layer (silicide electrode).

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Akihiko Konno 2326 Imai, Ome-shi, Tokyo Hitachi, Ltd. Device Development Center

Claims (6)

[Claims] 1. Polycrystalline silicon containing impurities of opposite conductivity type to serve as a base electrode is deposited on a semiconductor substrate on which a collector layer having one conductivity type is formed, and then a first silicon is deposited on the polycrystalline silicon. A step of laminating an insulating film, a step of selectively removing the first insulating film and polycrystalline silicon using a mask made of a photoresist film to form an opening in a region where a base is formed, A step of forming a base region by introducing impurities of opposite conductivity type using the insulating film as a mask;
An amorphous film containing one conductivity type impurity, which is formed by depositing a second insulating film and then forming a gas mixed with one conductivity type impurity;
Alternatively, a step of forming polycrystalline silicon on the sidewall of the opening, a step of exposing the base region in the opening, and a step of using the first insulating film as a mask to introduce impurities of one conductivity type through the opening to form the emitter region And a step of forming a bipolar transistor. 2. Polycrystalline silicon containing impurities of opposite conductivity type to serve as a base electrode is deposited on a semiconductor substrate on which a collector layer having one conductivity type is formed, and then the first polysilicon is deposited on the polycrystalline silicon. A step of laminating an insulating film; a step of forming a shallow base region by thermally diffusing an impurity of opposite conductivity type in the semiconductor substrate using the polycrystalline silicon as an impurity source of opposite conductivity type; Selectively removing the first insulating film and the polycrystalline silicon using the mask to form an opening in a region where an emitter is to be formed, a second insulating film is deposited, and then one opening of one conductivity type is formed. Forming amorphous or polycrystalline silicon containing one conductivity type impurity formed from a gas mixed with impurities on the sidewall of the opening, exposing the base region in the opening, and through the opening One conductivity type La method for producing a transistor - Baipo comprising a step of forming an emitter region by introducing pure things. 3. Polycrystalline silicon containing impurities of opposite conductivity type to be a base electrode is deposited on a semiconductor substrate on which a collector layer having one conductivity type is formed, and then first polysilicon is deposited on the polycrystalline silicon. A step of laminating an insulating film, a step of selectively removing the first insulating film and polycrystalline silicon using a mask made of a photoresist film to form an opening in a region where a base is formed, A step of forming a base region containing impurities of opposite conductivity type by using an epitaxial growth method, a step of burying a photoresist film in the opening region in a self-aligned manner, and a step of depositing a part other than the opening region during the epitaxial growth step. Removing the second epitaxial growth layer using the photoresist film as a mask, removing the photoresist film, depositing a second insulating film, and then mixing impurities of one conductivity type. Forming amorphous or polycrystalline silicon containing an impurity of one conductivity type formed from the gas on the side wall of the opening, exposing the base region formed by the epitaxial growth method in the opening, and opening And a step of introducing an impurity of one conductivity type to form an emitter region. 4. Polycrystalline silicon containing an impurity of opposite conductivity type to be the base electrode, a first insulating film, a second insulating film,
4. The bipolar transistor according to claim 1, wherein any one of the film forming steps of the amorphous silicon containing one conductivity type impurity or the polycrystalline silicon and the emitter electrode 11 is a film forming step by CVD. Manufacturing method. 5. The first and second insulating films are made of silicon oxide films, and the total film thickness of the second insulating film and amorphous or polycrystalline silicon containing impurities of one conductivity type is formed. 5. The bipolar device according to claim 4, wherein the thickness is 0.1 to 0.3 μm.
Method of manufacturing a transistor. 6. The method of manufacturing a bipolar transistor according to claim 4, wherein the step of forming amorphous silicon containing one conductivity type impurity or polycrystalline silicon by a low pressure CVD method.