JPS59108325A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS59108325A
JPS59108325A JP21901582A JP21901582A JPS59108325A JP S59108325 A JPS59108325 A JP S59108325A JP 21901582 A JP21901582 A JP 21901582A JP 21901582 A JP21901582 A JP 21901582A JP S59108325 A JPS59108325 A JP S59108325A
Authority
JP
Japan
Prior art keywords
silicon
groove
etching
film
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21901582A
Inventor
Toshio Kurahashi
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP21901582A priority Critical patent/JPS59108325A/en
Publication of JPS59108325A publication Critical patent/JPS59108325A/en
Application status is Pending legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/763Polycrystalline semiconductor regions

Abstract

PURPOSE:To omit processes, and to remove stress due to the interposition of a silicon dioxide film by forming a groove reaching to a substrate, depositing one conduction type polycrystalline semiconductor layer in the groove and oxidizing the surface to form an insulating film. CONSTITUTION:A U-shaped groove 16 is formed through dry etching while using the double films of a silicon dioxide film 14 and a silicon nitride film 15 as a mask. The vertical etching groove penetrates an N type semiconductor layer 13 and an N<+> type semiconductor layer 12, and reaches to the P type semiconductor substrate 11. The P type polycrystalline silicon layer 17 containing B is laminated, the polycrystalline silicon layer 17 on the silicon nitride film 15 is removed, and an upper section in the U-shaped groove 16 is also removed slightly through etching to form a recessed section. The silicon dioxide film 18 is formed on the polycrstalline silicon layer 17 through thermal oxidation, the silicon nitride film 15 is removed through etching, and an element isolation region is completed.
JP21901582A 1982-12-13 1982-12-13 Manufacture of semiconductor device Pending JPS59108325A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21901582A JPS59108325A (en) 1982-12-13 1982-12-13 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21901582A JPS59108325A (en) 1982-12-13 1982-12-13 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS59108325A true JPS59108325A (en) 1984-06-22

Family

ID=16728913

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21901582A Pending JPS59108325A (en) 1982-12-13 1982-12-13 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS59108325A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4767722A (en) * 1986-03-24 1988-08-30 Siliconix Incorporated Method for making planar vertical channel DMOS structures
US4873203A (en) * 1987-07-27 1989-10-10 Hitachi, Ltd. Method for formation of insulation film on silicon buried in trench
US5034785A (en) * 1986-03-24 1991-07-23 Siliconix Incorporated Planar vertical channel DMOS structure
US5106777A (en) * 1989-09-27 1992-04-21 Texas Instruments Incorporated Trench isolation process with reduced topography
US5290396A (en) * 1991-06-06 1994-03-01 Lsi Logic Corporation Trench planarization techniques
US5312770A (en) * 1991-06-06 1994-05-17 Lsi Logic Corporation Techniques for forming isolation structures
US5354706A (en) * 1993-03-02 1994-10-11 Lsi Logic Corporation Formation of uniform dimension conductive lines on a semiconductor wafer

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4767722A (en) * 1986-03-24 1988-08-30 Siliconix Incorporated Method for making planar vertical channel DMOS structures
US5034785A (en) * 1986-03-24 1991-07-23 Siliconix Incorporated Planar vertical channel DMOS structure
US4873203A (en) * 1987-07-27 1989-10-10 Hitachi, Ltd. Method for formation of insulation film on silicon buried in trench
US5106777A (en) * 1989-09-27 1992-04-21 Texas Instruments Incorporated Trench isolation process with reduced topography
US5290396A (en) * 1991-06-06 1994-03-01 Lsi Logic Corporation Trench planarization techniques
US5312770A (en) * 1991-06-06 1994-05-17 Lsi Logic Corporation Techniques for forming isolation structures
US5354706A (en) * 1993-03-02 1994-10-11 Lsi Logic Corporation Formation of uniform dimension conductive lines on a semiconductor wafer

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