JPH02174139A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a crystal defect from being caused in a semiconductor substrate by a method wherein an opening width at the upper part of a groove, for element isolation use, formed in the semiconductor substrate is made wider as compared with the lower-part. CONSTITUTION:In a state that a side wall 28a has been formed on an inner wall of an opening part 27 in a mask layer 24 on a semiconductor substrate, the semiconductor substrate is etched through the opening part 27; a groove 29 for element isolation use is formed. After that, the side wall 28a is removed to make the opening part 27 wider; an etching operation is executed again through the opening part 27; an opening width at upper parts 29a of the groove 29 is made wide as compared with the lower-part side. When the upper parts of the groove are made wide in this manner, a stress by formation of an insulating film 33 is dispersed in a depth direction and a transverse direction when, after an insulating film 30 has been formed on side walls of the groove 29, the groove except the upper parts 29a is filled with polycrystalline silicon 32, the upper parts 29a of the groove 29 are filled and the insulating film 33 is formed on the surface. Thereby, it is possible to prevent a crystal defect from being caused in the semiconductor substrate.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and in detail, M
The present invention relates to a method for forming element isolation portions in O3 LSIs and highly integrated bipolar LSIs using the single filling method.

(Prior Art) In recent years, in semiconductor memory devices, miniaturization of memory elements (memory cells) has been promoted in response to demands for increased storage capacity, and higher integration of elements has been achieved. Currently, it is necessary to further reduce the isolation width of elements in order to improve the degree of integration.
This has become an important issue.

Conventional element isolation uses pn junction isolation or selective oxidation isolation in bipolar LSIs (on the other hand, in MO
3LS+ mainly uses selective oxidation separation (Localoxi
dation of 5ilieonH below LOCO3
) has been widely used.

However, in separation by the LOCO8 method, bird's beaks occur and it is difficult to obtain a separation width of 0.5 μm or less.

Therefore, there is a strong demand for a new element isolation technology to replace this. Among the methods that have been proposed so far, there are selective epitaxial isolation, trench element isolation, dielectric isolation, etc., and here, as an example, trench element isolation technology will be explained.

FIG. 3 (al to fdl are from the document “LSI Handbook.

This figure shows an example of device isolation using trench photolithography (hereinafter referred to as trench device isolation), which is shown in ``The Institute of Electronics and Communication Engineers, Ohmsha, p. 392''. This method will be explained step by step below.

In FIG. 3 (al), 1 is a P-type silicon (Si) substrate, and after forming n+ buried 1'iJ2 on the surface side,
Epitaxial NIJ3 is deposited. Below, silicon substrate 1. n+ buried layer 2. The portion of the n epitaxial layer 3 is referred to as a silicon substrate. A pad silicon oxide film (hereinafter referred to as 5102 film) 4 and a silicon nitride film (hereinafter referred to as Si, N4 film) 5 are sequentially formed on this silicon substrate. Next, openings 6 for forming element isolation grooves are formed in these Si, N4 films 5 and 5102 films 4 by ordinary photolithography. Then, by etching the silicon substrate by reactive ion etching (RIE) through the opening 6 using the remaining Si, N4 film 5 as a mask, a deep groove 7 penetrating the n+ buried layer 2 is formed in the silicon substrate. .

Next, a SiO2 film 8 is formed on the inner wall of the groove 7 by thermal oxidation as shown in FIG. A layer 9 is formed. After that, polycrystalline silicon 10 is deposited thickly over the entire surface, and grooves 7 are formed in the polycrystalline silicon 1.
Fill with 0.

Next, the polycrystalline silicon 10 is left only in the groove 7 as shown in FIG. 3 (cl) by an etch pack.

Finally, using the Si3N film 5 as a mask, a cap oxide film 11 is formed on the surface of the polycrystalline silicon 10 by thermal oxidation as shown in FIG. 3fdl.

(Problems to be Solved by the Invention) However, in the conventional trench element isolation formation method as described above, there is a problem that The problem is that stress is generated. In particular, the 35th Applied Physics Association Lecture Proceedings @31 a-V-10,
As pointed out on page 692, cap oxide film 1
The stress between 1 and the polycrystalline silicon 10 is significant, and a bird's beak is generated in the area shown by the dotted circle in FIG. A large number of leakage currents occurred, and the resulting leakage current made it impossible to obtain sufficient device characteristics.

This invention alleviates the local stress generated during the formation of an insulating film on the surface of buried polycrystalline silicon, and as a result, suppresses the occurrence of crystal defects in the semiconductor substrate, making it possible to form a trench element with excellent performance. The purpose is to provide a separation formation method.

(Means for Solving the Problems) In the trench element isolation forming method, the opening width of the upper part of the element isolation groove formed in the semiconductor substrate is
It is made wider than the lower part. especially,
In this invention, a sidewall is formed on the inner wall of an opening in a mask layer on a semiconductor substrate, and the semiconductor substrate is etched through the opening to form a trench for element isolation, and then the sidewall is removed. By widening the opening and etching it through the opening again,
The opening width of the upper part of the groove is made wider than that of the lower part.

(Function) When the upper part of the groove is widened as described above, after forming an insulating film on the inner wall of the groove, the inside of the groove is filled with polycrystalline silicon except for the upper part, and the polycrystalline silicon is filled with polycrystalline silicon. on the surface of
When the mu film is formed by filling the upper part of the trench, the stress caused by the formation of the insulating film is dispersed in the depth direction and the lateral direction, as shown in FIG. In other words, stress concentration is alleviated, thereby reducing the occurrence of crystal defects in the semiconductor substrate.

(Embodiment) An embodiment of the present invention will be described below with reference to FIGS.

In FIG. 1(a), 21 is P-type silicon (100)
The substrate has a resistivity in the range of 1 to 20 Ω·cm.

Phosphorus (P) or arsenic (As) is added to the surface side of this P-type silicon (100) substrate 21 by a normal diffusion method.
Diffused to the extent of X 10” atoms/cc, n+ buried layer 22
form. Furthermore, an n layer 23 is formed on the n+ buried layer 22 by epitaxial growth. This n-layer 2
In forming No. 3, a commonly used growth method was used. That is, in this example, -diluted 5iH2Cj2 gas and PH3 gas or -diluted SiH4 gas and PH3 gas are used during growth, and the humidity is 1000 to 1000.
Growth was performed in the range of 1200°C. In addition, this n layer 23
is the thickness of the range usually used as i element isolation,
- For example, the thickness may be about 1 to 5 μm. This n
- layer 23 and n″″ buried layer 22 and P-type silicon (10
0) The substrate 21 portion is called the bottom silicon substrate.

Next, as shown in FIG. 1 Tbl, a silicon oxide film (hereinafter referred to as SiO2 film) 24 is deposited on the silicon substrate.
Specifically, it is grown on the n-layer 23. This 5in2
The film 24 is formed by a normal thermal oxidation method.

That is, in this example, an electric furnace was used and dry oxygen (02
) Oxidation is carried out at 1000°C in an atmosphere, and the
It grew to a depth of 00 people. Next, a resist 25 is applied onto the Sio2 film 24 using a spin code, and is deposited to a thickness of about 1 μm.

Thereafter, the resist 25 is patterned by photolithography as shown in FIG. 1 (C1).

Here, the width of the resist removed portion 26 is set to a width that allows a desired trench width, for example, a dimension of 0.5 to 1.5 μm, and the various conditions of photolithography are set so as to achieve this width.

Next, using the patterned resist 25 as a mask, reactive ion etching (RIE) is performed to remove SiO.
2 film 24 is etched, and the 5IO2 film 24 is etched as shown in FIG.
Form an opening 27 for groove formation as shown in dl.

Next, after removing the resist 25, a silicon nitride film (hereinafter referred to as Si, N film) 28 is deposited on the entire surface of the 5102 film 24 including the opening 27, as shown in FIG.
It is deposited by method D. This Si, N4 film 28, 51
The thickness may be sufficient as long as it can completely fill the opening 27 of the 02 film 24.

Thereafter, by an etch-back method, as shown in FIG. 1 ffl, Si,
The N4 film 28 is left as a sidewall 28a.

Next, using the 5102 film 24 and the sidewall 28a as a mask, the silicon substrate is etched into a groove shape by RIE through the opening 27 to form a groove 29 for element isolation in the silicon substrate as shown in FIG. Here, a
The depth 29 is the depth that penetrates the buried layer 22 by n.

The depth is usually 3-5 μm.

Next, as shown in FIG.
a is removed by etching.

Thereafter, through the opening 27 expanded by the removal of the sidewall, the R
A part of the silicon substrate, specifically a part of nN23, is etched by IE as shown in FIG. This expanded portion is called a pocket region 29a.

Thereafter, the S i O 2 film 24 used as a mask is removed as shown in FIG. 1 (jl) to expose the surface of the silicon substrate.

Next, the corners of the grooves are wet-etched to form the 19th (
Round as shown in kl.

After that, the inner wall of the groove 29 and the surface R of the silicon substrate:
, FIG. 1 (shown in jl)
Form at a length of 0.30 to 500 to 2,500. This 5Io
The formation of the two films at 3° may be performed using either thermal oxidation or CVD. Subsequently, B+ is ion-implanted to form a channel cut layer 31 in the silicon base portion at the bottom of the groove 29.

Next, as shown in FIG. 1 (-), polycrystalline silicon 32 is deposited all over the silicon substrate, and
to completely fill the groove 29.

The thickness of this polycrystalline silicon 32 may be 2000 to 5000 degrees.

Next, the polycrystalline silicon 32 is etched by an etch-pack method so that the polycrystalline silicon 32 is left only in the portions other than the upper portion of the groove 29, as shown in FIG. 1 (n layer).

Subsequently, a cap oxide film 33 is formed on the entire surface of the silicon substrate by using a conventional CVD method so as to fill the upper part of the trench 29. Finally, the cap oxide film 33 is etched by an etch-back method, and as shown in FIG.
Only the upper part of the groove 29 is filled in and remains on the surface of the groove 29. With the above steps, the trench element isolation section is completed.

In the above method, the upper part of the groove 29 has a pocket region 2
It forms 9m. Therefore, the stress generated by forming the cap oxide film 33 on the surface of the buried polycrystalline silicon 32 by filling the upper part of the groove 29 is dispersed in the depth direction and the lateral direction as shown in FIG. That is,
Stress concentration will be alleviated9, and thus the occurrence of crystal defects in the silicon substrate will be reduced. Therefore, there is no leakage current, and it is possible to form a high-performance element.

In the above embodiment, when forming 1J29 on a silicon substrate, a Si film is used as the film 24 which is the main part of the mask, or a Si film is used as the side wall 28a which is a part of the mask.
, an N4 film was used, but the materials may be replaced.

(Effects of the Invention) As described above in detail, according to the present invention, the open p width of the upper part of the element isolation groove is widened to provide a pocket region, so that the surface of the buried polycrystalline silicon is By filling the upper portion of the trench and forming an insulating film, the stress generated can be dispersed in the depth direction and the lateral direction. That is, it is capable of alleviating stress concentration, thereby reducing the occurrence of crystal defects in the semiconductor substrate, suppressing the occurrence of leakage current, and making it possible to form high-performance elements.

[Brief explanation of the drawing]

FIG. 1 is a process sectional view showing an embodiment of the semiconductor device manufacturing method of the present invention, FIG. 2 is an enlarged sectional view of the upper part of the trench in the above embodiment, and FIG. 3 is a conventional trench element isolation forming method. FIG. 21...P-type silicon (100) substrate, 22...n buried layer, 23...n layer, 24...silicon oxide film (S
in, membrane), 27...opening, 28a...side wall, 29...groove, 29a...pocket area, 3°...
・5IO2 film, 32... polycrystalline silicon, 33... cap oxide film. Section 1 of process cross-sectional diagram of one embodiment of the present invention

Claims (1)

[Claims] (a) A step of forming a mask layer on a semiconductor substrate, forming an opening in the mask layer, and further forming a sidewall on the inner wall of the opening; (b) a step of forming the sidewall. and etching the semiconductor substrate through the opening using the remaining mask layer as a mask to form a groove for element isolation in the semiconductor substrate; (c) After that, after removing the sidewall, the remaining mask layer is used as a mask. etching the semiconductor substrate through the opening expanded by the sidewall removal;
(d) After that, after forming an insulating film on the inner wall of the groove, filling the inside of the groove with polycrystalline silicon except for the upper part; (e) A method for manufacturing a semiconductor device comprising the step of: thereafter filling the upper part of the trench to form an insulating film on the surface of the polycrystalline silicon.