JPS6324672A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the collector series resistance while attaining high degree of integration of elements by a method wherein an insulating film is formed on a part of N layer on a P type substrate; P layers are laminated; grooves reaching the insulating film are made; sides of grooves are covered with the insulating film; windows are made in the bottom of grooves to fill the grooves with N type poli Si. CONSTITUTION:An N<+>layer 2 is buried in a P type Si substrate 1; an Si3N4 film 3 is partly provided; and an N epitaxial layer 4, an Si02 film 5 and another Si3N4 film 6 are laminated. An isolating groove B, a collector leading out groove A are made in specified positions by anisotropical dry etching process. When etched meeting the requirement for reaching the substrate 1, the film 3 becomes a stopper in the groove A, also on the sides and bottom of groove B by thermooxidation. The Si3N4 films 3, 6 on the bottom and surface of groove A are removed to fill the grooves A, B with N<+> polySi 8, 8'. The SiO2 film 5 is removed to be covered with a thermooxide film 9 and then a base layer 10, an emitter layer 11 and electrodes 12 are provided. In such a constitution, the collector series resistance can be reduced while preventing the lateral diffu sion of impurity from occuring to cut down the element space.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly relates to a method for manufacturing a semiconductor device having a connection region from the buried layer of the collector of an Ibora transistor to the electrode. .

[Conventional technology]

Conventionally, in order to connect the buried layer of the collector of a bipolar transistor and an electrode, it is not only necessary to simply form an electrode on the surface of the epitaxial layer in the collector region, but also to connect the buried layer of the collector of a bipolar transistor with the electrode from the surface of the epitaxial layer in order to reduce the series resistance of the collector. It is common to connect to the buried layer by diffusing impurities of the same conductivity type as the highly doped epitaxial layer.

FIG. 2 is a cross-sectional view of an example of a conventional semiconductor device.

According to the conventional semiconductor device manufacturing method, in this example, an n+ type buried layer 2' is provided on a p type silicon substrate 1, and an n type layer is formed by epitaxial growth on the silicon substrate 1 and the buried layer 2'. A structure in which an impurity layer 4' is provided, and an n+ type diffusion region 13 is provided in the lead-out portion connected to the collector electrode 14 extending from the opening of the oxide film 9' on the surface of the impurity layer 4' to the buried layer 2'. doing.

[Problem that the invention seeks to solve]

According to the conventional semiconductor device manufacturing method described above, in order to lower the resistance of the lead-out portion that connects the buried layer and the electrode, impurity diffusion is performed at a high concentration from the surface of the epitaxial layer, and the diffusion region of the lead-out portion is It is necessary to lower the resistance of the diffusion region and to allow the diffusion region to reach the buried layer, but if this is done, the lateral self-centering of the diffusion region becomes large.
In particular, when forming bipolar transistors, the heat treatment required to form the base and emitter regions, which is usually carried out in the post-process, is required. The area must be kept sufficiently away from the collector lead-out portion, which increases the device area6. Therefore, with conventional methods, it is difficult to simultaneously reduce the series resistance of the collector and increase the density of the device. There is a drawback.

[Means for solving problems]

The method for manufacturing a semiconductor device of the present invention includes a step of forming a buried layer of an opposite conductivity type on a semiconductor substrate of a -conductivity type, and selectively forming a first insulating film on a part of the buried layer. The process of
forming a semiconductor layer of an opposite conductivity type on the semiconductor substrate, the surface of which is provided with the buried layer and the first insulating film;
a step of removing the semiconductor layer above the first insulating film to form a trench from the surface of the semiconductor layer to the first insulating film; and a step of forming a second insulating film on the side surface of the trench. ,
The method includes the steps of removing a portion of the first insulating film exposed at the bottom of the trench, and filling the trench with polycrystalline silicon containing impurities of an opposite conductivity type.

〔Example〕

Next, an embodiment of the present invention will be described with reference to the drawings.

FIGS. 1(a) to 1(d) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining one embodiment of the present invention.

In this example, as shown in FIG. 1(a), first, an n+ type buried layer 2 is formed on a p type silicon substrate 1, and then a silicon nitride film 3 is deposited on the buried layer 2. The silicon nitride layer is removed from areas other than those forming the lead-out portion of the collector. Subsequently, an n-type silicon impurity layer 4 is grown, and a silicon oxide film 5 and nitride film 115j 6 are formed. Not here! When the material layer 4 is formed by epitaxial growth, polycrystalline silicon is usually deposited on top of the nitride film 3.

Next, as shown in FIG. 1(b), a photolithography process and anisotropic dry etching are used to etch the nitride film 6. Oxide film 5. Impurity layer 4 and silicon substrate 1 are etched to form trenches A and B. Here, the channel B is a channel for isolation between elements, and the channel A is a channel for drawing out the collector.

Furthermore, in the anisotropic dry etching for etching the impurity layer 4 and the silicon substrate 1, it is sufficient to carry out the etching under conditions such that the etching reaches the silicon substrate 1. stops. Further, after the scratches are formed, thermal oxidation is performed to form oxide films 7 and 7' on the curved surface of fiA and the side and bottom surfaces of groove B.

Next, as shown in FIG. 1 (c>), the nitride film 3 exposed at the bottom of the ?'?4A and the silicon nitride film 6 on the surface are removed to contain n+ type impurities in the trenches A and B. After filling polycrystalline silicon 8, 8', oxidation [5] on the surface of impurity layer 4 is removed, and thermal oxidation is further performed to form oxide IB!9 on the surface of impurity layer 4 and polycrystalline silicon 8, 8'. .

Next, as shown in FIG. 1(d), after forming a base region 10 and an emitter region 11 and opening contact windows for the base, emitter, and collector in the oxide film 9, the base region 10 and the emitter region 11 are formed.
Emitter and collector electrodes 12b, 12e and 12c
A bipolar) transistor is completed.

By the above method, it is easy to diffuse n-type impurities into the polycrystalline silicon 8, and not only can the series resistance of the collector be set low, but also because there is an oxide film 7 on the side surface of the mA. Since impurities do not diffuse laterally, the device area can be reduced.

Also, for isolation between elements? Since the groove 74B and the groove A of the collector pull-out part can be formed at the same time, the process is shortened.

〔Effect of the invention〕

As explained above, the present invention has the advantage that by making the polycrystalline silicon filled in the groove low in resistance, a collector lead-out portion with reduced series resistance of the collector can be formed, and the device area can be reduced. There is. Also, the drawer portion of this collector and the amount of elements i! ! Since 71I can be formed in the same process, there is also the effect that the manufacturing process can be shortened.

[Brief explanation of the drawing]

FIGS. 1A to 1D are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention, and FIG. 2 is a cross-sectional view of an example of a conventional semiconductor device. 1... Silicon substrate, 2.2'... Buried layer, 3...
・Nitride film, 4.4'... impurity layer, 5... oxide film,
6...Nitride film, 7.7'...Oxide film, 8.8'...
・Polycrystalline silicon, 9.9'...Oxide film, 10...
Base region, 11... Emitter region, 12b, 12c
, 12e - electrode, 13... diffusion region, 14... electrode, A, B... groove. Agent Patent Attorney Kusaya Uchihara 1 ■ Second Flash

Claims (1)

[Claims] a step of forming a buried layer of an opposite conductivity type on a semiconductor substrate of one conductivity type; a step of selectively forming a first insulating film on a portion of the buried layer; a step of forming a semiconductor layer of an opposite conductivity type on the semiconductor substrate having a first insulating film on its surface; a step of forming a groove reaching the first insulating film, a step of forming a second insulating film on the side surface of the trench, and a step of removing the portion of the first insulating film exposed at the bottom of the trench; A method for manufacturing a semiconductor device, comprising the step of filling the groove with polycrystalline silicon containing impurities of an opposite conductivity type.