JPH05129426A - Element isolation method of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain an element isolation method of a semiconductor device wherein fine isolation regions cad be obtained by low temperature treatment, and transistor characteristics of BVCBO, BVCEO, etc., can be improved. CONSTITUTION:An N-type epitaxial layer 43 is formed on a P-type semiconductor substrate 41. An oxide film 44 and a nitride film 45 are formed are after the other on the upper surface of the layer 43. A trench layer 46a is formed by etching. A side wall 47a of an oxide film is formed on the inner wall surface of the trench layer 46a. A doped CVD film like a BSG film 48 containing baron is buried in the trench.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an element isolation method for a semiconductor device which enables fine isolation and obtains a high degree of integration.

[0002]

2. Description of the Related Art FIG. 3 is a process sectional view of a prior stage of an element isolation method for a conventional semiconductor device, and FIG. 4 is a process sectional view of a subsequent stage thereof, which is an isolation method by impurity diffusion. First, as shown in FIG. 3A, a buried N ⁺ diffusion layer 2 is provided on a P-type semiconductor substrate 1 to reduce a bipolar collector resistance, and then an impurity P ⁺ diffusion layer 10 for isolation is formed. After that, the epitaxial layer 3 is formed. At this time, the N ⁺ buried layer 2 and the P ⁺ diffusion layer 10 are auto-doped and the layers spread upward.

Next, in order to facilitate the separation of the N type epitaxial layer 3, as shown in FIG. 3B, a diffusion layer 10a is provided from above. At this time, the insulating film 11 formed on the epitaxial layer 3 is used to diffuse and form the impurities. Next, as shown in FIG. 3C, drive-in is performed by a known diffusion technique to remove the P ⁺ diffusion layer 10,
The diffusion layer 10a is joined and the isolation layer 10b is formed to complete the separation.

Next, the subsequent steps shown in FIGS. 4 (a) to 4 (c) are carried out to form, for example, a transistor and the like. At this point, as shown in FIG. ^{+ The} buried layer 2 has a remarkable upward diffusion, and the isolation layer 10
The lateral diffusion of b is remarkable.

Next, the collector layer 2a is formed through known photolithography / etching / diffusion steps. This reduces the collector resistance and diffuses until it contacts the N ⁺ diffusion layer 2.

Next, as shown in FIG. 4B, a base layer 12 is similarly formed, and the base layer 12 is formed in the base layer 12 as shown in FIG.
As shown in (c), the emitter layer 13 is formed. In this case, there is an emitter pushing effect, and the push layer 13a is naturally formed.

5 (a) to 5 (d) are sectional views showing the steps of another conventional element isolation method for a semiconductor device.
This is an element isolation method using an insulating film isolation method. First, FIG.
As shown in (a), a buried N ⁺ collector layer 22 is provided in a P type semiconductor substrate 21, and a P ⁺ pre-isolation layer 30 is provided.
And the N-type single crystal layer 23 is formed by a known epitaxial technique.
To form.

Next, as shown in FIG. 5B, the oxide film 2
4. The nitride film 25 is sequentially formed on the N-type single crystal layer 23, and the trench layer 26a is obtained through the known photolithography / etching technique (including the trench etching technique).

Next, as shown in FIG. 5 (c), a thick oxide film is formed in a high pressure oxidation furnace to fill the inside of the trench layer 26a. In this case, the film thickness of the nitride film 25 serves as a stopper. The oxide film 25a is thinly formed.

Next, as shown in FIG. 5D, in order to bond the P ⁺ pre-isolation layer 30a and the oxide film 26b, annealing is performed by a known diffusion technique to form an isolation.

[0011]

However, even with the two conventional separation methods described above, the upward diffusion of the N ⁺ diffusion layer 3 by the impurity separation method shown in FIGS. 3 and 4, and the diffusion method shown in FIG. In addition, there is N ⁺ upward diffusion in the separation method of the lateral diffusion insulating film of the P ⁺ isolation layers 30 and 30a, lateral oxidation due to the necessity of a thick oxide film, and a transistor or the like formed later, for example, BV _{Since the} breakdown voltage of _CBO (collector-base breakdown voltage) and BV _CEO (collector-emitter breakdown voltage) cannot be obtained, it is necessary to secure a thick epitaxial layer and a margin for the isolation region, so that fine element isolation cannot be performed. ..

In the present invention, among the problems of the above-mentioned prior art, the upward diffusion of the N ⁺ diffusion layer by the isolation method by impurity diffusion and the lateral direction of the P ⁺ isolation layer by the element isolation method by the insulation isolation method. Since it is necessary to make room for the epitaxial layer and isolation region due to the diffusion of
An object of the present invention is to provide element isolation of a semiconductor device, which solves the problem that fine element isolation cannot be performed.

[0013]

In order to solve the above problems, the present invention provides an element isolation method for a semiconductor device,
A step of forming a trench layer in an epitaxial layer on a semiconductor substrate, forming a sidewall of an oxide film on the inner surface of the trench layer, and then burying a doped CVD film such as a silica gate glass film containing boron in the sidewall. It was done.

[0014]

According to the present invention, since the above steps are introduced in the element isolation method of the semiconductor device, the lateral diffusion of boron is prevented by the sidewalls in the trench layer, and the junction with the semiconductor substrate is achieved. It becomes possible and therefore the above problems can be eliminated.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the element isolation method for a semiconductor device according to the present invention will be described below with reference to the drawings. 1 (a)-
FIG. 1D is a process sectional view of the first stage of the embodiment,
2A to 2C are process cross-sectional views of the subsequent stage.

First, as shown in FIG. 1A, an N ⁺ buried layer 42 is formed on a P-type semiconductor substrate 41 in the preceding steps of FIGS. 1A to 1D, and then, as shown in FIG. Then, the N-type epitaxial layer 43 is formed. This N-type epitaxial layer 43
Can be formed thinner than the conventional one, and the floating of the N ⁺ buried layer 42 can be reduced accordingly.

Next, as shown in FIG. 1B, the oxide film 4 is formed.
4 and a nitride film 45 are sequentially formed on the N-type epitaxial layer 43, and an opening 46 is formed in a portion requiring separation by a known photolithography / etching technique. Next, as shown in FIG. 1C, the nitride film 45 and the oxide film 44 are etched by a trench dry silicon etcher until the P-type semiconductor substrate 41 is reached to form a trench layer 46a. (In this case, even if the etching does not reach the semiconductor substrate 41, there is no problem according to the present invention.) Next, as shown in FIG. 1D, the oxide film 47 is thinly formed by the atmospheric pressure CVD method. To do. Naturally, the thin oxide film 47 is also formed on the inner wall of the trench layer 46a, but the formed shape is not so good (however, there is no problem with the present invention).

Next, the subsequent steps shown in FIGS. 2A to 2C are performed, and the thin oxide film 4 is formed by known dry etching.
When the entire surface of 7 is etched, the oxide film 47 remains on the inner wall of the trench layer 46a and becomes the sidewall 47a.
Next, as shown in FIG. 2B, the trench layer 46 is buried, but a doped CVD process such as a silica gate glass (hereinafter referred to as BSG) film 48 by a normal pressure CVD method containing boron is performed. It is preferable to fill it, and it is formed thick until the inside of the trench is filled.

Next, as shown in FIG. 2C, a buried BSG layer 48a is formed again by full-surface etchback. The heat treatment in the separation process up to this point is at most 40 at atmospheric pressure CVD.
The temperature is about 0 ° C., and the N ⁺ buried layer 42 has no upward diffusion.

Further, the sidewall 47 made of an oxide film is used.
Since there is a, there is no lateral diffusion of impurities from the BSG film 48. However, it is necessary to form the P ⁺ layer 49 shown in FIG. 2C.
The annealing process is not necessary since the diffusion is performed at the same time by the heat treatment for forming the emitter (this description is omitted).

To give specific numerical examples of each part in the present invention, the thickness of the N-type epitaxial layer 43 is 1 μm, 0.
5 Ωcm, N ⁺ upward diffusion 0.1 μ, BSG film 48 13
w +%, a few kΩ / □ in the P ⁺ layer 49, a base layer (not shown) of 0.3μ, and an emitter layer (not shown) of 0.2μ, and even if there is an emitter pushing effect, BV _CBO ≧
20V, BV _CEO ≧ 10V, HFE (grounded emitter direct current amplification factor) were realized. The separation area is 0.5μ
It can be formed with a thickness of up to 1.0 μ, and a significantly fine pattern can be formed.

[0022]

As described above in detail, according to the present invention, the trench layer is formed in the epitaxial layer, the side wall of the oxide film is formed on the inner wall surface of the trench layer, and then the boron of the BSG film is removed. as while preventing lateral diffusion bonding between the semiconductor substrate becomes possible, since to form the isolation region, can be realized in a fine isolation region is obtained, further everything isolation region forming a low temperature process N ⁺ The floating of the buried layer is reduced, a thin epitaxial layer is possible, and improvement of transistor characteristics such as BV _CBO and BV _CEO can be expected.

[Brief description of drawings]

FIG. 1 is a process sectional view of a preceding stage for explaining an embodiment of an element isolation method for a semiconductor device of the present invention.

FIG. 2 is a process sectional view of the latter stage of the embodiment.

FIG. 3 is a process cross-sectional view of the former stage of a conventional element isolation method for a semiconductor device.

FIG. 4 is a process cross-sectional view of a latter stage of the conventional semiconductor device element isolation method.

FIG. 5 is a process cross-sectional view of another conventional element isolation method for a semiconductor device.

[Explanation of symbols]

41 Semiconductor Substrate 42 N ⁺ Buried Layer 43 N-Type Epitaxial Layer 44 Oxide Film 45 Nitride Film 46 Opening 46a Trench Layer 47 Thin Oxide Film 47a Sidewall 48 BSG Film 48a Buried BSG Layer 49 P ⁺ Layer

Claims (1)

[Claims] 1. A step of forming an epitaxial layer on a semiconductor substrate and sequentially forming an oxide film and a nitride film on the epitaxial layer, and etching the nitride film, the oxide film, and the epitaxial layer to form a trench layer. Then, a step of forming a thin oxide film on the front surface, a step of forming a side wall of the oxide film on the inner wall surface of the trench layer by full-scale etch back, and a step of doping silica gate glass or the like in the trench layer A method for element isolation of a semiconductor device, which comprises a step of burying a CVD film.