CN113782589A - Process method of groove type power MOSFET device - Google Patents
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- CN113782589A CN113782589A CN202111011366.5A CN202111011366A CN113782589A CN 113782589 A CN113782589 A CN 113782589A CN 202111011366 A CN202111011366 A CN 202111011366A CN 113782589 A CN113782589 A CN 113782589A
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- 238000000034 method Methods 0.000 title claims abstract description 71
- 230000008569 process Effects 0.000 title claims abstract description 62
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 239000000969 carrier Substances 0.000 claims abstract description 9
- 238000004519 manufacturing process Methods 0.000 claims abstract description 8
- 239000004065 semiconductor Substances 0.000 claims abstract description 8
- 230000015556 catabolic process Effects 0.000 claims abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 2
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 claims description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 2
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 2
- 230000006872 improvement Effects 0.000 description 5
- 238000012360 testing method Methods 0.000 description 5
- 230000003068 static effect Effects 0.000 description 3
- 238000013100 final test Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- TVZRAEYQIKYCPH-UHFFFAOYSA-N 3-(trimethylsilyl)propane-1-sulfonic acid Chemical compound C[Si](C)(C)CCCS(O)(=O)=O TVZRAEYQIKYCPH-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 239000013256 coordination polymer Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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Abstract
The invention discloses a process method of a trench type power MOSFET device, which is formed in an epitaxial layer on a semiconductor substrate, wherein when a process for forming a sacrificial silicon oxide layer is carried out on the epitaxial layer, a low-temperature process temperature not higher than 1050 ℃ is adopted for manufacturing the sacrificial oxide layer, and by reducing the process temperature of the process for forming the sacrificial oxide layer, when the sacrificial oxide layer with the same thickness as that of the traditional process is formed, the low-temperature process reduces the quantity of carriers in the substrate which are reversely diffused into the epitaxial layer, the effective thickness of the epitaxial layer is increased, and the breakdown voltage is improved.
Description
Technical Field
The invention relates to the field of semiconductor devices and manufacturing, in particular to a trench type power MOSFET device and a process method of the trench type power MOSFET device.
Background
Power MOSFETs, one of the main bodies of power semiconductor devices, are widely used in the fields of communications, computers, automobiles, and consumer electronics, and are important components in discrete devices and smart power integrated circuits. With the increasing demand of consumer electronics, the demand of power MOSFETs is increasing, for example, in disk drives, automotive electronics, and power devices. The Trench type M0SFET (Trench M0S) has a low switching loss and a high switching speed due to its high integration level, low on-resistance, low gate-drain charge density and large current capacity, and is widely used in the low-voltage power field.
As shown in fig. 1, a trench is formed in a silicon substrate or an epitaxial layer 1 of a conventional trench type power MOSFET device, and a gate-drain capacitance of a conventional device with a thick bottom dielectric layer is sharply reduced due to the existence of the thick dielectric layer between gates and drains. In addition, in the off state (the gate source is connected with 0 potential), due to the thick dielectric layer at the bottom, lateral depletion is generated, and therefore the breakdown voltage BV is improved.
An ideal power MOSFET device should have ideal static and dynamic characteristics to withstand high voltages in the off state; in the conducting state, the high-current high-voltage LED has high current and low voltage drop; when the switch is switched, the switch has short on-off time, can bear high di/dt and dv/dt, and has full control function.
The static electrical parameters appearing in the data reports of various WAT (wafer test), CP (probe test) and FT (final test) are the main basis for judging whether the device is qualified, and the common static electrical parameters comprise BV (BV)DSS,IDSS,IGSS,RDSON,VGSAnd the like.
BVDSSThe maximum drain-source voltage that the power device can bear when working normally is defined as the voltage value when the drain current is equal to 250uA under the condition that the grid electrode and the source electrode are grounded, and the maximum drain-source voltage is an important index for judging the states of the channel between the drain electrode and the source electrode of the device and the PN junction of the intrinsic diode.
For trench MOS devices BV is affectedDSSMainly has epitaxial layer resistivity and thickness, trench depth, contact depth, etc., and the high temperature process of the furnace tube during the process will affect the epitaxial layer thickness (epitaxial layer thickness T in FIG. 1) and thus BVDSSCausing an impact.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a process method of a trench type power MOSFET device.
In order to solve the above problems, the process method for the trench type power MOSFET device according to the present invention is formed in an epitaxial layer on a semiconductor substrate, and when a process for forming a sacrificial silicon oxide layer is performed on the epitaxial layer, a low temperature process temperature not higher than 1050 ℃ is used to form the sacrificial oxide layer.
In a further improvement, the semiconductor substrate comprises a silicon substrate, a silicon germanium substrate, a gallium arsenide substrate, an indium phosphide substrate and a silicon carbide substrate.
In a further improvement, the temperature of the sacrificial oxide layer forming process is 950 ℃.
In a further improvement, the thickness of the sacrificial oxide layer formed by the low-temperature process temperature is consistent with that of the high-temperature process.
The further improvement is that the low temperature process reduces the number of carriers in the substrate extending into the epitaxial layer, increases the effective thickness of the epitaxial layer and thereby increases the breakdown voltage BVDSS。
According to the trench type power MOSFET device, by reducing the process temperature of the forming process of the sacrificial oxide layer, when the sacrificial oxide layer with the same thickness as that of the traditional process is formed, the quantity of current carriers in the substrate which are reversely diffused into the epitaxial layer is reduced through the low-temperature process, the effective thickness of the epitaxial layer is increased, and the breakdown voltage is improved.
Drawings
Fig. 1 is a schematic cross-sectional view of a trench power MOSFET.
Fig. 2 is a schematic diagram of the original thickness of the epitaxial layer, the effective thickness of the epitaxial layer after the conventional 1050 c process, and the effective thickness of the epitaxial layer after the 950 c process of the present invention.
FIG. 3 shows BV of the device with 1050 ℃ process and 950 ℃ process at the same original thickness of the epitaxial layerDSSThe test curve is shown schematically.
Description of the reference numerals
1 is the substrate, 2 is the epitaxial layer, 3 is the bulk region, and T is the epitaxial layer effective thickness.
Detailed Description
The following detailed description of the present invention is provided with reference to the accompanying drawings, and the technical solutions in the present invention will be clearly and completely described, but the present invention is not limited to the following embodiments. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is noted that the drawings are in greatly simplified form and that non-precision ratios are used for convenience and clarity only to aid in the description of the embodiments of the invention. All other embodiments obtained by a person skilled in the art without making any inventive step are within the scope of protection of the present invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity, and the same reference numerals denote the same elements throughout. It will be understood that when an element or layer is referred to as being "on" …, "adjacent to …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on …," "directly adjacent to …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
In order to make the technical means, the creation characteristics, the achievement purposes and the effects of the invention easy to understand, the invention is further explained below by combining the specific drawings.
The invention relates to a process method of a trench type power MOSFET device, which is formed in an epitaxial layer on a semiconductor substrate, and takes a silicon substrate as an example, when the process of forming a sacrificial silicon oxide layer is carried out on the epitaxial layer, a low-temperature process temperature not higher than 1050 ℃ is adopted to manufacture and form the sacrificial oxide layer.
Because the traditional forming process of the sacrificial oxide layer is a high-temperature furnace tube process at 1050 ℃, under the high-temperature process, due to the difference of carrier concentration, carriers in the original substrate can be reversely diffused into the epitaxial layer and continuously diffuse from the lower part of the epitaxial layer to the center of the epitaxial layer or even to the upper layer of the epitaxial layer, so that the number of the carriers in the epitaxial layer close to the substrate is increased, the thickness of the epitaxial layer keeping the original carrier concentration is gradually reduced, which is equivalent to that the effective thickness of the epitaxial layer is reduced, and BV is causedDSSIs reduced. And the higher the temperature, the more carriers diffuse into the epitaxial layer, resulting in a thinner effective thickness of the epitaxial layer, BVDSSThe lower.
The invention reduces the traditional process temperature of 1050 ℃, and adopts the lower process temperature of 950 ℃ to form the same thickness of the sacrificial oxide layer as the traditional process. Under the low-temperature process, the number of carriers entering the epitaxial layer in the substrate is reduced, and the influence on the effective thickness of the epitaxial layer is reduced under the condition that the thickness of the integral epitaxial layer is kept the same as that of the traditional process, so that the effective thickness of the epitaxial layer is improved as much as possible, as shown in fig. 2, a section shown by an arrow in the figure is the effective thickness of the epitaxial layer, and through comparison between the process of the invention and the traditional process, the effective thickness of the epitaxial layer after the process of the invention is higher than that after the traditional process.
By testing devices formed by the process of the present invention, the data obtained is shown in fig. 3, using a sacrificial oxide layer formed with a thickness of 500 a as an example, such thatBV with conventional process temperature of 1050 deg.CDSSAverage value of about 40V, and the device processed at 950 ℃ of the invention has BV after a large number of testsDSSThe average value of the voltage can be stabilized at about 44.5V basically, and the promotion is obvious.
Therefore, according to the process method of the trench type power MOSFET device, the process temperature of the forming process of the sacrificial oxide layer is reduced, when the sacrificial oxide layer with the same thickness as that of the traditional process is formed, the quantity of current carriers in the substrate which are reversely diffused into the epitaxial layer is reduced through the low-temperature process, the effective thickness of the epitaxial layer is increased, and the breakdown voltage BV is improvedDSS。
The above are merely preferred embodiments of the present invention, and are not intended to limit the present invention. Various modifications and alterations to this invention will become apparent to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (6)
1. A process method of a trench type power MOSFET device is characterized in that: the groove type power MOSFET device is formed in an epitaxial layer on a semiconductor substrate, and when a sacrificial silicon oxide layer is formed on the epitaxial layer, the sacrificial silicon oxide layer is formed at a low-temperature process temperature not higher than 1050 ℃.
2. The process of manufacturing a trench power MOSFET of claim 1 wherein: the semiconductor substrate comprises a silicon substrate, a germanium-silicon substrate, a gallium arsenide substrate, an indium phosphide substrate and a silicon carbide substrate.
3. The process of manufacturing a trench power MOSFET of claim 1 wherein: the forming process temperature of the sacrificial oxide layer is 950 ℃.
4. The process of manufacturing a trench power MOSFET of claim 1 wherein: the thickness of the sacrificial oxide layer manufactured at the low-temperature process temperature is consistent with that of the sacrificial oxide layer manufactured at the high-temperature process.
5. The process of manufacturing a trench power MOSFET of claim 1 wherein: the low temperature process reduces the number of carriers in the substrate extending into the epitaxial layer, increases the effective thickness of the epitaxial layer, and thereby improves the breakdown voltage BVDSS。
6. The process of manufacturing a trench power MOSFET of claim 1 wherein: and forming a sacrificial oxide layer by adopting a furnace tube process.
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| CN202111011366.5A CN113782589A (en) | 2021-08-31 | 2021-08-31 | Process method of groove type power MOSFET device |
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| CN202111011366.5A CN113782589A (en) | 2021-08-31 | 2021-08-31 | Process method of groove type power MOSFET device |
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Citations (9)
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| KR20080002495A (en) * | 2006-06-30 | 2008-01-04 | 주식회사 하이닉스반도체 | Method for manufacturing nand flash memory device |
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| CN106340448A (en) * | 2016-11-28 | 2017-01-18 | 清华大学 | Manufacturing method of gate oxidation layer of SiC power MOSFET device and SiC power MOSFET device |
| CN109904223A (en) * | 2019-01-23 | 2019-06-18 | 上海华虹宏力半导体制造有限公司 | The process of gate trench top chamfer |
| CN112053957A (en) * | 2020-09-10 | 2020-12-08 | 深圳市芯电元科技有限公司 | Manufacturing method of trench MOSFET |
| CN112802742A (en) * | 2021-03-24 | 2021-05-14 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing semiconductor device |
-
2021
- 2021-08-31 CN CN202111011366.5A patent/CN113782589A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH05129426A (en) * | 1991-10-30 | 1993-05-25 | Oki Electric Ind Co Ltd | Element isolation method of semiconductor device |
| KR20010065668A (en) * | 1999-12-30 | 2001-07-11 | 박종섭 | Method for forming isolation layer of a semiconductor device |
| KR20060113273A (en) * | 2005-04-30 | 2006-11-02 | 매그나칩 반도체 유한회사 | Method for manufacturing a semiconductor device |
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| CN109904223A (en) * | 2019-01-23 | 2019-06-18 | 上海华虹宏力半导体制造有限公司 | The process of gate trench top chamfer |
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