CN112349769A - Super junction terminal structure for improving avalanche capability and manufacturing method - Google Patents
Super junction terminal structure for improving avalanche capability and manufacturing method Download PDFInfo
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- CN112349769A CN112349769A CN202011005472.8A CN202011005472A CN112349769A CN 112349769 A CN112349769 A CN 112349769A CN 202011005472 A CN202011005472 A CN 202011005472A CN 112349769 A CN112349769 A CN 112349769A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 238000000407 epitaxy Methods 0.000 claims abstract description 25
- 238000005530 etching Methods 0.000 claims abstract description 17
- 238000000151 deposition Methods 0.000 claims abstract description 16
- 238000001259 photo etching Methods 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims abstract description 9
- 210000000746 body region Anatomy 0.000 claims abstract description 8
- 238000002347 injection Methods 0.000 claims abstract description 8
- 239000007924 injection Substances 0.000 claims abstract description 8
- 238000000137 annealing Methods 0.000 claims abstract description 7
- 239000012535 impurity Substances 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 239000002184 metal Substances 0.000 claims abstract description 4
- 229910052751 metal Inorganic materials 0.000 claims abstract description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 4
- 229920005591 polysilicon Polymers 0.000 claims abstract description 4
- 238000002513 implantation Methods 0.000 claims description 9
- 230000005669 field effect Effects 0.000 claims description 3
- 230000007704 transition Effects 0.000 claims description 3
- 238000012545 processing Methods 0.000 abstract description 4
- 230000003071 parasitic effect Effects 0.000 description 9
- 230000015556 catabolic process Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 4
- 238000009826 distribution Methods 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 238000013461 design Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
Abstract
The invention relates to a method for manufacturing a super junction terminal structure capable of improving avalanche capability, which comprises the steps of growing an N-epitaxy on an N + substrate; injecting N-type impurities in N-epitaxy, wherein the injection size in the terminal region is X3 & gt X2 & gt X1; on the surface of the N-epitaxy, growing a P-type epitaxy after etching a deep trench, and filling the deep trench with the P-type epitaxy; performing a CMP process, and removing the P-type epitaxy and the N-epitaxy outside the deep trench to form a super junction structure with N columns and P columns alternating; injecting a body region through a PW photoetching plate and annealing to form a PWELL region; depositing a field oxide layer and etching back, forming gate by depositing gate oxide and polysilicon and etching back, injecting As or P, and forming N-source by pushing a well; and depositing ILD and etching back, carrying out hole injection, and finally depositing metal and etching back to form the final structure of the device. The invention can effectively reduce the area of the terminal, improve the current processing capability of the device and reduce the cost of the device under the same avalanche capability requirement.
Description
Technical Field
The invention belongs to the technical field of semiconductor discrete devices, and particularly relates to a super junction terminal structure capable of improving avalanche capability and a manufacturing method thereof.
Background
The super-junction VDMOS is a novel power semiconductor device which is rapidly developed and widely applied. The super junction structure is introduced on the basis of a common vertical double-diffused metal oxide semiconductor (VDMOS), so that the VDMOS has the advantages of high input impedance, high switching speed, high working frequency, voltage control, good thermal stability and simple driving circuit, and the defect that the relation between the on-resistance and the breakdown voltage of the VDMOS is sharply increased to the power of 2.5 is overcome. At present, the super junction VDMOS is widely applied to power supplies or adapters of computers, mobile phones, lighting, liquid crystal or plasma televisions, game machines and other consumer electronic products.
The avalanche capability of a VDMOS device is seriously restricted by a secondary breakdown effect caused by a parasitic BJT when the traditional VDMOS is subjected to avalanche breakdown, a bipolar transistor BJT is inevitably parasitic near a Pbody region, the Pbody region forms a base region of the parasitic BJT, meanwhile, a collector and an emitter of the parasitic BJT are respectively a drain and a source of the VDMOS, and in addition, the parasitic BJT has an equivalent resistance RB from the source of the VDMOS to the Pbody region. When the VDMOS is in a blocking state, the internal electric field of the device is gradually increased along with the increase of the drain-source voltage, and the leakage current is increased along with the increase of the internal electric field. When partial leakage current flows through a BJT body region, voltage drop is generated at two ends of an equivalent resistor RB and is equal to VBE of a parasitic triode BJT, when a VDMOS approaches avalanche breakdown, the leakage current is increased sharply, and if the voltage drop on the RB is enough to enable the parasitic triode to be turned on, the parasitic BJT can cause secondary breakdown effect. For a super junction MOSFET, to avoid the turn-on of a parasitic BJT, the current flowing through RB during avalanche needs to be reduced, so under a certain avalanche current condition, the design of the position of a breakdown point of a super junction device becomes particularly important, at present, the current flowing through RB is reduced by mainly making P-region charges larger than N-region charges to enable the breakdown point to occur in the body or at the bottom of a P column, but in this case, the potential of a terminal is concentrated to the edge to cause the breakdown of the outer edge of the junction terminal, and the number of terminals trench needs to be increased to solve the problem, but the junction terminal area is increased.
The junction terminal is used as an important component of a power semiconductor device and plays an important role in realizing and improving system performance. The requirements for the structure of the junction termination include a plurality of aspects such as high area efficiency and good reliability. The area efficiency of the power device is greatly dependent on the junction terminal structure, and when the area occupied by the junction terminal is reduced, the area of the active region is increased on the same chip area, so that the current processing capacity can be improved.
Disclosure of Invention
The invention aims to provide a super junction terminal structure capable of improving avalanche capability and a manufacturing method thereof, which can effectively improve the avalanche energy of a device and guarantee the current processing capability and the reliability of the device on the premise of ensuring a small-size terminal.
The technical scheme adopted by the invention is as follows:
the manufacturing method of the super junction terminal structure for improving the avalanche capability is characterized in that:
the method comprises the following steps:
step 1: growing a layer of N-epitaxy on the N + substrate;
step 2: injecting N-type impurities in N-epitaxy, wherein the injection size in the terminal region is X3 & gt X2 & gt X1;
and step 3: on the surface of the N-epitaxy, a deep groove is etched through a Trench photoetching plate, and then a P-type epitaxy is grown to fill the deep groove; performing a CMP process, and removing the P-type epitaxy and the N-epitaxy outside the deep trench to form a super junction structure with N columns and P columns alternating;
and 4, step 4: injecting a body region through a PW photoetching plate and annealing to form a PWELL region;
and 5: depositing a field oxide layer and etching back, forming gate by depositing gate oxide and polysilicon and etching back, injecting As or P, and forming N-source by pushing a well;
step 6: and depositing ILD and etching back, carrying out hole injection, and finally depositing metal and etching back to form the final structure of the device.
In step 1, the resistivity of the epitaxial N-is higher than that of the N + substrate.
In the step 2, N-type impurities are implanted in a JFET (junction field effect transistor) implantation mode, the implantation dosage is 2e12 cm < -2 > to 5e12 cm < -2 >, and the implantation energy is 60kev to 80 kev.
In step 2, X3 is located at two mesas at the periphery of the terminal, X2 is located at the 3 rd and 4 th mesas at the periphery of the terminal, and X1 is located at the centers of the cell mesas and the 5 th mesas at the terminal.
And 4, implanting a body region through the PW photoetching plate and annealing to form a PWELL region in the cell and the transition region.
The super junction terminal structure with improved avalanche capability is obtained by the manufacturing method.
The invention has the following advantages:
the structure and the method can effectively reduce the area of the terminal, improve the current processing capacity of the device and reduce the cost of the device under the same avalanche capability requirement on the premise of not changing the existing super junction process flow and not additionally increasing the photoetching mask; the avalanche tolerance of the device is effectively improved on the premise of not increasing the area of the terminal, and the reliability of the device is improved.
Drawings
FIG. 1 is a schematic diagram of step 1.
FIG. 2 is a schematic diagram of step 2.
FIG. 3 is a schematic diagram of step 3.
FIG. 4 is a schematic diagram of step 4.
FIG. 5 is a schematic diagram of step 5.
FIG. 6 is a schematic diagram of step 6.
Fig. 7 is a schematic diagram of avalanche current distribution of the super junction termination structure of the present invention.
Fig. 8 is a schematic diagram of avalanche current distribution of a conventional super junction termination structure.
Detailed Description
The present invention will be described in detail with reference to specific embodiments.
The invention relates to a super junction terminal structure manufacturing method for improving avalanche capability, which comprises the following steps:
step 1: growing a layer of N-epitaxy on the N + substrate;
step 2: injecting N-type impurities in N-epitaxy, wherein the injection size in the terminal region is X3 & gt X2 & gt X1;
and step 3: on the surface of the N-epitaxy, a deep groove is etched through a Trench photoetching plate, and then a P-type epitaxy is grown to fill the deep groove; performing a CMP process, and removing the P-type epitaxy and the N-epitaxy outside the deep trench to form a super junction structure with N columns and P columns alternating;
and 4, step 4: injecting a body region through a PW photoetching plate and annealing to form a PWELL region;
and 5: depositing a field oxide layer and etching back, forming gate by depositing gate oxide and polysilicon and etching back, injecting As or P, and forming N-source by pushing a well;
step 6: and depositing ILD and etching back, carrying out hole injection, and finally depositing metal and etching back to form the final structure of the device.
In step 1, the resistivity of the epitaxial N-is higher than that of the N + substrate.
In the step 2, N-type impurities are implanted in a JFET (junction field effect transistor) implantation mode, the implantation dosage is 2e12 cm < -2 > to 5e12 cm < -2 >, and the implantation energy is 60kev to 80 kev. X3 is located at two mesas at the periphery of the terminal, X2 is located at the 3 rd and 4 mesas at the periphery of the terminal, and X1 is located at the center of the cell mesas and the 5 th mesas at the terminal.
And 4, implanting a body region through the PW photoetching plate and annealing to form a PWELL region in the cell and the transition region.
Through the design and verification of the invention, compared with the conventional super junction terminal, on the premise of P-rich inside a device, the structure of the invention can effectively improve the distribution of the terminal electric field, so that the avalanche current is concentrated in a cell region, the avalanche energy is effectively improved, and the terminal area is reduced.
The invention is not limited to the examples, and any equivalent changes to the technical solution of the invention by a person skilled in the art after reading the description of the invention are covered by the claims of the invention.
Claims (6)
1. The manufacturing method of the super junction terminal structure for improving the avalanche capability is characterized in that:
the method comprises the following steps:
step 1: growing a layer of N-epitaxy on the N + substrate;
step 2: injecting N-type impurities in N-epitaxy, wherein the injection size in the terminal region is X3 & gt X2 & gt X1;
and step 3: on the surface of the N-epitaxy, a deep groove is etched through a Trench photoetching plate, and then a P-type epitaxy is grown to fill the deep groove; performing a CMP process, and removing the P-type epitaxy and the N-epitaxy outside the deep trench to form a super junction structure with N columns and P columns alternating;
and 4, step 4: injecting a body region through a PW photoetching plate and annealing to form a PWELL region;
and 5: depositing a field oxide layer and etching back, forming gate by depositing gate oxide and polysilicon and etching back, injecting As or P, and forming N-source by pushing a well;
step 6: and depositing ILD and etching back, carrying out hole injection, and finally depositing metal and etching back to form the final structure of the device.
2. The method of manufacturing a superjunction termination structure with improved avalanche capability of claim 1, wherein:
in step 1, the resistivity of the epitaxial N-is higher than that of the N + substrate.
3. The method of manufacturing a superjunction termination structure with improved avalanche capability of claim 2, wherein:
in the step 2, N-type impurities are implanted in a JFET (junction field effect transistor) implantation mode, the implantation dosage is 2e12 cm < -2 > to 5e12 cm < -2 >, and the implantation energy is 60kev to 80 kev.
4. The method of manufacturing a superjunction termination structure with improved avalanche capability of claim 3, wherein:
in step 2, X3 is located at two mesas at the periphery of the terminal, X2 is located at the 3 rd and 4 th mesas at the periphery of the terminal, and X1 is located at the centers of the cell mesas and the 5 th mesas at the terminal.
5. The method of manufacturing a superjunction termination structure with improved avalanche capability of claim 4, wherein:
and 4, implanting a body region through the PW photoetching plate and annealing to form a PWELL region in the cell and the transition region.
6. A super junction termination structure with improved avalanche capability obtained by the manufacturing method as claimed in claim 5.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011005472.8A CN112349769A (en) | 2020-09-23 | 2020-09-23 | Super junction terminal structure for improving avalanche capability and manufacturing method |
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| CN202011005472.8A CN112349769A (en) | 2020-09-23 | 2020-09-23 | Super junction terminal structure for improving avalanche capability and manufacturing method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114184091A (en) * | 2021-04-08 | 2022-03-15 | 西安龙飞电气技术有限公司 | Infrared radar dual-mode digital processing method for air-to-air missile seeker |
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2020
- 2020-09-23 CN CN202011005472.8A patent/CN112349769A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114184091A (en) * | 2021-04-08 | 2022-03-15 | 西安龙飞电气技术有限公司 | Infrared radar dual-mode digital processing method for air-to-air missile seeker |
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