CN210224042U

CN210224042U - Planar structure channel metal oxide semiconductor field effect transistor

Info

Publication number: CN210224042U
Application number: CN201920963740.3U
Authority: CN
Inventors: Ji Pan; 潘继; Peng Xu; 徐鹏
Original assignee: Wuxi Vodaco Semiconductor Technology Co ltd
Current assignee: Wuxi Vodaco Semiconductor Technology Co ltd
Priority date: 2019-06-25
Filing date: 2019-06-25
Publication date: 2020-03-31
Anticipated expiration: 2029-06-25

Abstract

The utility model discloses a planar structure channel metal oxide semiconductor field effect transistor. The planar structure channel metal oxide semiconductor field effect transistor comprises a substrate, wherein the substrate respectively comprises a first substrate and a second substrate from bottom to top, the first substrate is a P-type wafer substrate, and the second substrate is processed by a deep N-well process. A plurality of channels are formed on the upper surface of the second substrate at intervals, a grid electrode is formed in each channel, a source electrode and a drain electrode are respectively formed on two adjacent sides of each channel, and the grid electrode, the source electrode and the drain electrode are located on the same side of the base body. The utility model discloses well channel type grid and the grid that the homonymy set up, source electrode and drain electrode structure can improve the conductivity, reduce the unit interval to reduce integrated power chip's unit on-resistance, improve the conductivity, and reduce the transistor area under the same property condition about half, be convenient for simultaneously integrate a plurality of transistor structures on same base member.

Description

Planar structure channel metal oxide semiconductor field effect transistor

Technical Field

The present invention relates to the field of integrated circuit semiconductors, and more particularly, to a planar trench mosfet and a method of fabricating the same.

Background

The LDMOS in the prior art is a MOSFET device in an integrated power chip, can be easily integrated on a chip with a CMOS process, and provides better unit on-resistance (RdsA) and high switching speed. The trench type MOSFET may provide a smaller wafer footprint because the trench type MOSFET may achieve a smaller cell pitch and higher current density.

For example, under the process of a withstand voltage class (BV) of 34V, the channel type MOSFET can reach a unit on-resistance value RdsA (Vgs ═ 5V) of 3-4 mOhm-mm2, and the LDMOS with the same withstand voltage class can only reach RdsA (Vgs ═ 5V) -7 mOhm-mm2 (the lower the number is, the lower the unit on-resistance value is, the higher the efficiency of the MOSFET is).

However, the electrodes of the channel MOSFET are distributed on the upper and lower ends of the wafer, so that the channel MOSFET cannot be integrated with the CMOS process.

SUMMERY OF THE UTILITY MODEL

The utility model provides a planar structure channel metal oxide semiconductor field effect transistor, which comprises a substrate, wherein the substrate comprises a first substrate and a second substrate from bottom to top respectively, the first substrate is a P-type wafer substrate, the second substrate is processed by a deep N-well process,

the upper surface of the second substrate is provided with a plurality of channels which are spaced from each other, a grid electrode is formed in each channel, a source electrode and a drain electrode are respectively formed on two adjacent sides of each channel, and the grid electrode, the source electrode and the drain electrode are positioned on the same side of the base body.

The utility model discloses well channel type grid and the grid that the homonymy set up, source electrode and drain electrode structure can improve the conductivity, reduce the unit interval to reduce integrated power chip's unit on-resistance, improve the conductivity, and reduce the transistor area under the same property condition about half, be convenient for simultaneously integrate a plurality of transistor structures on same base member.

In some embodiments, the second substrate has an oxide layer on its upper surface.

In some embodiments, the trench surface forms uniform or non-uniform oxide layer sidewalls.

In some embodiments, the trench is filled with a polycrystalline material.

In some embodiments, the source forms an N + diffusion region and a P-diffusion region from bottom to top.

In some embodiments, the drain forms an N + diffusion region.

Additional aspects and advantages of embodiments of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.

Drawings

The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

fig. 1 is a schematic cross-sectional view of a planar structure trench mosfet according to an embodiment of the present invention;

fig. 2 is a schematic flow chart illustrating a method of processing a planar trench mosfet according to an embodiment of the present invention;

fig. 3 is another schematic cross-sectional view of a planar trench mosfet according to an embodiment of the present invention.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are exemplary only for the purpose of explaining the present invention, and should not be construed as limiting the present invention.

Referring to fig. 1-3, a planar structure trench mosfet according to an embodiment of the present invention includes a substrate, the substrate includes a first substrate 10 and a second substrate 20 from bottom to top, the first substrate 10 is a P-type wafer substrate, and the second substrate 20 is processed by a deep N-well process. A plurality of channels are formed on the upper surface of the second substrate 20, a gate 30 is formed in each channel, a source 40 and a drain 50 are respectively formed on two adjacent sides of each channel, and the gate 30, the source 40 and the drain 50 are located on the same side of the substrate.

The utility model discloses well channel type grid 30 and grid 30, source 40 and the drain electrode 50 structure that the homonymy set up can improve the turn-on performance, reduce the unit interval to reduce integrated power supply chip's unit on-resistance, improve the turn-on performance, and reduce the transistor area under the same property condition about half, be convenient for simultaneously integrate a plurality of transistor structures on same base member.

In particular, the integrated use of MOSFETs and ICs may reduce capacitance/inductance/resistance, thereby achieving higher performance and faster switching speeds.

Lateral diffused MOS transistors (LDMOS) are widely integrated with ICs because of their ease of integration with CMOS circuitry, relatively low resistivity (RdsA) and fast switching speed.

Compared with the LDMOSFET, the trench MOSFET has better use effect and can reach lower RdsA due to narrower unit space and higher current density. For example, when BV is 34V, the trench MOSFET may realize RdsA (Vgs 5V)3 to 4mOhm-mm 2. With the same BVDSS, LDMOS can achieve RdsA (Vgs ═ 5V) to 7mOhm-mm 2.

Therefore, the trench MOSFET can realize half lower RdsA than the LDMOSFET, or can be made into smaller size on the premise of reaching the same Rdson, thereby achieving greater economic benefit.

However, the conventional trench MOSFET has the source and gate electrodes designed at the top and the drain electrode designed at the bottom, and thus it is difficult to integrate the conventional trench MOSFET with a CMOS process.

The utility model provides an use transistor of trench DMOS structure, the Rdson performance is improved and keep less transistor area easily integrated with the IC circuit.

Specifically, the current flow of the planar trench mosfet according to the embodiment of the present invention is shown in fig. 1.

In some embodiments, the upper surface of the second substrate 10 is covered with an oxide layer.

In some embodiments, the trench surface forms uniform or non-uniform oxide sidewalls.

In some embodiments, the trench is filled with a polycrystalline material.

In some embodiments, the source 40 forms an N + diffusion region and a P-diffusion region from bottom to top.

In some embodiments, drain 50 forms an N + diffusion region.

In addition, as shown in fig. 3, the gate poly in the deep trench can be further separated into 2 sections by the filled oxide layer, and a gate polymer and a source polymer are respectively formed from top to bottom, so as to form a shunt gate structure.

As such, the specific resistance (RdsA) is further reduced due to drift region charge balance.

The utility model provides a method for processing planar structure channel metal oxide semiconductor field effect transistor, including the following steps:

s1: an oxide layer is formed on the upper surface of the substrate,

s2: etching the oxide layer to form a recess,

s3: the recess is silicon etched to form a channel,

s4: growing an oxide layer in the channel, and growing an oxide layer in the channel,

s5: the oxide layer in the trench is etched to form a deep trench,

s6: growing grid polycrystal on the deep groove and the oxide layer on the upper surface of the substrate,

s7: etching the polycrystal, removing the polycrystal on the upper surface of the substrate, covering the channel through the oxide layer,

s8: p body implantation and activation and N source implantation and activation are carried out on the substrate.

Specifically, in step S5, an oxide etch is performed using the PR mask to form a deep trench, and the PR mask is removed.

The channel type grid 30 of the planar structure channel metal oxide semiconductor field effect transistor processed by the processing method of the planar structure channel metal oxide semiconductor field effect transistor and the grid 30, the source 40 and the drain 50 structures arranged on the same side can improve the conduction performance and reduce the unit spacing, thereby reducing the unit conduction resistance of an integrated power chip, improving the conduction performance, reducing the area of the transistor under the condition of the same performance by about half, and simultaneously facilitating the integration of a plurality of transistor structures on a single semiconductor tube core, so that a semiconductor element can be easily integrated into a high-end driver.

While embodiments of the present invention have been shown and described, it will be understood by those of ordinary skill in the art that: various changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A planar structure channel metal oxide semiconductor field effect transistor is characterized by comprising a substrate, wherein the substrate respectively comprises a first substrate and a second substrate from bottom to top, the first substrate is a P-type wafer substrate, the second substrate is processed by a deep N-well process,

2. The planar structure trench mosfet of claim 1 wherein the top surface of the second substrate is covered with an oxide layer.

3. The planar structure trench mosfet of claim 1 wherein the trench surface forms uniform or non-uniform oxide sidewalls.

4. The planar structure trench mosfet of claim 1 wherein the trench is filled with a polycrystalline material.

5. The planar structure trench mosfet of claim 1 wherein the source is formed from bottom to top with N + and P-diffusion regions.

6. The planar structure trench mosfet of claim 5 wherein said drain forms an N + diffusion region.