CN104517853A - Super-junction semiconductor device manufacturing method - Google Patents
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- CN104517853A CN104517853A CN201410204523.8A CN201410204523A CN104517853A CN 104517853 A CN104517853 A CN 104517853A CN 201410204523 A CN201410204523 A CN 201410204523A CN 104517853 A CN104517853 A CN 104517853A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
Abstract
The invention discloses a super-junction semiconductor device manufacturing method. The method includes the steps: injecting first electroconductive type impurities on an N-silicon wafer; forming a first electroconductive type diffusion area through diffusion junction pushing; forming multiple grooves through photoetching, and enabling first electroconductive type diffusion area thin layers among the grooves to form a structure which is in alternate arrangement; filling the grooves with uniformly-doped second electroconductive type epiaxial layers, and forming a super-junction structure formed by the first electroconductive type thin layers and second electroconductive type thin layers which are in alternate arrangement. The super-junction structure is directly formed in the diffusion area, so that cost can be lowered greatly; due to a doping concentration structure of the diffusion area, side wall angles of the grooves can be reduced, difficulty in forming the grooves can be lowered greatly, and process cost is further lowered; super-junction IGBT (insulated gate bipolar transistor) and MOSFET (metal oxide semiconductor field effect transistor) devices or semi-super-junction IGBT and MOSFET devices can be formed easily by combining the method with back thinning and back laser annealing processes.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit manufacture method, particularly relate to a kind of super junction-semiconductor device manufacture method.
Background technology
The appearance of existing vertical double diffused metal-oxide semiconductor field effect transistor (VDMOS) structure, makes the development of power electronics enter into new stage.Existing VDMOS is many electronic conductivities device, has that switching speed is fast, input impedance is high, easy driving, there is not the advantages such as secondary-breakdown phenomenon.Desirable VDMOS should have lower conducting resistance, switching loss and higher blocking voltage.In the withstand voltage application of height, existing VDMOS needs to increase the thickness of epitaxial loayer and reduces the doping content of epitaxial loayer to improve puncture voltage, and this simultaneously also can the conducting resistance of increased device, increases power consumption.Due to the restraining function in 2.5 powers (silicon limit theory) between the conducting resistance of existing VDMOS and puncture voltage, limit the development of high-voltage power VDMOS.
Late 1980s, " silicon limit theory " has been broken in a kind of proposition of new structure.D.J.Coe proposed the p type island region that to adopt in the Laterally Diffused Metal Oxide Semiconductor pipe (LDMOS) and be alternately arranged first in 1988 and N-type region replaces low-doped drift layer in existing LDMOS power device to make the method for voltage support layer, i.e. super junction LDMOS.The Chen Xing of electronics University of Science and Technology in 1993 academician that assists proposes and replaces the new construction of the drift layer of existing VDMOS theoretical by the p type island region be alternately arranged and N-type region structure in VDMOS pipe, namely be called as superjunction (Super-junction in the future, SJ) pressure-resistance structure, it requires the charge balance of N-type region and p type island region, under identical conducting resistance, the puncture voltage of hyperconjugation VDMOS is far longer than traditional VDMOS.
The preparation technology of existing super junction power device is mainly divided into two large classes:
The first utilizes repeatedly the mode of extension and injection to form P post in N-type epitaxial substrate; Repeatedly epitaxy technique makes process costs greatly increase.
The second is that the mode of filling in the deep plough groove etched P of adding post extension is formed.Add P post extension utilizing deep trench to insert mode and prepare in the technique of super junction, general employing epitaxial wafer, add extension in epitaxial loayer grooving and form P post, the impurity concentration of P post is normally homogeneous, therefore trench angles is more close to 90 degree, charge matching is better, and device withstand voltage (BV) is also higher.Wherein, the cost of epitaxial wafer is also higher, obtains sidewall large close to the technology difficulty of the groove of 90 degree.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of super junction-semiconductor device manufacture method, can reduce technology difficulty and process costs.
For solving the problems of the technologies described above, super junction-semiconductor device manufacture method provided by the invention comprises the steps:
Step one, at N-grown above silicon first oxide-film, on described silicon chip, inject the first conductive type impurity through described first oxide-film.
Step 2, diffusion knot is carried out to the first injected conductive type impurity and forms the first conduction type diffusion region; From described silicon chip surface to the bottom of described first conduction type diffusion region, the doping content of described first conduction type diffusion region reduces gradually.
Step 3, employing lithographic etch process form multiple groove in described first conduction type diffusion region, and the first conduction type thin layer be made up of described first conduction type diffusion region between described groove and each described groove forms the structure be alternately arranged; The Sidewall angles of each described groove is 86 degree ~ 88 degree, and the width of each described groove is reduced from the top to the bottom step by step.
Step 4, adopt epitaxial growth technology in each described groove, fill the second conductive type epitaxial layer of Uniform Doped, the second conduction type thin layer is formed by the second conductive type epitaxial layer in each described groove, super-junction structures is formed by the described first conduction type thin layer be alternately arranged and described second conduction type thin layer, utilize the charge matching that the doping content of described first conduction type thin layer reduces from the top to the bottom step by step and the width of described second conduction type thin layer reduces from the top to the bottom step by step characteristic realizes between described first conduction type thin layer and described second conduction type thin layer.
Further improvement is, also comprises following front processing step:
Step 5, formation grid oxygen, polysilicon gate, P type channel region, source region, interlayer film, contact hole, front metal and passivation layer.
Further improvement is, described super junction-semiconductor device is super junction MOSFET element, also comprises following back process step:
Step 6, thinning back side is carried out to described silicon chip.
Step 7, carry out backside particulate and inject and form N-type resilient coating.
Step 8, carry out backside particulate and inject and form N+ contact layer.
Step 9, described N-type resilient coating and described N+ contact layer carried out to annealing and activate.
Step 10, formation back metal.
Further improvement is, described super junction-semiconductor device is super junction insulated gate bipolar transistor (IGBT) device, also comprises following back process step:
Step 6, thinning back side is carried out to described silicon chip.
Step 7, carry out backside particulate and inject and form N-type resilient coating.
Step 8, carry out backside particulate and inject and form P+ contact layer.
Step 9, described N-type resilient coating and described P+ contact layer carried out to annealing and activate.
Step 10, formation back metal.
Further improvement is, the Implantation Energy of the first conductive type impurity described in step one is 20Kev ~ 2Mev, implantation dosage 5e11cm
-2~ 5e13cm
-2.
Further improvement is, the temperature spreading knot in step 2 is 1200 DEG C ~ 1300 DEG C; The junction depth of described first conduction type diffusion region is 10 microns ~ 50 microns.
Further improvement is, in step 6 by described wafer thinning to 20 microns ~ 80 microns.
Further improvement is, the Implantation Energy that the backside particulate of the resilient coating of N-type described in step 7 injects is 200Kev ~ 10Mev, implantation dosage 5e10cm
-2~ 5e13cm
-2.
Further improvement is, the Implantation Energy that the backside particulate of the contact layer of N+ described in step 8 injects is 10Kev ~ 100Kev, implantation dosage 1e14cm
-2~ 1e16cm
-2.
Further improvement is, the Implantation Energy that the backside particulate of the contact layer of P+ described in step 8 injects is 10Kev ~ 50Kev, implantation dosage 1e12cm
-2~ 1e15cm
-2.
Super-junction structures of the present invention is formed directly in diffusion region, so do not need to adopt epitaxial wafer, can greatly reduce costs; Simultaneously, the doping content of diffusion region reduces from the top to the bottom step by step, this makes the Sidewall angles of groove of the present invention to reduce, can not only make between P type thin layer and N-type thin layer, to realize good charge matching, greatly can also reduce the difficulty making groove, thus further reduce process costs.
By the change to back process, the present invention is applied to the manufacture of super junction MOSFET element and super junction VDMOS and super junction IGBT device, by the change of the back process to super junction IGBT device can also in super junction IGBT device an integrated fast recovery diode thus form super junction against conductivity type IGBT (RC IGBT).
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 is the embodiment of the present invention one method flow diagram;
Fig. 2 is the device architecture figure that the embodiment of the present invention two method is formed;
Fig. 3 is the device architecture figure that the embodiment of the present invention two method is formed;
Fig. 4 is the device architecture figure that the embodiment of the present invention three method is formed.
Embodiment
As shown in Figure 1, be the embodiment of the present invention one method flow diagram; As shown in Figure 2, be the device architecture figure that the embodiment of the present invention one method is formed.The embodiment of the present invention one super junction-semiconductor device manufacture method comprises the steps:
Step one, on N-silicon chip 1, grow the first oxide-film, on described silicon chip 1, inject the first conductive type impurity through described first oxide-film.Described silicon chip 1 vertical pulling (CZ) monocrystalline silicon piece or zone melting single-crystal (FZ) silicon chip.The Implantation Energy of described first conductive type impurity is 20Kev ~ 2Mev, implantation dosage 5e11cm
-2~ 5e13cm
-2, implantation dosage can require adjustment by the withstand voltage and diffusion junction depth concrete according to device.
In device architecture corresponding to Fig. 2, the first conduction type is N-type, and the second conduction type is P type.The reversion of the doping type of the first and second conduction types is equally applicable to embodiment of the present invention method, and namely the first conduction type is P type, and the second conduction type is that N-type is equally applicable to embodiment of the present invention method.
Step 2, diffusion knot is carried out to the first injected conductive type impurity and forms the first conduction type diffusion region 2; From described silicon chip 1 surface to the bottom of described first conduction type diffusion region 2, the doping content of described first conduction type diffusion region 2 reduces gradually.The temperature of described diffusion knot is 1200 DEG C ~ 1300 DEG C; The junction depth of described first conduction type diffusion region 2 is 10 microns ~ 50 microns, and junction depth can adjust according to requirement of withstand voltage; The time of described diffusion knot sets according to the junction depth of described first conduction type diffusion region 2, ensures that junction depth reaches required value.
Step 3, employing lithographic etch process form multiple groove 3a in described first conduction type diffusion region 2; Be preferably, first a dielectric mask layer is formed on described silicon chip 1 surface when etching groove 3a, adopt lithographic etch process to carry out etching to described dielectric mask layer and form groove 3a figure, adopt the dielectric mask layer being formed with groove 3a figure to make mask and the described groove 3a of etching formation is carried out to silicon.
The the first conduction type thin layer be made up of described first conduction type diffusion region 2 such as the n thin layer in Fig. 2 between described groove 3a and each described groove 3a forms the structure be alternately arranged; The Sidewall angles of each described groove 3a is 86 degree ~ 88 degree, and the width of each described groove 3a is reduced from the top to the bottom step by step; According to the difference of device withstand voltage and diffusion junction depth, trenched side-wall angle can adjust between 86-88 degree, as the Sidewall angles of groove 3a is 87 degree as described in each in the embodiment of the present invention one method.Relative to the vertical stratification that Sidewall angles is 90 degree, the embodiment of the present invention one method can reduce the formation process difficulty of groove greatly, thus reduces process costs.
Step 4, adopt epitaxial growth technology in each described groove 3a, fill the second conductive type epitaxial layer of Uniform Doped, the second conduction type thin layer is formed as the p thin layer in Fig. 2 by the second conductive type epitaxial layer in each described groove 3a, super-junction structures is formed by the described first conduction type thin layer be alternately arranged and described second conduction type thin layer, utilize the charge matching that the doping content of described first conduction type thin layer reduces from the top to the bottom step by step and the width of described second conduction type thin layer reduces from the top to the bottom step by step characteristic realizes between described first conduction type thin layer and described second conduction type thin layer.
Step 5, carry out following front technique:
Form grid oxygen, polysilicon gate, P type channel region 5, source region 6, P+ district 7, interlayer film, contact hole, front metal and passivation layer.JFET layer 4, a JFET layer 4 can also be formed for N-type doping, for reducing the bulk effect of device at super-junction structures top.Draw source electrode by the contact hole that formed at the top in source region 6 and P+ district 7 and front metal, draw grid by the contact hole at polysilicon gate top and front metal.
Described super junction-semiconductor device corresponding to Fig. 2 is super junction MOSFET element.Also comprise following back process step:
Step 6, thinning back side is carried out to described silicon chip 1 and described silicon chip 1 is thinned to 20 microns ~ 80 microns.Described super junction-semiconductor device corresponding to Fig. 2 is super junction MOSFET element, and directly exposed the bottom being arranged the super-junction structures formed by P type thin layer and N-type interlaminate after thinning back side, namely drift region is all made up of super-junction structures.
Step 7, carry out backside particulate and inject and form N-type resilient coating.Be preferably, the Implantation Energy that the backside particulate of described N-type resilient coating injects is 200Kev ~ 10Mev, implantation dosage 5e10cm
-2~ 5e13cm
-2.Described super junction-semiconductor device corresponding to Fig. 2 is super junction MOSFET element, and namely drift region is all made up of super-junction structures, therefore N-type resilient coating also can omit.
Step 8, carry out backside particulate and inject and form N+ contact layer 8.Be preferably, the Implantation Energy that the backside particulate of described N+ contact layer 8 injects is 10Kev ~ 100Kev, implantation dosage 1e14cm
-2~ 1e16cm
-2.
Step 9, described N-type resilient coating and described N+ contact layer 8 carried out to annealing and activate, be preferably, adopt laser annealing to activate.
Step 10, formation back metal, and draw drain electrode by back metal.
Figure shown in dotted line frame 101 in Fig. 2 is the doping content curve at the AA dotted line place along Fig. 2, and BC section corresponds to the doping content of described first conduction type diffusion region 2, can find out that this doping content reduces gradually; CD section corresponds to the doping content of described N+ contact layer 8.
As shown in Figure 3, be the device architecture figure that the embodiment of the present invention two method is formed.The difference part of the embodiment of the present invention two super junction-semiconductor device manufacture method and the embodiment of the present invention one method is:
The described super junction-semiconductor device that the embodiment of the present invention two method is formed is half super junction MOSFET element,
The embodiment of the present invention two method is after the thinning back side of step 6, also remain with certain thickness described silicon chip 1 being arranged by P type thin layer and N-type interlaminate bottom the super-junction structures formed, the described silicon chip 1 of this reservation is as bottom auxiliary layer (BAL), by super-junction structures, whole drift region adds that bottom auxiliary layer forms, therefore be called half super-junction structures.
The embodiment of the present invention two method is carried out backside particulate and is injected formation N-type resilient coating 9 in step 7.Be preferably, the Implantation Energy that the backside particulate of described N-type resilient coating 9 injects is 200Kev ~ 10Mev, implantation dosage 5e10cm
-2~ 5e13cm
-2.
The step one of the embodiment of the present invention two method is all identical with the embodiment of the present invention one method to step 10 to step 5, step 8.
Figure shown in dotted line frame 102 in Fig. 3 is the doping content curve at the EE dotted line place along Fig. 3, and FG section corresponds to the doping content of described first conduction type diffusion region 2, can find out that this doping content reduces gradually; GH section corresponds to the doping content as the described silicon chip 1 of described bottom auxiliary layer; The doping content of the corresponding described N-type resilient coating 9 of HI section; IJ section corresponds to the doping content of described N+ contact layer 8.
As shown in Figure 4, be the device architecture figure that the embodiment of the present invention three method is formed.The difference part of the embodiment of the present invention three super junction-semiconductor device manufacture method and the embodiment of the present invention one method is:
The described super junction-semiconductor device that the embodiment of the present invention three method is formed is half super junction IGBT device, and the embodiment of the present invention three method in step 8 is: step 8, carry out backside particulate and inject and form P+ contact layer 10; The Implantation Energy that the backside particulate of described P+ contact layer 10 injects is 10Kev ~ 50Kev, implantation dosage 1e12cm
-2~ 1e15cm
-2.Other step of the embodiment of the present invention three method and the identical of the embodiment of the present invention two.
Figure shown in dotted line frame 103 in Fig. 4 is the doping content curve at the KK dotted line place along Fig. 4, and LM section corresponds to the doping content of described first conduction type diffusion region 2, can find out that this doping content reduces gradually; MN section corresponds to the doping content as the described silicon chip 1 of described bottom auxiliary layer; The doping content of the corresponding described N-type resilient coating 9 of NO section; OP section corresponds to the doping content of described P+ contact layer 10, and wherein OP section is the doping of P type, and other section is all N-type doping.
The embodiment of the present invention four method can be obtained by carrying out corresponding change to the embodiment of the present invention three method, in the embodiment of the present invention four method, after step 6, described silicon chip 1 is no longer comprised in the bottom of super-junction structures, described silicon chip 1 is not namely had as BAL layer yet, whole drift is trivial to be all made up of super level structure, makes the last described super junction-semiconductor device formed be super junction IGBT device.
The embodiment of the present invention five method can be obtained by carrying out corresponding change to the embodiment of the present invention three method, in the embodiment of the present invention five method, also need to carry out the injection of N+ district at selection area in step 8, N+ district is also connected with the back metal of follow-up formation, like this can in IGBT device a fast recovery diode in parallel thus form half super junction against conductivity type IGBT device.
The embodiment of the present invention six method can be obtained by carrying out corresponding change to the embodiment of the present invention four method, in the embodiment of the present invention six method, also need to carry out the injection of N+ district at selection area in step 8, N+ district is also connected with the back metal of follow-up formation, like this can in IGBT device a fast recovery diode in parallel thus form super junction against conductivity type IGBT device.
Above by specific embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (10)
1. a super junction-semiconductor device manufacture method, is characterized in that, comprises the steps:
Step one, at N-grown above silicon first oxide-film, on described silicon chip, inject the first conductive type impurity through described first oxide-film;
Step 2, diffusion knot is carried out to the first injected conductive type impurity and forms the first conduction type diffusion region; From described silicon chip surface to the bottom of described first conduction type diffusion region, the doping content of described first conduction type diffusion region reduces gradually;
Step 3, employing lithographic etch process form multiple groove in described first conduction type diffusion region, and the first conduction type thin layer be made up of described first conduction type diffusion region between described groove and each described groove forms the structure be alternately arranged; The Sidewall angles of each described groove is 86 degree ~ 88 degree, and the width of each described groove is reduced from the top to the bottom step by step;
Step 4, adopt epitaxial growth technology in each described groove, fill the second conductive type epitaxial layer of Uniform Doped, the second conduction type thin layer is formed by the second conductive type epitaxial layer in each described groove, super-junction structures is formed by the described first conduction type thin layer be alternately arranged and described second conduction type thin layer, utilize the charge matching that the doping content of described first conduction type thin layer reduces from the top to the bottom step by step and the width of described second conduction type thin layer reduces from the top to the bottom step by step characteristic realizes between described first conduction type thin layer and described second conduction type thin layer.
2. super junction-semiconductor device manufacture method as claimed in claim 1, is characterized in that, also comprise following front processing step:
Step 5, formation grid oxygen, polysilicon gate, P type channel region, source region, interlayer film, contact hole, front metal and passivation layer.
3. super junction-semiconductor device manufacture method as claimed in claim 2, it is characterized in that, described super junction-semiconductor device is super junction MOSFET element, also comprises following back process step:
Step 6, thinning back side is carried out to described silicon chip;
Step 7, carry out backside particulate and inject and form N-type resilient coating;
Step 8, carry out backside particulate and inject and form N+ contact layer;
Step 9, described N-type resilient coating and described N+ contact layer carried out to annealing and activate;
Step 10, formation back metal.
4. super junction-semiconductor device manufacture method as claimed in claim 2, it is characterized in that, described super junction-semiconductor device is super junction IGBT device, also comprises following back process step:
Step 6, thinning back side is carried out to described silicon chip;
Step 7, carry out backside particulate and inject and form N-type resilient coating;
Step 8, carry out backside particulate and inject and form P+ contact layer;
Step 9, described N-type resilient coating and described P+ contact layer carried out to annealing and activate;
Step 10, formation back metal.
5. super junction-semiconductor device manufacture method as claimed in claim 1, is characterized in that: the Implantation Energy of the first conductive type impurity described in step one is 20Kev ~ 2Mev, implantation dosage 5e11cm
-2~ 5e13cm
-2.
6. super junction-semiconductor device manufacture method as claimed in claim 1, is characterized in that: the temperature spreading knot in step 2 is 1200 DEG C ~ 1300 DEG C; The junction depth of described first conduction type diffusion region is 10 microns ~ 50 microns.
7. the super junction-semiconductor device manufacture method as described in claim 3 or 4, is characterized in that: in step 6 by described wafer thinning to 20 microns ~ 80 microns.
8. the super junction-semiconductor device manufacture method as described in claim 3 or 4, is characterized in that: the Implantation Energy that the backside particulate of the resilient coating of N-type described in step 7 injects is 200Kev ~ 10Mev, implantation dosage 5e10cm
-2~ 5e13cm
-2.
9. super junction-semiconductor device manufacture method as claimed in claim 3, is characterized in that: the Implantation Energy that the backside particulate of the contact layer of N+ described in step 8 injects is 10Kev ~ 100Kev, implantation dosage 1e14cm
-2~ 1e16cm
-2.
10. super junction-semiconductor device manufacture method as claimed in claim 4, is characterized in that: the Implantation Energy that the backside particulate of the contact layer of P+ described in step 8 injects is 10Kev ~ 50Kev, implantation dosage 1e12cm
-2~ 1e15cm
-2.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107134492A (en) * | 2016-02-26 | 2017-09-05 | 苏州东微半导体有限公司 | Super junction power device and its manufacture method |
| WO2019047988A1 (en) * | 2017-09-07 | 2019-03-14 | 无锡华润上华科技有限公司 | Transversely two-way diffused metal oxide semiconductor component and manufacturing method therefor |
| CN115020478A (en) * | 2022-08-08 | 2022-09-06 | 北京芯可鉴科技有限公司 | Transverse double-diffusion field effect transistor, manufacturing method, chip and circuit |
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| CN102194700A (en) * | 2010-03-15 | 2011-09-21 | 富士电机系统株式会社 | Manufacturing method of super-junction semiconductor device |
| US20110241111A1 (en) * | 2010-03-31 | 2011-10-06 | Renesas Electronics Corporation | Semiconductor device |
| CN103681779A (en) * | 2012-09-11 | 2014-03-26 | 无锡华润上华半导体有限公司 | Field effect transistor structure and manufacturing method thereof |
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| US11227948B2 (en) | 2017-09-07 | 2022-01-18 | Csmc Technologies Fab2 Co., Ltd. | Lateral double-diffused metal oxide semiconductor component and manufacturing method therefor |
| CN115020478A (en) * | 2022-08-08 | 2022-09-06 | 北京芯可鉴科技有限公司 | Transverse double-diffusion field effect transistor, manufacturing method, chip and circuit |
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