CN109994550A - A kind of trough grid superjunction MOS device - Google Patents

A kind of trough grid superjunction MOS device Download PDF

Info

Publication number
CN109994550A
CN109994550A CN201711490285.1A CN201711490285A CN109994550A CN 109994550 A CN109994550 A CN 109994550A CN 201711490285 A CN201711490285 A CN 201711490285A CN 109994550 A CN109994550 A CN 109994550A
Authority
CN
China
Prior art keywords
mos device
layer
ion implanting
ion
present
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201711490285.1A
Other languages
Chinese (zh)
Inventor
李泽宏
王为
谢驰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Guizhou Hengxin Microelectronics Technology Co Ltd
Original Assignee
Guizhou Hengxin Microelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Guizhou Hengxin Microelectronics Technology Co Ltd filed Critical Guizhou Hengxin Microelectronics Technology Co Ltd
Priority to CN201711490285.1A priority Critical patent/CN109994550A/en
Publication of CN109994550A publication Critical patent/CN109994550A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors

Abstract

A kind of trough grid superjunction MOS device proposed by the present invention, by the first time outer ion implanting delayed and second it is outer delay ion and instead expand form buried layer, and it is connected to form P column with the ion implantation doping layer after slot grid etching, to form the alternate super-junction structure of P/N column with epitaxial layer.Device architecture proposed by the present invention compares traditional Trench MOS device with higher breakdown voltage, lower than conducting resistance, and the ion implantation doping layer after deep etching has groove gate oxide and alleviates electric field action, improves reliability of the gate oxide.Superjunction MOS structure manufacturing process of the present invention is easy, with traditional Trench MOS device process compatible, only increases ion implanting twice, overcomes cumbersome, the with high costs disadvantage of current superjunction devices manufacturing process.

Description

A kind of trough grid superjunction MOS device
Technical field
The invention belongs to power semiconductor device technology fields, and in particular to a kind of trough grid superjunction MOS device.
Background technique
Superjunction MOS device provides laterally electricity by introducing p-type and the alternately arranged junction type Withstand voltage layer of N-type in its drift region , the new relation of breakdown voltage Yu conducting resistance Ron ∝ BV1.33 is obtained, has broken the silicon substrate MOS device limit, has greatly improved The breakdown voltage of MOS device reduces forward conduction loss.
There are mainly two types of manufacturing methods for current superjunction MOS device: first is that inject to form super-junction structure by multiple extension, it should Method and process is simple, but process is cumbersome, and time cost is higher；Second is that being completed by deep etching and filling, this method is simpler Just, but need to introduce high aspect ratio equipment, higher cost.
The present invention proposes a kind of trough grid superjunction MOS device, can be in current tradition Trench MOS process equipment On the basis of complete the manufacture of superjunction, under conditions of guaranteeing device high-breakdown-voltage, low on-resistance parameter, significantly simplified technique Process saves production cost.
Summary of the invention
The technical problems to be solved by the invention are to propose a kind of trough grid superjunction MOS device, to overcome current main-stream The disadvantages of superjunction manufacturing approach craft complexity, higher cost.
For the two methods for solving current manufacture superjunction MOS device: multiple extension is injected and deep plough groove etched filling technique The shortcomings that complex process, higher cost, the present invention propose a kind of manufacturing method of New Low Voltage slot grid superjunction MOS device.In life Foreign ion injection once opposite with epitaxial material doping type is done when producing power MOS epitaxial wafer, continuation later is outer to be extended down to institute The epitaxy layer thickness needed.Try again ion implanting after having dug deep trouth, doping and the ion same type of outer Delay injection Impurity grows gate oxide so that the Doped ions injected twice are connected to form alternately arranged P/N column later, by tradition The process flow manufacture of Trench MOS finishes, i.e. the manufacture of completion superjunction MOS device.The structure is remarkably improved hitting for device Voltage is worn, reduces the ratio conducting resistance of device, and for N-channel superjunction MOS device, the P column under Trench is conducive to alleviate The electric field of Cao Shan corner improves reliability of the gate oxide.
The technical scheme is that a kind of trough grid superjunction MOS device, including metallization drain terminal electrode 1, N+ substrate 2, the N- epitaxial layer 5 above N+ substrate 2, outer delay, which is injected by primary ions and instead expanded, forms buried layer 3, has etched deep trouth The doped layer 4 that ion implanting is formed afterwards, thermally grown gate oxide 6, the heavily doped polysilicon 7 of deposit, on the N- epitaxial layer Portion two sides are the area PXing Ti 8, are provided with mutually independent N+ source region 9 in the area the P Xing Ti 8, the boron-phosphorosilicate glass 10 of deposit, on Surface metalation source electrode 11.
The doped layer 4 that the anti-buried layer 3 for expanding formation of ion implanting extension and ion implanting are formed is connected and forms with epitaxial layer 5 The alternate super-junction structure of P/N column.
Beneficial effects of the present invention are a kind of trough grid superjunction MOS device, the alternately arranged junction type Withstand voltage layer of P/N column The longitudinal field plate formed with deep trench provides a transverse electric field to device drift region, significantly improves the breakdown potential of device Pressure, and reduce the conducting resistance of device, reduce power consumption when device forward conduction.The present invention passes through to be infused using outer delay ion Enter the anti-P column for expanding the ion implanting done after complete with etching groove and being formed in super-junction structure, enormously simplifies the system of superjunction MOS device It makes process, complex process degree and reduces costs.The doped layer that ion implanting is formed after deep etching simultaneously can be to gate oxidation Layer plays a protective role, and improves the reliability of component grid oxidizing layer.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of embodiment 1；
Fig. 2-1 be in the committed step manufacturing process of the present embodiment on N+ substrate extension N- layers of first time of molding figure；
Fig. 2-2 is that mask plate does a P-type ion injection moulding figure in the committed step manufacturing process of the present embodiment；
Fig. 2-3 is in the committed step manufacturing process of the present embodiment into buried layer molding figure；
Fig. 2-4 be remake after having etched deep trouth in the committed step manufacturing process of the present embodiment one or many p-types from Sub- injection moulding figure；
It forms and schemes with p type buried layer after one or many ion implantings in the committed step manufacturing process of Fig. 2-5 the present embodiment.
Specific embodiment
A kind of trough grid superjunction MOS device proposed by the present invention only increases by two on the basis of traditional Trench MOS structure Secondary ion injection, can get high-breakdown-voltage, the low superjunction MOS device than conducting resistance.
Embodiment:
As shown in Figure 1, being a kind of structural schematic diagram of trough grid superjunction MOS device proposed by the present invention.Including metal Change drain terminal electrode 1, N+ substrate 2, the N- epitaxial layer 5 positioned at N+ substrate 2 above, outer delay is injected by primary ions and counter expands shape At buried layer 3, the doped layer 4 of ion implanting formation after deep trouth, thermally grown gate oxide 6, the heavy doping polycrystalline of deposit have been etched Silicon 7, N- epitaxial layer top two sides are the area PXing Ti 8, are provided with mutually independent N+ source region 9 in the area PXing Ti 8, deposit Boron-phosphorosilicate glass 10, upper surface metallizing source 11.
The present invention has the manufacturing process mutually compatible with traditional TrenchMOS device, and increased processing step is realized more It is simple and reliable, but there is breakdown voltage more higher than traditional Trench MOS device, it is lower than conducting resistance and more robust Reliability of the gate oxide.
Fig. 2-1 to 2-5 is the committed step manufacturing flow chart of the present embodiment.Fig. 2-1 is the first time extension on N+ substrate N- layers, Fig. 2-2 is to do a P-type ion using mask plate to inject, and Fig. 2-3 is to continue extension N- layers to required thickness, ion note The p type impurity entered, which instead expands, forms buried layer 3, and Fig. 2-4 is that one or many P-type ion injections, Fig. 2-5 are remake after having etched deep trouth For superjunction P column is connected to form after one or many ion implantings with p type buried layer.The device presses tradition Trench MOS process later Manufacture.
The solution of the present invention is suitable for P-channel trough grid superjunction MOS device simultaneously.Body can be used in the semiconductor material Silicon, silicon carbide, GaAs, indium phosphide or germanium silicon.
Although the present invention is described in detail referring to the foregoing embodiments, for those skilled in the art, It is still possible to modify the technical solutions described in the foregoing embodiments, or part of technical characteristic is carried out etc. With replacement, all within the spirits and principles of the present invention, any modification, equivalent replacement, improvement and so on should be included in this Within the protection scope of invention.

Claims (3)

1. a kind of trough grid superjunction MOS device, it is characterised in that: including metallization drain terminal electrode (1), N+ substrate (2), be located at N- epitaxial layer (5) above N+ substrate (2), outer delay, which is injected by primary ions and instead expanded, forms buried layer (3), has etched deep trouth The doped layer (4) that ion implanting is formed afterwards, thermally grown gate oxide (6) and the heavily doped polysilicon (7) deposited, outside the N- Prolonging floor top two sides is the area PXing Ti (8), is provided with mutually independent N+ source region (9), the boron phosphorus of deposit in the area PXing Ti (8) Silica glass (10) and upper surface metallizing source (11).
2. trough grid superjunction MOS device according to claim 1, it is characterised in that: ion implanting extension is counter to expand to be formed Buried layer 3 and ion implanting formed doped layer 4 be connected and with epitaxial layer 5 form the alternate super-junction structure of P/N column.
3. trough grid superjunction MOS device according to claim 1 or 2, it is characterised in that: the semiconductor material can be adopted With body silicon, silicon carbide, GaAs, indium phosphide or germanium silicon.
CN201711490285.1A 2017-12-30 2017-12-30 A kind of trough grid superjunction MOS device Pending CN109994550A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201711490285.1A CN109994550A (en) 2017-12-30 2017-12-30 A kind of trough grid superjunction MOS device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201711490285.1A CN109994550A (en) 2017-12-30 2017-12-30 A kind of trough grid superjunction MOS device

Publications (1)

Publication Number Publication Date
CN109994550A true CN109994550A (en) 2019-07-09

Family

ID=67111487

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201711490285.1A Pending CN109994550A (en) 2017-12-30 2017-12-30 A kind of trough grid superjunction MOS device

Country Status (1)

Country Link
CN (1) CN109994550A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114242768A (en) * 2021-11-18 2022-03-25 深圳真茂佳半导体有限公司 Silicon carbide MOSFET device with improved gate bottom charge balance and manufacturing method thereof
CN116666222A (en) * 2023-07-28 2023-08-29 江西萨瑞半导体技术有限公司 Trench MOS device and preparation method thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060244054A1 (en) * 2005-04-28 2006-11-02 Nec Electronics Corporation Semiconductor device
US20070114599A1 (en) * 2005-11-23 2007-05-24 M-Mos Sdn. Bhd. High density trench MOSFET with reduced on-resistance
US20110049614A1 (en) * 2009-08-27 2011-03-03 Vishay-Siliconix Super junction trench power mosfet devices
CN107170688A (en) * 2017-07-14 2017-09-15 邓鹏飞 A kind of slot type power device and preparation method thereof
CN207993871U (en) * 2017-12-30 2018-10-19 贵州恒芯微电子科技有限公司 A kind of trough grid superjunction MOS device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060244054A1 (en) * 2005-04-28 2006-11-02 Nec Electronics Corporation Semiconductor device
US20070114599A1 (en) * 2005-11-23 2007-05-24 M-Mos Sdn. Bhd. High density trench MOSFET with reduced on-resistance
US20110049614A1 (en) * 2009-08-27 2011-03-03 Vishay-Siliconix Super junction trench power mosfet devices
CN107170688A (en) * 2017-07-14 2017-09-15 邓鹏飞 A kind of slot type power device and preparation method thereof
CN207993871U (en) * 2017-12-30 2018-10-19 贵州恒芯微电子科技有限公司 A kind of trough grid superjunction MOS device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114242768A (en) * 2021-11-18 2022-03-25 深圳真茂佳半导体有限公司 Silicon carbide MOSFET device with improved gate bottom charge balance and manufacturing method thereof
CN116666222A (en) * 2023-07-28 2023-08-29 江西萨瑞半导体技术有限公司 Trench MOS device and preparation method thereof

Similar Documents

Publication Publication Date Title
CN105185825A (en) Injection Control In Semiconductor Power Devices
CN104716177B (en) A kind of manufacture method for the radio frequency LDMOS device for improving electric leakage
CN102376762B (en) Super junction LDMOS(Laterally Diffused Metal Oxide Semiconductor) device and manufacturing method thereof
CN102044563A (en) LDMOS (laterally diffused metal oxide semiconductor) device and manufacturing method thereof
CN106298935B (en) LDMOS device and its manufacturing method
CN109686781B (en) Method for manufacturing super junction device by multiple epitaxy
CN106098777A (en) A kind of splitting bar accumulation type DMOS device
CN108461537A (en) A kind of trench gate charge storage type IGBT and preparation method thereof
CN106158973A (en) A kind of accumulation type DMOS
CN110504310A (en) A kind of RET IGBT and preparation method thereof with automatic biasing PMOS
CN109713029B (en) Manufacturing method of multi-time epitaxial super junction device with improved reverse recovery characteristic
CN103515443B (en) A kind of super junction power device and manufacture method thereof
CN114005877A (en) Ultrathin super-junction IGBT device and preparation method
CN109994550A (en) A kind of trough grid superjunction MOS device
CN110047930A (en) VDMOS device
CN109273534A (en) A kind of device of novel shielding gate power MOS
CN206976353U (en) A kind of channel-type semiconductor device for optimizing terminal structure
CN203288599U (en) VDMOS device of novel structure
CN108054211A (en) Trench vertical bilateral diffusion metal oxide transistor and preparation method thereof
CN104681438A (en) Forming method of semiconductor device
CN105448733A (en) Depletion type VDMOS device and manufacturing method thereof
CN109256428B (en) Fin type super junction power semiconductor transistor and manufacturing method thereof
CN105957894A (en) DMOS with composite dielectric layer structure
CN207993871U (en) A kind of trough grid superjunction MOS device
CN106057906B (en) A kind of accumulation type DMOS with p type buried layer

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination